CN112363766A - Integrated circuit ultra-low power memory content retention system, method and medium - Google Patents
Integrated circuit ultra-low power memory content retention system, method and medium Download PDFInfo
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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- G06F9/4401—Bootstrapping
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- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/325—Power saving in peripheral device
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Abstract
The invention discloses a system, a method and a storage medium for keeping the content of an integrated circuit ultra-low power consumption memory, belonging to the integrated circuit design industry. The system comprises: the system comprises a power management module, a CPU and a data handling subsystem. The data handling subsystem comprises a main memory, a nonvolatile memory, a data handling controller and a data compression and decompression module. The data transport controller is used for transporting the data in the main memory to the data compression and decompression module for compression after receiving a data transport instruction sent by the CPU, and transporting the data decompressed by the data compression and decompression module to the main memory after power-on. The data compression and decompression module is used for compressing the data in the main memory conveyed by the data conveying controller and decompressing the data in the nonvolatile memory. The invention can reduce power consumption and improve response speed without losing data.
Description
Technical Field
The present application relates to the field of integrated circuit design technologies, and in particular, to an integrated circuit ultra-low power memory content retention system, method, and medium.
Background
In embedded systems, there are very demanding requirements for low power consumption. Particularly, for the static power consumption during the silent period of the system, it is desirable that the static power consumption is as close to 0 as possible, so as to prolong the standby time in the battery-powered state. At the same time, the application demands the system to respond to the external signal and respond immediately.
One technique introduced in modern integrated circuit design is then: and (5) sleeping. This technique requires independent power supply for different parts of the integrated circuit chip, and after the system enters a sleep state, the power supply for as many parts of the system as possible is completely cut off, thereby ensuring that the power consumption of the system is very low in the sleep state, but the method sacrifices the response speed of the system.
On the premise of pursuing extremely low power consumption, the problem that the power-down power consumption of the memory cannot be 0 even by using the IP (Internet protocol) held by the memory because the data is lost after the power failure of the main memory is faced. In addition, it takes time for the contents in the main memory to be stored in the nonvolatile memory, and it also takes time for the contents to be read from the nonvolatile memory and restored to the main memory after waking up. In particular, the time to recover from memory can affect the response speed of the system. Such response speeds are often dictated by protocol or specification requirements and cannot be tolerated. In addition, the insufficient response speed in some high real-time systems can cause a very serious disaster.
Disclosure of Invention
The method for keeping the content of the integrated circuit ultra-low power consumption memory solves the problems that data loss can be caused after the main memory is powered off, the power-down power consumption of the memory cannot be 0 even if the IP kept by the memory is used, and the response speed is low.
In order to solve the above problems, the present invention adopts a technical solution that: the integrated circuit ultra-low power consumption memory content holding system comprises a power management module, a CPU and a data handling subsystem. The data handling subsystem comprises a main memory, a nonvolatile memory, a data handling controller and a data compression and decompression module. The data transport controller is used for transporting the data in the main memory to the data compression and decompression module for compression after receiving a data transport instruction sent by the CPU; and carrying the data decompressed by the data compression and decompression module to the main memory after the power is on. The data compression and decompression module is used for compressing the data in the main memory conveyed by the data conveying controller and decompressing the read data in the nonvolatile memory. The data handling controller is directly connected to the main memory, and the data handling controller is directly connected to the non-volatile memory. After the CPU sends out a data transport command, the integrated circuit only keeps the power supply of the data transport subsystem, and after all the data compressed by the data compression and decompression module are stored in the nonvolatile memory, the power supply of the data transport subsystem is interrupted. After the power management module receives the system recovery request, the power of the data carrying subsystem is firstly turned on, and after the data carrying subsystem carries the data decompressed by the data compression and decompression module to the main memory, the power of other modules except the data carrying subsystem in the integrated circuit is turned on. The data compression and decompression module compresses the data in the main memory transported by the data transport controller and decompresses the read data in the nonvolatile memory, and the decompression or compression is performed by using an LZ4 algorithm and a data stream format after removing a data head and a checksum by using a standard LZ4 data stream format.
The invention adopts another technical scheme that: a method for keeping the content of an integrated circuit ultra-low power consumption memory is provided. It includes: a data reading step, namely, carrying the data in the main memory to a data compression and decompression module by using a data carrying controller according to a data carrying instruction sent by a CPU (Central processing Unit), compressing the data in the main memory by using the data compression and decompression module, and storing the compressed data in a nonvolatile memory; and a data writing step, reading the data in the nonvolatile memory into a data compression and decompression module according to a recovery request of the system, decompressing the data in the nonvolatile memory by using the data compression and decompression module, and transporting the decompressed data into the main memory by using the data transport controller.
In another aspect of the present application, a computer-readable storage medium is provided that stores computer instructions, wherein the computer instructions are operable to perform a method of integrated circuit ultra-low power memory content retention in an aspect.
The beneficial effect that this application technical scheme can reach is: the computer system reduces the power consumption on the premise of not losing data when entering a sleep or wake-up state, improves the response speed of the system, reduces the wake-up delay of the system, realizes lossless and efficient compression, and meets the application requirement with strict time requirement.
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FIG. 1 is a diagram of an embodiment of an integrated circuit ultra low power memory content retention system according to the invention;
FIG. 2 is a diagram illustrating an embodiment of an LZ4 algorithm used by the data compression and decompression module according to the present invention;
FIG. 3 is a diagram of another embodiment of a method for maintaining contents of an integrated circuit ultra-low power memory according to the present invention.
Detailed Description
The following detailed description of the preferred embodiments of the present invention, taken in conjunction with the accompanying drawings, will make the advantages and features of the invention easier to understand by those skilled in the art, and thus will clearly and clearly define the scope of the invention.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
With the high-speed development of computer systems, the requirement for low power consumption is higher and higher, and it is desirable that the static power consumption is as close to 0 as possible. The standby time in the battery-powered state can be prolonged, and the application requirements require the system to respond to external signals and respond immediately. And the computer system has the problems of data loss after the main power failure and slow response speed when reading and writing a large amount of data.
FIG. 1 is a diagram of an embodiment of an integrated circuit ultra-low power memory content retention system according to the invention.
In this particular embodiment, an integrated circuit ultra-low power memory content retention system includes: the system comprises a power management module, a CPU and a data handling subsystem. Further comprising:
the data handling subsystem comprises a main memory, a nonvolatile memory, a data handling controller and a data compression and decompression module.
The data transport controller is used for transporting the data in the main memory to the data compression and decompression module for compression after receiving a data transport instruction sent by the CPU; and carrying the data decompressed by the data compression and decompression module to the main memory after the power is on.
And the data compression and decompression module is used for compressing the data in the main memory conveyed by the data conveying controller and decompressing the read data in the nonvolatile memory.
In one embodiment of the invention, the data handling subsystem includes a main memory RAM, a non-volatile memory FLASH, a data handling controller, a data compression and decompression module, a memory controller, a bus controller, and the like during the design of the integrated circuit. The memory controller converts commands such as read and write commands issued by the memory device into recognizable signals, and the bus controller manages the use of the bus.
In one embodiment of the invention, the data handling controller is directly connected to the main memory RAM and the data handling controller is directly connected to the non-volatile memory FLASH. The middle does not pass through other logic modules except the data compression and decompression module, so that the data handling controller has the capability of reading 4 bytes per clock cycle. The non-bus circuit is adopted to avoid the risk of bus waiting delay, so that the reading path of the main memory RAM reaches the theoretical limit bandwidth, the carrying speed is improved, and the working time is shortened. The data transfer controller is directly connected with the nonvolatile memory, so that only the data transfer controller carries out data transfer work between the main memory RAM and the nonvolatile memory, and the data compression and decompression module can complete the read/write of the main memory RAM within 1 clock cycle, so that an additional cache circuit is not needed.
In an embodiment of the invention, the data compression and decompression module uses an LZ4 algorithm to perform data compression and decompression, the LZ4 algorithm focuses more on the compression and decompression speed, and completes matching search and coding with minimum steps, thereby increasing the bandwidth of the data stream as much as possible.
In one embodiment of the invention, the non-volatile memory FLASH has the capability of 4-line parallel operation. In the prior art, it is possible to read/write 4-bit data at most in one cycle for the non-volatile memory FLASH, i.e. it takes a minimum of 8 clock cycles for the data retrieved from the main memory RAM in one cycle to be written into the non-volatile memory FLASH, and vice versa, if the time consumed for the preparation operation is not taken into account. A roughly estimated 8KB amount of data requires 250us of time to operate at a clock frequency of 64 MHz. A large amount of power in 250us of time is consumed in the operation of the non-volatile memory FLASH, and the operation speed of the non-volatile memory FLASH is determined by the process structure and cannot be changed in most scenes. Therefore, the data amount needing to be read and written by the nonvolatile memory FLASH is reduced through data compression, the whole process is accelerated, and the purpose of saving power consumption is achieved.
In a specific embodiment of the invention, before the computer goes to sleep, after the data handling controller receives a data handling instruction sent by the CPU, the power management module interrupts power of other parts of the computer system except the data handling subsystem, the data handling controller starts to operate, the data handling controller compresses the data stored in the main memory RAM by the LZ4 algorithm, a compressed packet obtained after compression is written into the non-volatile memory FLASH, and after all the data stored in the main memory RAM are handled and stored in the non-volatile memory FLASH, the data compression operation is completed, at this time, the data handling subsystem is powered off, and the computer goes to sleep. The process is convenient for the computer to sleep without data loss.
In a specific embodiment of the present invention, when the computer needs to wake up, after the power management module receives a system recovery request triggered by an integrated circuit or an external signal, the power of the data handling subsystem is turned on first, the data compression and decompression module decompresses the data stored in the read nonvolatile memory FLASH through an algorithm, decompresses the data to obtain the source data before compression, the source data carries the data stored in the decompressed nonvolatile memory FLASH to the main memory RAM through the data handling controller, carries and stores all the data stored in the nonvolatile memory FLASH to the main memory RAM, the data decompression is completed, at this time, the other subsystems such as the CPU of the computer are powered on, and the computer wakes up to enter a working state. The process is convenient for the data to be quickly recovered after the computer is awakened.
FIG. 2 is a diagram of an embodiment of the data compression and decompression module using LZ4 algorithm
In this embodiment, the data compression and decompression module uses the LZ4 algorithm to perform data compression and decompression. When two RAMs are arranged in an integrated circuit, double RAM bandwidth can be directly obtained, RAM0 mainly stores source data, the rest space is used for buffering, RAM1 is used for storing a hash table of LZ4 algorithm matching characters and distances, and LZ4 algorithm searches matching character strings by calculating the hash table. The hash table represents a mapping relationship using a structure of (Key). Key is a binary number of 4 bytes. Value is 4 bytes to indicate the location of the data in the data block.
In this particular embodiment, the data block format of the LZ4 algorithm includes: 1 byte token, 0-N byte character string length identification, 0-M byte uncompressed character string, 2 byte offset and 0-Z byte matching length. The LZ4 algorithm uses a sliding window and a read-ahead buffer to achieve data compression and decompression. The pre-read buffer is used to hold the first 4 bytes of the current input data, i.e. 32bits, which is exactly the width of one RAM read. And then, after the 4 bytes are subjected to hash calculation, judging whether the current byte appears in a sliding window once. Matching may be performed if it has appeared in the sliding window. And then continue the sliding window search backwards. After the whole sliding is finished, the distance between the current byte and the byte appearing before is used for representing the actual data, thereby realizing the compression of the data. After the LZ4 algorithm compresses, the data volume is generally about 1/2-1/3 of the original data volume, and the sleep/recovery time of the whole system can be shortened to be within 150 us.
In this particular embodiment, the width of the sliding window in the LZ4 algorithm is variable. The longer the window, the higher the compression ratio on average. Typically this window may be 20 bytes or tens of KB in length. Longer windows require increased time to traverse the sliding window. The storage space required by the hash table is also increased, and the probability of hash collision is also increased. The width of the selected sliding window is therefore the minimum amount of data saved, 8KB, and compression can be accomplished with one sliding at the time of the minimum amount of data.
In this embodiment, the hash algorithm requires that the size of the hash-computed data block be specified first. I.e. compress the data with page. The size of a Page is typically 4KB to 32 KB. Therefore, 8KB with the same size as the sliding window can be directly used as an operation object of the single page. After the hash calculation is completed, information such as the matching distance needs to be calculated, and then the information is packaged and stored in a non-volatile memory FLASH.
In this embodiment, when decompression is performed, since the data stored in the nonvolatile memory FLASH is continuous stream information, the data amount not exceeding 8KB is read at a time and stored in the RAM buffer, and then decompression is started. One part of data blocks in the data are non-repeated data and are directly copied into the RAM of the original data recovery area, the other part of the data blocks are repeated data, uncompressed data segments can be quickly found through distances, and then the data blocks are copied into the RAM of the original data recovery area, and decompression is completed. The LZ4 algorithm requires a very low number of operations to decompress, so that the bottleneck of the whole system does not occur in the process of data decompression.
In this embodiment, the hash table does not need to be carried. It is dynamically generated and erased, stored in main memory RAM, and discarded after use.
FIG. 3 is a diagram of another embodiment of a method for maintaining contents of an integrated circuit ultra-low power memory according to the present invention.
In this embodiment, the method for maintaining the content of the ultra-low power memory of the integrated circuit mainly includes: a method for keeping the content of an integrated circuit ultra-low power consumption memory is provided. It includes: and a data reading step, wherein before the computer goes to sleep, the data transport controller receives a data transport instruction sent by the CPU, transports the data in the main memory to a data compression and decompression module for compression, and writes the compressed data in the main memory into a nonvolatile memory. And a data writing step, when the computer needs to be awakened, after the power management module receives a system recovery request triggered by an integrated circuit or an external signal, the data compression and decompression module decompresses by reading data in the nonvolatile memory, and the decompressed data in the nonvolatile memory is transported to the main memory through the data transport controller.
In an embodiment of the present invention, the method for maintaining contents of an integrated circuit ultra-low power consumption memory of the present application includes a process S101, and the data reading step includes: before the computer enters sleep, after the data handling controller receives a data handling instruction sent by the CPU, the power management module interrupts other parts of power supply of the computer system except the data handling subsystem. The data transport controller transports the data in the main memory to a data compression and decompression module for compression, the data compression and decompression module compresses the data in the main memory RAM by adopting an LZ4 algorithm, an LZ4 algorithm compresses the data in the main memory RAM by matching characters and distances, and the compressed data in the main memory is written into a nonvolatile memory. Since the data compression and decompression module can complete the read/write of the main memory within 1 clock cycle, no additional cache circuit is needed. In a hardware-only integrated circuit design, the CPU of the chip is powered down before going to sleep, and the main memory RAM of the chip is effectively freed up. Thus, a large amount of memory space is available to provide a lossless data compression/decompression algorithm with a dictionary of data space needed to store data for compression and decompression. The process is convenient for the computer to sleep without data loss.
In an embodiment of the present invention, the method for maintaining contents of an integrated circuit ultra-low power memory of the present application includes a process S102, and the data reading step includes: when the computer needs to be awakened, after the power management module receives a system recovery request triggered by an integrated circuit or an external signal, the data compression and decompression module decompresses by reading data in the nonvolatile memory, at the moment, the data in the nonvolatile memory is a compressed packet, and the LZ4 algorithm has low computation required for decompression, so that the bottleneck of the whole system cannot occur in the data decompression process. The LZ4 algorithm decompresses the data in the non-volatile memory FLASH through matching characters and distances, wherein a part of data blocks are non-repeated data and are directly copied into an original data recovery area RAM, the other part of data blocks are repeated data, an uncompressed data segment can be quickly found through the distances and then are copied into the original data recovery area RAM, and the decompressed data in the non-volatile memory FLASH is transferred to a main memory RAM through a data transfer controller. The process is convenient for the data to be quickly recovered after the computer is awakened.
The integrated circuit ultra-low power consumption memory content holding system provided by the invention can be used for executing the integrated circuit ultra-low power consumption memory content holding method described in any embodiment, and the implementation principle and the technical effect are similar, and are not described herein again.
In another embodiment of the present invention, a computer-readable storage medium stores computer instructions, wherein the computer instructions are operable to perform the method for ultra-low power memory content retention in an integrated circuit as described in any of the embodiments.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent structural changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. An integrated circuit ultra-low power consumption memory content holding system comprises a power management module, a CPU and a data handling subsystem,
the data handling subsystem comprises a main memory, a nonvolatile memory, a data handling controller and a data compression and decompression module;
the data transport controller is used for transporting the data in the main memory to the data compression and decompression module for compression after receiving a data transport instruction sent by the CPU; after the power is switched on, the data decompressed by the data compression and decompression module are transported to the main memory;
the data compression and decompression module is used for compressing the data in the main memory carried by the data carrying controller and decompressing the data in the nonvolatile memory.
2. The integrated circuit ultra-low power memory content retention system of claim 1, wherein the integrated circuit only retains power to the data handling subsystem after the CPU issues a data handling instruction.
3. The integrated circuit ultra-low power consumption memory content retention system according to claim 1, wherein the power supply to the data handling subsystem is interrupted after all the data compressed by the data compression and decompression module is stored in the non-volatile memory.
4. The integrated circuit ultra-low power memory content retention system of claim 1, wherein the data-handling controller is directly connected to the main memory and the data-handling controller is directly connected to the non-volatile memory.
5. The integrated circuit ultra-low power memory content retention system of claim 1, wherein the power management module first powers on the data handling subsystem after receiving a system resume request.
6. The system of claim 1, wherein after the data transport subsystem transports the decompressed data from the data decompression module to the main memory, power is turned on to other modules of the integrated circuit except the data transport subsystem.
7. The integrated circuit ultra-low power memory content retention system of claim 1, wherein the data compression and decompression module compresses data in the main memory carried by a data transport controller and decompresses read data in the non-volatile memory, including decompressing or compressing according to LZ4 algorithm.
8. The integrated circuit ultra-low power memory content retention system of claim 7, wherein said process of decompressing or compressing according to the LZ4 algorithm comprises,
the data stream format is decompressed or compressed using the standard LZ4 data stream format after the removal of the data header and checksum.
9. A method for keeping the content of an integrated circuit ultra-low power consumption memory is characterized by comprising the following steps,
a data reading step, namely, carrying data in a main memory to the data compression and decompression module by using a data carrying controller according to a data carrying instruction sent by a CPU, compressing the data in the main memory by using the data compression and decompression module, and storing the compressed data in a nonvolatile memory; and the number of the first and second groups,
and a data writing step, namely reading the data in the nonvolatile memory into the data compression and decompression module according to a recovery request of a system, decompressing the data in the nonvolatile memory by using the data compression and decompression module, and carrying the decompressed data into the main memory by using the data carrying controller.
10. A computer readable storage medium storing computer instructions, wherein the computer instructions are operative to perform the integrated circuit ultra low power memory content retention method of claim 9.
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