CN105093979B - Failure safe arithmetic processing apparatus - Google Patents
Failure safe arithmetic processing apparatus Download PDFInfo
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- CN105093979B CN105093979B CN201510260992.6A CN201510260992A CN105093979B CN 105093979 B CN105093979 B CN 105093979B CN 201510260992 A CN201510260992 A CN 201510260992A CN 105093979 B CN105093979 B CN 105093979B
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- operational part
- power supply
- failure safe
- safe arithmetic
- processing apparatus
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0428—Safety, monitoring
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1629—Error detection by comparing the output of redundant processing systems
- G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1629—Error detection by comparing the output of redundant processing systems
- G06F11/1633—Error detection by comparing the output of redundant processing systems using mutual exchange of the output between the redundant processing components
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0796—Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1608—Error detection by comparing the output signals of redundant hardware
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
- G06F11/182—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits based on mutual exchange of the output between redundant processing components
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/2015—Redundant power supplies
Abstract
The present invention provides a kind of failure safe arithmetic processing apparatus.In the failure safe arithmetic processing apparatus of the output control part of the result with multiple operational parts and each operational part of verification, in the temporary voltage variation due to power supply, when each operational part exports identical wrong data simultaneously, output control part exports the data of mistake to outside with keeping intact with possibly can not detecting the wrong data of each operational part.Multiple operational parts for forming failure safe arithmetic processing apparatus independently supply any one power supply in multiple power supplys of electric power in addition to corresponding operational part supply electric power respectively, the circuit part supply electric power beyond operational part also to forming failure safe arithmetic processing apparatus.In addition, at least one power supply in multiple power supplys is set to turn into different power supply capacitys in the lump.
Description
Technical field
Used the present invention relates to a kind of in the field for requiring high security, internally with multiple operational parts, using guarantor
Demonstrate,prove the safe arithmetic processing apparatus of multiple system failure of the consistent failsafe configuration of its operation result.
Background technology
The field of high security is required in railway signaling safety system, power station etc., the system for carrying out calculation process will
Operational part multiplex comes with reference to its result, continues normal action if consistent, is performed if inconsistent a succession of
Control so as to being transferred to safe state as system.
Therefore, it is necessary to the reason for excluding multiple operational parts while carrying out the output of identical mistake.As one of its reason,
Interim variation in voltage with power supply.In patent document 1 and patent document 2, electricity is separately supplied to multiple operational parts
Source.The probability for the failure that simultaneously identical type occurs for power supply is low, therefore can reduce the failure operational part due to power supply while enter
The probability of the output of row identical mistake.
But in the power supply being supplied separately to while when producing same variation in voltage, operational part exports identical mistake simultaneously
Data, exported to outside while the data that make mistake thus may can not be detected in output control part by mistake.In patent text
In offering 1, the CPU of folk prescription is also connected with the power supply of the opposing party to monitor the power supply of the opposing party, in addition, in documents 2, it is double
The CPU of side mutually monitors respective power supply output, thus detects the interim variation of multiple power supplys.However, it ought send out in the supply
When giving birth to interim variation in voltage, it is possible to which CPU is with will not receiving the operational stop instructions such as the reset from power monitoring portion defeated
The data to make mistake.
Patent document 1：Japanese Unexamined Patent Publication 2002-116921 publications
Patent document 2：Japanese Unexamined Patent Publication 6-298105 publications
The content of the invention
It is an object of the present invention in failure safe arithmetic processing apparatus, supplied even in multiple arithmetic processing sections
Power supply in there occurs interim variation in voltage, can also exclude the possibility of the operation result of output error.
The present invention is in order to solve above-mentioned problem, multiple operational parts difference list for forming failure safe arithmetic processing apparatus
Any one power supply in multiple power supplys of only ground supply electric power except in addition to corresponding operational part supply electric power, also to forming therefore
Hinder the circuit part supply electric power beyond the operational part of safe arithmetic processing apparatus, or make any one in above-mentioned multiple power supplys
Individual power supply turns into the power supply capacity different from other power supplys.
According to the present invention, though in the supply there occurs during interim variation in voltage, due in each operational part by electricity
The timing of the dynamic influence of buckling has differences, and can exclude above-mentioned each operational part while export the operation result of identical mistake
Situation.
Brief description of the drawings
Fig. 1 is the structure chart of the failure safe arithmetic processing apparatus of embodiment 1.
Fig. 2 is by the equivalent circuit after the circuit reduction beyond the operational part of embodiment 1 by resistance and capacitive component
Figure.
Fig. 3 is variation in voltage, clock and the output in each operational part when representing input voltage variation in embodiment 1
The figure of the time passage of data.
Fig. 4 is the structure chart of the failure safe arithmetic processing apparatus of embodiment 2.
Fig. 5 is the structure chart of the failure safe arithmetic processing apparatus of embodiment 3.
Symbol description
11st, 41,51 failure safe arithmetic processing apparatus；12 operational part A；13 operational part B；14 power supply A；15th, 45 power supply B；
16 output control parts；17 buffers；18 other circuits；52 operational part C；54 power supply C；20A system power supplies；21A system power supplies electricity
Pressure；The resistance components R of load beyond 22A system operations portionA；The all capacitive component C of 23A circuit systemsA；24A system operations
The voltage in portion；25B system power supplies；26B system power source voltages；The resistance components R of load beyond 27B system operations portionB；28B
The all capacitive component C of circuit systemB；The voltage in 29B system operations portion；30 power inputs change；In 31A system operations portion
Variation in voltage；32A system operations portion acts lower threshold voltage；33A system operations portion Action clock；34A system operations portion is defeated
Go out data；The wrong output data in 35A system operations portion；Variation in voltage in 36B system operations portion；37B system operations portion
Act lower threshold voltage；38B system operations portion Action clock；39B system operations portion output data；40B system operations portion
The output data of mistake.
Embodiment
Hereinafter, as embodiments of the present invention, 1~embodiment of embodiment 3 is illustrated in order.
(embodiment 1)
On embodiments of the invention 1,1~Fig. 3 of reference picture is illustrated.
Embodiment 1 is the failure safe arithmetic processing apparatus as multiplicated system, to carry out identical simultaneously with two
The operational part of computing, and possess the situation based on two duplex system structures with the power supply of capacity.Fig. 1 is embodiment 1
Failure safe arithmetic processing apparatus structure chart.
Failure safe arithmetic processing apparatus 11 is used for the operational part for requiring output data fail safe.Shown in Fig. 1
Structure in, in order to assure fail safe, there are operational part A (12) and operational part B (13) the two operational parts.From failure
The data that safe arithmetic processing apparatus 11 exports are based on the data calculated by operational part A (12) and operational part B (13).
Data from operational part A (12) and operational part B (13) outputs are temporarily preserved (interim storage) in output control
In buffer 17 in portion (16).Operational part A (12) and operational part B (13) mutually monitors respective output data, confirms phase
Mutual output data is equal.In the case where confirming that mutual output data is consistent, exported according to operational part A (12) instruction
The data preserved in buffer 17 in output control part 16.When at least any one party in the output data in both sides is present
In the case that the mutual Data Data of problem is inconsistent, not from the output data of buffer 17.In addition, operational part A (12) and fortune
Calculation portion B (13) has the function of sending the reset signal for stopping computing (to method, system) to subject side, is generating mutually
Output data it is inconsistent the problems such as in the case of, subject side is resetted.
The probability that operational part A (12) and operational part B (13) both sides break down simultaneously is very low, passes through such method
It is configured to carry out the failure safe arithmetic processing apparatus of failure safe output.
But for operational part A (12) and operational part B (13) while the failure cause of identical type be present
Under, there is the danger that same error signal is exported from the operational part of both sides.Then, even if operational part A (12) and computing
Portion B (13) carries out the mutual monitoring of output data, it is also possible to the mistake can not be detected, so that the letter to outside output error
Number.
Therefore, in failure safe arithmetic processing apparatus, as described above, it is necessary to strongly exclude the failure of identical type simultaneously
Reason, fully suppress the probability to outside output error signal.
As it is above-mentioned while identical type failure cause, enumerate to operational part A (12) and operational part B (13) supply
Power supply.When operational part A (12) and operational part B (13) receive power supply from public power, when being sent out in public power
When raw interim abnormal, operational part A (12) and operational part B (13) may export the data of identical mistake simultaneously.
Therefore, power supply is carried out from power supply A (14) for operational part A (12), for operational part 13 (B) from power supply B
(15) power supply is carried out.Power supply A (14) and power supply B (15) both sides produce the probability of the failure of identical type very simultaneously
It is low, so by will be separated to the power supply that operational part A (12) and operational part B (13) is supplied, the operational part of both sides can be reduced
The probability of the failure of identical type is produced simultaneously.
But when in power supply A (14) and power supply B (15) simultaneously there occurs during variation in voltage, for each power supply
Load size (including operational part A (12) and operational part B (13)) in the case of equal, while export same levels
Interim abnormal voltage.Thus, appear in operational part A (12) and operational part B (13) while produce abnormality of the same race
Possibility.Now, operational part A (12) and operational part B (13) also have even if carrying out the mutual monitoring of respective output data
The mistake of output data possibly can not be detected, so that the data to outside output error.
Therefore, in embodiment 1, even if above-mentioned abnormity of power supply occurs, in order to prevent operational part A (12) and operational part
B (13) while the data of identical mistake are exported, the as shown in Figure 1 pair of load being connected with power supply takes measures.As the measure,
Circuit (example beyond from any one in power supply A (14) or power supply B (15) to operational part A (12) and operational part B (13)
Such as, output control part 16, other circuits 18) supply power supply, thus make the size band of load variant consciously.
In order to illustrate, represent to pass through resistance and capacitive component in fig. 2 by the operational part A (12) in Fig. 1 and computing
The equivalent circuit figure after circuit (output control part 16, other circuits 18) simplification beyond portion B (13).
Fig. 2 (A) is the equivalent circuit of A circuit systems, power supply A (14) of the A system power supplies 20 equivalent to Fig. 1.Operational part A
(12) the resistance components R of the load beyondA22 by the substrate of failure safe arithmetic processing apparatus 11 and the resistance components structure of circuit
Into.The all capacitive component C of A circuit systemsA23 by the capacitive component that is included in A system power supplies 20 itself and in operational part A
(12) substrate of failure safe arithmetic processing apparatus 11 and the electric capacity of circuit of the voltage from A system power supplies 20 are supplied to beyond
Composition is formed.In addition, the input voltage E to the input voltage that operational part A (12) applies equivalent to A system operations portionCPU_A24。
Fig. 2 (B) is the equivalent circuit of B system circuit, power supply B (15) of the B system power supply 25 equivalent to Fig. 1.Operational part B
(13) the resistance components R of the load beyondB28 by the substrate of failure safe arithmetic processing apparatus 11 and the resistance components structure of circuit
Into.The all capacitive component C of B system circuitB28 by the capacitive component that is included in B system power supply 26 itself and in operational part B
(13) substrate of failure safe arithmetic processing apparatus 11 and the electric capacity of circuit of the voltage from B system power supply 25 are supplied to beyond
Composition is formed.In addition, the input voltage E to the input voltage that operational part B (13) applies equivalent to B system operational partCPU_B29。
As shown in Figure 1, the circuit being connected with the power supply A (14) of A systems is compared to the electricity being connected with power supply B (15)
Road, circuit number is few, in addition, IC used in output control part 16 and other circuits 17 etc. is born with what circuit was connected side by side
Lotus, so RA＞ RB.A system power source voltages E now is represented in figure 3in_A21 and B system supply voltagein_BDuring 26 variation
A system operations portion input voltage Ecpu_AThe 24 and input voltage Ecpu of B system operational part_B29 variation, clock with
And the relation of output data.
Pass through the variation in voltage 30 of the power supply shown in Fig. 3, Fig. 2 A system power source voltages Ein_A21 and B system power supply electricity
Press Ein_B26 also together change.Therefore, the input voltage Ecpu in Fig. 2 A system operations portion_A24 produce Fig. 3 A system operations portion
In input voltage variation 31, similarly, the input voltage Ecpu of Fig. 2 B system operational part_B29 produce Fig. 3 B system computing
Input voltage variation 36 in portion.
Here, the variation in voltage 30 of power supply is produced, from V1To V2The input voltage in A system operations portion when voltage declines
Ecpu_AThe 24 and input voltage Ecpu of B system operational part_B29 variation is represented by following formula.
ECPU_A=V2× { 1-exp (- t/RACA)}+V1× exp (- t/RACA)
ECPU_B=V2× { 1-exp (- t/RBCB)}+V1× exp (- t/RBCB)
Typically, on operational part, being designed makes it when 10% or so variation in voltage is produced also without by mistake
Action, so the action lower threshold for acting lower threshold voltage 32 and B system operational part by Fig. 3 A system operations portion
Voltage 37 is set to specified 10%.In addition, by each input voltage of A system operations portion and B system operational part due to above-mentioned electricity
Minimum value when buckling is moved and declined is set to V2, make minimum value V2Less than the action lower threshold 32 and B in A system operations portion
The action lower threshold 37 in system operations portion.
Then, the variation in voltage 31 to A system operations portion since when power input variation 30 declines is less than A systems
The time Δ t of the action lower threshold voltage 32 of operational partAAnd to B system since when power input variation 30 declines
Time Δ t of the variation in voltage 36 of operational part less than the action lower threshold voltage 37 of B system operational partBPass through following relation
Formula represents.
0.9V1=V2× { 1-exp (- Δ tA/RACA)}+V1× exp (- Δ tA/RACA)
0.9V1=V2× { 1-exp (- Δ tB/RBCB)}+V1× exp (- Δ tB/RBCB)
When obtaining Δ t according to these relational expressionsAAnd Δ tBWhen, turn into following such.
ΔtA=-RACAln{(0.9V1- V2)/(V1- V2)}
ΔtB=-RBCBln{(0.9V1- V2)/(V1- V2)}
In addition, when the frequency of A systems and the Action clock 33 and 38 of each operational part of B system is set to f [Hz],
The length of the bit of data 1 turns into 1/f [s].For opening for the wrong output data 35 in the output data 34 in A system operations portion
It is more than the bit of beginning bit offset 1 of the wrong output data 40 in the output data 39 of beginning bit and B system operational part,
Need to meet conditional as shown below.
ΔtB- Δ tA=-RBCBln{(0.9V1- V2)/(V1- V2)}+RACAln{(0.9V1- V2)/(V1- V2) ＞
1/f
According to above-mentioned condition formula, A systems and the respective resistance components of B system circuit and capacitive component (A systems are designed
And the load beyond each operational part of B system), it is met following relational expression.
RACA- RBCB[f × ln { (0.9V of ＞ 1/1- V2)/(V1- V2)}]
In addition, in order to effectively reach above-mentioned relation formula, can be to any one power supply (power supply A (14) or electricity in Fig. 1
Source B (15)) connection and the load of operational part A (12) and operational part B (13) same degree.
In the failure safe arithmetic processing apparatus 11 shown in Fig. 1, operational part A (12) and operational part B (13) are entering
The same computing of row.Then, output control part 17 confirms to come from operational part A (12) output data 34 and from operational part (13)
In output data 39 at least any one have no problem.Then, as shown in figure 4, becoming in the input voltage from power supply
When dynamic, if even if the output data 34 in A system operations portion and the output data 39 of B system operational part differ 1 bit, because by
Operational part A (12) and operational part B (13) mutually monitor respective output, are capable of detecting when the mistake of output data.
Will not mistakenly it be exported from output control part 16 from operational part A (12) and operational part B therefore, it is possible to provide one kind
(13) the failure safe arithmetic processing apparatus of the data of output.
(embodiment 2)
Embodiments of the invention 2 are characterised by, in each computing to composition failure safe arithmetic processing apparatus respectively
In each power supply unit of portion's supply electric power, make its power supply capacity that there is difference.As embodiment 2, Fig. 4 is represented in dual system
Power supply unit is the figure of the structure of different power supply capacitys in failure safe arithmetic processing apparatus (Fig. 1).
For example, power supply B (45) uses the power supply capacity power supply bigger than power supply A (14).Thus, even in power supply A (14) with
And in power supply B (45) simultaneously there occurs variation in voltage in the case of, due to making power supply capacity that there is difference, operational part can be prevented
A (12) and operational part B (13) while export identical wrong data.
(embodiment 3)
Embodiments of the invention 3 be as multiplicated system failure safe arithmetic processing apparatus be used for triplex system implementation
Example.Fig. 5 is the knot for representing to have added the failure safe arithmetic processing apparatus of power supply C (54) and operational part C (52) triplex system
The figure of structure.Operational part C (52) and operational part A (12) and operational part (B) 13 carry out same computing simultaneously.In addition, operational part A
(12), operational part B (13) and operational part C (52) has mutually monitoring output, and carry out the work(of other side's system reset respectively
Energy.
In the structure shown in Fig. 5, power supply C (54) is except in addition to operational part C (52) supply electric power, also to output control part
16 and other circuits 18 carry out power supply.Thus, power supply A (14) and power supply B (115) to each operational part (12) with
And operational part (13) carry out power supply when load with power supply C (54) progress power supply load compared with, the size of load
It is different.Of course, it is possible to substitute power supply C (54), by power supply A (14) or power supply B (15) to output control part 16 and other electricity
Road 18 carries out power supply.
Therefore, when all simultaneously variation in voltage occurs for three power supplys, operational part A (12), operational part B can be prevented
And operational part C (52) while the data of output error (13).
Claims (6)
1. a kind of failure safe arithmetic unit, it is characterised in that possess：
Multiple operational parts, it has carries out same computing simultaneously, and mutually monitors the function of output data；
Output control part, it has the output data of each operational part of interim storage, according to from the multiple operational part
In any one operational part output data from instruction to the outside each operational part for exporting the interim storage function；
The multiple power supplys set to each operational part,
Any one power supply in the multiple power supply is in addition to the corresponding operational part supply electric power also to described defeated
Go out control unit supply electric power, so that the load of the power supply in addition to any one described power supply in the multiple power supply is big
It is small of different sizes with the load of any one power supply.
2. failure safe arithmetic unit according to claim 1, it is characterised in that
It is the power supply capacity different from other power supplys to make at least one power supply in the multiple power supply.
3. failure safe arithmetic unit according to claim 1 or 2, it is characterised in that
Any one in the multiple operational part is in the case where the output data mutually monitored is consistent, to the output
Control unit sends the instruction.
4. failure safe arithmetic unit according to claim 1 or 2, it is characterised in that
The multiple operational part has the function that other the multiple operational parts are sent with reset signal respectively.
5. failure safe arithmetic unit according to claim 4, it is characterised in that
The multiple operational part in the case where the output data mutually monitored is inconsistent, sends described reset and believed respectively
Number.
6. failure safe arithmetic unit according to claim 4, it is characterised in that
The multiple operational part stops the computing of itself when receiving the reset signal respectively.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014106919A JP6600128B2 (en) | 2014-05-23 | 2014-05-23 | Arithmetic processing unit |
| JP2014-106919 | 2014-05-23 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105093979A CN105093979A (en) | 2015-11-25 |
| CN105093979B true CN105093979B (en) | 2017-11-28 |
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| JP (1) | JP6600128B2 (en) |
| CN (1) | CN105093979B (en) |
| DE (1) | DE102015208989A1 (en) |
| GB (1) | GB2526917B (en) |
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| CN110890884A (en) * | 2018-09-10 | 2020-03-17 | 台湾积体电路制造股份有限公司 | Fail-safe circuit, integrated circuit device, and method of controlling node of circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH04149743A (en) * | 1990-10-15 | 1992-05-22 | Mitsubishi Electric Corp | Driving system for data processor |
| JPH06298105A (en) * | 1993-04-15 | 1994-10-25 | Nippondenso Co Ltd | Rear wheel steering device control system |
| JP2001183490A (en) * | 1999-12-22 | 2001-07-06 | Hitachi Ltd | Reactor core flow control system |
| JP2002116921A (en) | 2000-10-06 | 2002-04-19 | Matsushita Electric Ind Co Ltd | Auxiliary device for central processing unit |
| US8143851B2 (en) * | 2008-02-15 | 2012-03-27 | Apple Inc. | Power source having a parallel cell topology |
| JPWO2011068177A1 (en) * | 2009-12-02 | 2013-04-18 | 日本電気株式会社 | Redundant calculation system and redundant calculation method |
| JP2011198205A (en) * | 2010-03-23 | 2011-10-06 | Railway Technical Research Institute | Redundant system control system |
| CN101996110B (en) * | 2010-11-17 | 2012-12-19 | 中国航空工业集团公司第六三一研究所 | Three-redundancy fault-tolerant computer platform based on modular structure |
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2015
- 2015-04-14 GB GB1506268.0A patent/GB2526917B/en active Active
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| DE102015208989A1 (en) | 2015-11-26 |
| JP6600128B2 (en) | 2019-10-30 |
| CN105093979A (en) | 2015-11-25 |
| GB2526917A (en) | 2015-12-09 |
| JP2015222520A (en) | 2015-12-10 |
| GB2526917B (en) | 2016-09-07 |
| GB201506268D0 (en) | 2015-05-27 |
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