GB2526917A - Fail-safe processing apparatus - Google Patents
Fail-safe processing apparatus Download PDFInfo
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- GB2526917A GB2526917A GB1506268.0A GB201506268A GB2526917A GB 2526917 A GB2526917 A GB 2526917A GB 201506268 A GB201506268 A GB 201506268A GB 2526917 A GB2526917 A GB 2526917A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0428—Safety, monitoring
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1629—Error detection by comparing the output of redundant processing systems
- G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0796—Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1608—Error detection by comparing the output signals of redundant hardware
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
- G06F11/182—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits based on mutual exchange of the output between redundant processing components
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1629—Error detection by comparing the output of redundant processing systems
- G06F11/1633—Error detection by comparing the output of redundant processing systems using mutual exchange of the output between the redundant processing components
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/2015—Redundant power supplies
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- General Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Safety Devices In Control Systems (AREA)
- Hardware Redundancy (AREA)
- Retry When Errors Occur (AREA)
- Power Sources (AREA)
Abstract
A fail-safe processing apparatus has a plurality of calculation units 12 & 13 having a function to simultaneously perform the same calculation and mutually monitor the output data. An output control unit 16 has a function to temporarily store the output data for each of the calculation units and output the stored data for each of the calculation units according to an instruction from one of the plurality of calculation units. A plurality of power supplies 14 & 15 are provided for each of the calculation units, wherein one of the plurality of power supplies supplies power not only to the associated calculation unit but also to the output control unit. At least one of the power supplies may have a different power capacity from the others. Each of the calculation units may have a function to send a reset signal to the other calculation units. If the mutually monitored data in unmatched each of the plurality of calculation units may send the reset signal and when the reset signal is received each of the plurality of calculation units may stop their own calculations. The output data is temporarily stored in a buffer in the output control unit.
Description
FAIL-SAFE PROCESSING APPARATUS
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a multiple-system fail-safe processing apparatus that is used in a field requiring high safety, includes therein a plurality of calculation units, and provides a fail-safe configuration to ensure a match between the calculation results.
Description of the Related Art
A system performing calculation in a field requiring high safety, such as railway signaling safety systems and power plants, includes multiple calculation units and performs a series of controls so that the system checks whether or not the calculation results are matched; if matched, the system continues normal operation; and if unmatched, the system transitions to a safe state.
Thus, it is necessary to eliminate the factors for which a plurality of calculation units simultaneously produce the same erroneous output. One of the factors includes a temporary voltage variation of a power supply. Japanese Patent Laid- Open No. 2002-116921 (Patent Document 1) and Japanese Patent Laid-Open No. 6- 298105 (Patent Document 2) include a plurality of calculation units to each of which power is separately supplied from a different power supply. There is a low probability that a plurality of power supplies simultaneously generate a failure of the same type, which allows a reduction in probability that a plurality of calculation units simultaneously produce the same erroneous output due to a power supply failure.
However, if different power supplies separately supplying power simultaneously generate the same voltage variation, the plurality of calculation units simultaneously output the same erroneous data, thus leading to a possibility that the output control unit cannot detect the erroneous data and outputs the erroneous data to outside. In order to detect a temporary voltage variation of a plurality of power supplies, Patent Document 1 provides a configuration in which one CPU is also connected to the other power supply and monitors the other power supply, and Patent Document 2 provides a configuration in which both CPUs mutually monitor each other's power supply output. However, if a temporary voltage variation occurs in a power supply, the CPU may output erroneous data without receiving a calculation stop command such as reset from a power monitoring unit. Accordingly, it is an object of the present invention to provide a fail-safe processing apparatus that eliminates the possibility of outputting an erroneous calculation result even if a temporary voltage variation occurs in a power supply supplying power to a plurality of calculation units.
SUMMARY OF THE INVENTION
In order to solve the above problem, one of a plurality of power supplies separately supplying power to a plurality of calculation units constituting a fail-safe processing apparatus supplies power not only to the associated calculation unit but also to the other circuit portions other than the calculation units constituting the fail-safe processing apparatus, or has a different power supply capacity.
According to the present invention, even if a temporary voltage variation occurs in a power supply, each calculation unit has a difference in timing affected by the voltage variation, and hence the present invention can prevent each of the calculation units from simultaneously outputting the same erroneous calculation res u It.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a configuration view illustrating a fail-safe processing apparatus according to a first embodiment; FIG. 2 is an equivalent circuit diagram simplified by replacing the circuits other than the calculation units according to the first embodiment with resistor and capacitor components; FIG. 3 is a diagram illustrating voltage variation, clock, and evolution in time of output data in each calculation unit at input voltage variation according to the first embodiment; FIG. 4 is a configuration view illustrating a fail-safe processing apparatus according to a second embodiment; and FIG. 5 is a configuration view illustrating a fail-safe processing apparatus according to a third embodiment.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Hereinafter, first to third embodiments will be described in sequence as the embodiments of the present invention.
[First Embodiment] The first embodiment of the present invention will be described with reference to FIGS. ito 3.
The first embodiment as a multiple-system fail-safe processing apparatus basically has a dual-system configuration including two calculation units simultaneously performing the same calculation and two power supplies having the same capacity. FIG. 1 is a configuration view illustrating a fail-safe processing apparatus 11 according to the first embodiment.
The fail-safe processing apparatus 11 is applied to a calculation unit requiring fail-safe properties of output data. In order to ensure fail-safe properties, the configuration illustrated in FIG. 1 includes two calculation units: a calculation unit A(i 2) and a calculation unit BO 3). Data outputted from the fail-safe processing apparatus 11 is based on the data calculated by the calculation unit A(12) and the calculation unit B(13).
The data outputted from the calculation unit A(1 2) and the calculation unit B(i 3) is once held (temporarily stored) in a buffer 17 in an output control unit (16).
The calculation unit A(12) and the calculation unit B(13) mutually monitor each other's output data to confirm that the mutual output data is equal to each other. If the output data is equal to each other, the data stored in the buffer 17 in the output control unit 16 is outputted by an instruction of the calculation unit A(12). If the mutual output data is not equal to each other due to a problem of at least one of both the output data, data is not outputted from the buffer 17. Note that the calculation unit A(1 2) and the calculation unit B(1 3) have a function to send a reset signal to the other party (paired system) to stop calculation, and reset the other side if a problem occurs such that the mutual output data is not equal to each other.
There is a very low probability that both the calculation unit A(1 2) and calculation unit B(1 3) fail at the same time] and hence such a method allows a configuration of a fail-safe processing apparatus enabling fail-safe output.
However, if there are factors for the same failure occurring simultaneously in both the calculation unit A(12) and the calculation unit B(13), there is also a risk of outputting an erroneous signal from both the calculation units. Thus, although the output data is mutually monitored, the calculation unit A(12) and the calculation unit B(1 3) cannot detect the error and may output the erroneous signal to outside.
Therefore, as described above, the fail-safe processing apparatus needs to eliminate the factors for the simultaneous occurrence of the same failure as much as possible to sufficiently suppress the probability of outputting the erroneous signal to outside.
Examples of the factors for the simultaneous occurrence of the same failure include a power supply supplying power to the calculation unit A(1 2) and the calculation unit B(13). When the calculation unit A(12) and the calculation unit B(13) are powered from a common power supply, a temporary failure occurring in the common power supply may cause the calculation unit A(12) and the calculation unit B(1 3) to simultaneously output the same erroneous data.
In light of this, the calculation unit A(12) is powered from the power supply A(14), and the calculation unit B(13) is powered from the power supply B(15).
There is a very low probability that both the power supply A(14) and the power supply B(1 5) simultaneously generate a failure of the same type. Thus, the separation of power supplies powering the calculation unit A(12) and the calculation unit B(13) allows a reduction in probability that both the calculation units simultaneously generate a failure of the same type.
However, if a voltage variation occurs simultaneously both in the power supply A(1 4) and the power supply B(1 5) with the same magnitude of load for each power supply (including the calculation unit A(1 2) and the calculation unit B(1 3)), a temporary abnormal voltage of the same level is simultaneously outputted. This may result in that the same abnormal condition may occur simultaneously in the calculation unit A(12) and the calculation unit B(13). Even if each other's output data is mutually monitored at this time, the calculation unit A(12) and the calculation unit B(1 3) cannot detect the output data error and may output erroneous data to outside.
In light of this, as illustrated in FIG. 1, the first embodiment devises the load connected to each power supply to prevent the calculation unit A(12) and the calculation unit B(13) from simultaneously outputting the same erroneous data even if the power supply failure occurs. More specifically, the magnitude of load is intentionally differentiated by allowing one of the power supply A(14) and the power supply B(15) to supply power also to circuits (for example] the output control unit 16 and the other circuit 18) other than the calculation unit A(12) and the calculation unit B(13).
For convenience of description, FIG. 2 illustrates an equivalent circuit diagram simplified by replacing the circuits (the output control unit 16 and the other circuit 18) other than the calculation unit A(1 2) and the calculation unit B(1 3) in FIG. 1 with resistor and capacitor components.
FIG. 2(A) is an equivalent circuit of an A system circuit, in which an A system power supply 20 corresponds to the power supply A(1 4) in FIG. 1. A resistor component RA 22 of the load other than the calculation unit A(1 2) includes resistor components of the substrate and circuits of the fail-safe processing apparatus 11. A capacitor component CA23 of the entire A system circuit includes a capacitor component contained in the A system power supply 20 itself as well as the capacitor components of the substrate and circuits of the fail-safe processing apparatus 11 to which voltage is supplied from the A system power supply 20 other than the calculation unit A(12). An input voltage applied to the calculation unit A(12) corresponds to an input voltage EcPu_A24 of the A system calculation unit.
FIG. 2(B) is an equivalent circuit of a B system circuit, in which a B system power supply 25 corresponds to the power supply B(1 5) in FIG. 1. A resistor component RB 28 of the load other than the calculation unit B(13) includes resistor components of the substrate and circuits of the fail-safe processing apparatus 11. A capacitor component CB 28 of the entire B system circuit includes a capacitor component contained in the B system power supply 26 itself as well as the capacitor components of the substrate and circuits of the fail-safe processing apparatus 11 to which voltage is supplied from the B system power supply 25 other than the calculation unit B(13). An input voltage applied to the calculation unit B(13) corresponds to an input voltage EcPU_B 29 of the B system calculation unit.
As illustrated in FIG. 1, the number of circuits connected to the power supply A(1 4) of the A system is less than the number of circuits connected to the power supply B(15) and the ICs for use in the output control unit 16 and the other circuit 18 are the load connected in parallel with the circuit. Thus, RA is greater than RB. FIG. 3 illustrates a relationship among the variations of the input voltage ECPU_A 24 of the A system calculation unit and the input voltage EcPU_B 29 of the B system calculation unit at the time of variation in the A system power supply voltage Em_A 21 and the B system power supply voltage Em_B 26, clock, and output data.
The A system power supply voltage Em_A 21 and the B system power supply voltage Em_B 26 in FIG. 2 vary as illustrated by a power input variation 30 of a power supply in FIG. 3. Thus, the input voltage EcPU_A 24 of the A system calculation unit in FIG. 2 generates an input voltage variation 31 in the A system calculation unit in FIG. 3. Likewise, the input voltage ECPU_B 29 of the B system calculation unit in FIG. 2 generates an input voltage variation 36 in the B system calculation unit in FIG. 3.
Here, the variation of the input voltage ECPU_A 24 of the A system calculation unit and the input voltage Ecr'u_e 29 of the B system calculation unit at the point of time when the power input variation 30 of the power supply occurs and the voltage falls from Vi to V2, is expressed by the following equation.
ECPU_A = V2 x {1 -exp(-tIRACA)} + Vi x exp(-t/RACA) Ecpue = V2 x {1 -exp(-tIRBCB)} + Vi x exp(-t/RBCB) In general, the calculation units are designed so as not to malfunction even if about 10% of voltage variation occurs. Thus, it is assumed in FIG. 3 that an operating lower limit threshold voltage 32 of the A system calculation unit and an operating lower limit threshold voltage 37 of the B system calculation unit are 10% of the rated voltage. It is also assumed that V2 is defined as a minimum value when each input voltage of the A system calculation unit and the B system calculation unit falls by the voltage variation, and the minimum value J2 is below the operating lower limit threshold voltage 32 of the A system calculation unit and the operating lower limit threshold voltage 37 of the B system calculation unit.
Assuming that a time MA is defined as the time from when the power input variation 30 falls until the voltage variation 31 in the A system calculation unit falls below the operating lower limit threshold voltage 32 of the A system calculation unit, and a time MB is defined as the time from when the power input variation 30 falls until the voltage variation 36 in the B system calculation unit falls below the operating lower limit threshold voltage 37 of the B system calculation unit, the time can be expressed by the following relational expression.
0.9 Vi = V2 x {1-exp(-AWRACA)} + Vi x exp(-AtPiRACA) 0.9 Vi = V2 x {1-exp(-AtB/RBCB)} + Vi x exp(-AtB/RBCB) From the above relational expression, the time AtA and the time Ats can be obtained as follows.
AtA = -RACAIn{(O.9V1-V2)/(V1-V2)} AtB = -RBCBIn{(O.9V1-V2)/(V1-V2)} Assuming also that f[Hz] is defined as the frequency of operating clocks 33 and 38 of respective calculation units of the A system and the B system, the length of one bit of data is 1/f[s]. In order to generate one or more bits of difference between a start bit of erroneous output data 35 of the output data 34 in the A system calculation unit and a start bit of erroneous output data 40 of the output data 39 in the B system calculation unit, the following the conditional expression needs to be satisfied.
AtB -AtA = -RBCBIn{(0.9Vi-V2)/(V1-V2)} + RACAIn{(O.9V1-V2)/(Vi-V2)}> 1/f From the above conditional expression, the respective resistor components and capacitor components of the A system and the B system circuit (load other than the respective calculation units of the A system and the B system) may be designed so as to satisfy the following relational expression.
RACA -RBCB> 1I[f x ln{(O.9V1-V2)/(V1-V2)}] In order to reliably achieve the above relational expression, a comparable load to the calculation unit A(12) and the calculation unit B(13) may be connected to any one of the power supplies (the power supply A(1 4) or the power supply B(1 5) in FIG. 1).
In the fail-safe processing apparatus 11 illustrated in FIG. 1, the calculation unit A(1 2) and the calculation unit B(1 3) perform the same calculation. Then, the output control unit 17 checks whether or not at least one of the output data 34 from the calculation unit A(12) and the output data 39 from the calculation unit B(13) contains an error. Then, as illustrated in FIG. 4, if there is even one bit of difference between the output data 34 of the A system calculation unit and the output data 39 of the B system calculation unit when a variation of the input voltage from the power supply occurs, an error of the output data can be detected since the calculation unit A(12) and the calculation unit B(13) mutually monitor each others output.
This makes it possible to provide a fail-safe processing apparatus in which the output control unit 16 can prevent erroneous output of data from the calculation unit A(12) and the calculation unit B(13).
[Second Embodiment] A second embodiment of the present invention differentiates the power supply capacity among the power supply units supplying power to each calculation unit constituting the fail-safe processing apparatus. FIG. 4 is a view illustrating a configuration as the second embodiment in which in a dual-system fail-safe processing apparatus (FIG. 1), the power supply units have a different power supply capacity from each other.
For example, the power supply B(45) has a larger power supply capacity than that of the power supply A(1 4). Thus, even if a voltage variation occurs simultaneously in the power supply A(1 4) and the power supply B(45), the difference in the power supply capacity can prevent the calculation unit A(12) and the calculation unit B(13) from simultaneously outputting the same erroneous data.
[Third Embodiment] A third embodiment of the present invention applies a triple-system as a multiple-system fail-safe processing apparatus. FIG. 5 is a configuration view illustrating a triple-system fail-safe processing apparatus that adds a power supply 0(54) and a calculation unit 0(52). The calculation unit 0(52) performs the same calculation as the calculation unit A(12) and the calculation unit B(13) at the same time. In addition, the calculation unit A(12), the calculation unit B(13), and the calculation unit C(52) have a function to mutually monitor each other's output and reset the paired system.
In the configuration illustrated in FIG. 5, the power supply C(54) supplies power not only to the calculation unit 0(52) but also the output control unit 16 and the other circuit 18. This configuration differentiates the load between the load when the power supply A(14) and the power supply B(15) supply power to the calculation unit A(1 2) and the calculation unit B(1 3) respectively and the load when the power supply C(54) supplies power. It is apparent that instead of the power supply C(54), the power supply A(14) or the power supply B(15) may be configured to supply power to the output control unit 16 and the other circuit 18.
Therefore, even if a voltage variation occurs simultaneously in all the three power supplies, this configuration can prevent the calculation unit A(1 2), the calculation unit B(13), and the calculation unit C(52) from simultaneously outputting the same erroneous data.
Claims (6)
- What is claimed is: 1. A fail-safe processing apparatus comprising: a plurality of calculation units having a function to simultaneously perform the same calculation and mutually monitor output data; an output control unit having a function to temporarily store the output data for each of the calculation units and output the stored output data for each of the calculation units according to an instruction from one of the plurality of calculation units to outside; and a plurality of power supplies provided for each of the calculation units, wherein one of the plurality of power supplies supplies power not only to the associated calculation unit but also to the output control unit.
- 2. The fail-safe processing apparatus according to claim 1, wherein at least one of the plurality of power supplies has a different power supply capacity from that of the other power supplies.
- 3. The fail-safe processing apparatus according to claim 1 or 2, wherein if the mutually monitored output data is matched, one of the plurality of calculation units issues the instruction to the output control unit.
- 4. The fail-safe processing apparatus according to any one of claims 1 to 3, wherein each of the plurality of calculation units has a function to send a reset signal to the other of the plurality of calculation units.
- 5. The fail-safe processing apparatus according to claim 4, wherein if the mutually monitored output data is unmatched, each of the plurality of calculation units sends the reset signal.
- 6. The fail-safe processing apparatus according to claim 4 or 5, wherein when the reset signal is received, each of the plurality of calculation units stops its own calculation.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014106919A JP6600128B2 (en) | 2014-05-23 | 2014-05-23 | Arithmetic processing unit |
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| GB201506268D0 GB201506268D0 (en) | 2015-05-27 |
| GB2526917A true GB2526917A (en) | 2015-12-09 |
| GB2526917B GB2526917B (en) | 2016-09-07 |
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| GB1506268.0A Active GB2526917B (en) | 2014-05-23 | 2015-04-14 | Fail-safe processing apparatus |
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| JP (1) | JP6600128B2 (en) |
| CN (1) | CN105093979B (en) |
| DE (1) | DE102015208989A1 (en) |
| GB (1) | GB2526917B (en) |
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| CN110890884A (en) * | 2018-09-10 | 2020-03-17 | 台湾积体电路制造股份有限公司 | Fail-safe circuit, integrated circuit device, and method of controlling node of circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06298105A (en) * | 1993-04-15 | 1994-10-25 | Nippondenso Co Ltd | Rear wheel steering device control system |
| US20120233506A1 (en) * | 2009-12-02 | 2012-09-13 | Yoshio Kameda | Redundant computing system and redundant computing method |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04149743A (en) * | 1990-10-15 | 1992-05-22 | Mitsubishi Electric Corp | Driving system for data processor |
| JP2001183490A (en) * | 1999-12-22 | 2001-07-06 | Hitachi Ltd | Reactor core flow control system |
| JP2002116921A (en) | 2000-10-06 | 2002-04-19 | Matsushita Electric Ind Co Ltd | Auxiliary device for central processing unit |
| US8143851B2 (en) * | 2008-02-15 | 2012-03-27 | Apple Inc. | Power source having a parallel cell topology |
| JP2011198205A (en) * | 2010-03-23 | 2011-10-06 | Railway Technical Research Institute | Redundant system control system |
| CN101996110B (en) * | 2010-11-17 | 2012-12-19 | 中国航空工业集团公司第六三一研究所 | Three-redundancy fault-tolerant computer platform based on modular structure |
-
2014
- 2014-05-23 JP JP2014106919A patent/JP6600128B2/en active Active
-
2015
- 2015-04-14 GB GB1506268.0A patent/GB2526917B/en active Active
- 2015-05-15 DE DE102015208989.4A patent/DE102015208989A1/en active Granted
- 2015-05-21 CN CN201510260992.6A patent/CN105093979B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06298105A (en) * | 1993-04-15 | 1994-10-25 | Nippondenso Co Ltd | Rear wheel steering device control system |
| US20120233506A1 (en) * | 2009-12-02 | 2012-09-13 | Yoshio Kameda | Redundant computing system and redundant computing method |
Also Published As
| Publication number | Publication date |
|---|---|
| DE102015208989A1 (en) | 2015-11-26 |
| JP6600128B2 (en) | 2019-10-30 |
| CN105093979B (en) | 2017-11-28 |
| CN105093979A (en) | 2015-11-25 |
| JP2015222520A (en) | 2015-12-10 |
| GB2526917B (en) | 2016-09-07 |
| GB201506268D0 (en) | 2015-05-27 |
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