CN105070686B - The preparation method and TFT substrate structure of TFT substrate - Google Patents
The preparation method and TFT substrate structure of TFT substrate Download PDFInfo
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- CN105070686B CN105070686B CN201510514415.5A CN201510514415A CN105070686B CN 105070686 B CN105070686 B CN 105070686B CN 201510514415 A CN201510514415 A CN 201510514415A CN 105070686 B CN105070686 B CN 105070686B
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- 239000000758 substrate Substances 0.000 title claims abstract description 68
- 238000002360 preparation method Methods 0.000 title claims abstract description 29
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 82
- 229910052796 boron Inorganic materials 0.000 claims abstract description 47
- 239000012528 membrane Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000010410 layer Substances 0.000 claims description 127
- -1 boron ion Chemical class 0.000 claims description 39
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 31
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 26
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 26
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 25
- 239000011229 interlayer Substances 0.000 claims description 20
- 239000002131 composite material Substances 0.000 claims description 14
- 239000012212 insulator Substances 0.000 claims description 14
- 239000007789 gas Substances 0.000 claims description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- 150000002500 ions Chemical class 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- 238000005224 laser annealing Methods 0.000 claims description 3
- 229910000077 silane Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 238000009740 moulding (composite fabrication) Methods 0.000 abstract description 15
- 238000002347 injection Methods 0.000 abstract description 11
- 239000007924 injection Substances 0.000 abstract description 11
- 238000004519 manufacturing process Methods 0.000 abstract description 11
- 229910021419 crystalline silicon Inorganic materials 0.000 abstract description 10
- 239000010408 film Substances 0.000 description 29
- 239000004973 liquid crystal related substance Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000006197 hydroboration reaction Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/2205—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention provides a kind of preparation method and TFT substrate structure of TFT substrate.The preparation method of the TFT substrate of the present invention, during amorphous silicon layer is made, by the way of more one-step film formings, and it is surface-treated after every one-step film forming using hydroboron gas by CVD and boron ion injection is carried out to amorphous silicon membrane, finally give the amorphous silicon layer of boron ion doping, formed after channel region without being individually doped to channel region, be effectively simplified processing procedure, reduce production cost.The TFT substrate structure of the present invention, channel region complete boron ion injection in non-crystalline silicon film forming, and without individually carrying out channel doping processing procedure, making is simple, and production cost is low.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of preparation method of TFT substrate and TFT substrate structure.
Background technology
In display technology field, liquid crystal display (Liquid Crystal Display, LCD) and Organic Light Emitting Diode
The flat-panel monitors such as display (Organic Light Emitting Diode, OLED) progressively substitute CRT monitor.
Usual liquid crystal display device includes housing, the liquid crystal panel in housing and the backlight module in housing
(Backlight module).Wherein, the structure of liquid crystal panel is mainly by a thin-film transistor array base-plate (Thin Film
Transistor Array Substrate, TFT Array Substrate), a colored filter substrate (Color
Filter, CF) and the liquid crystal layer (Liquid Crystal Layer) that is configured between two substrates formed, its operation principle
It is to control the rotation of the liquid crystal molecule of liquid crystal layer by applying driving voltage on two panels glass substrate, by the light of backlight module
Line reflects generation picture.
Thin-film transistor array base-plate is that TFT substrate is important component in liquid crystal display.In TFT substrate,
In order to adjusting device threshold voltage, it is necessary to carry out channel doping.Generally after grid oxidation film formation, lead in channel region
Cross ion embedding technology to enter a small amount of alms giver or acceptor impurity ion implanting, so as to complete channel doping.And it is ion implanted
In processing procedure, with ion implantation apparatus realize be ion implanted it is most commonly seen, such as channel region, N-type heavily doped region, N-type lightly doped district and P
Type doped region etc. generally uses ion implantation apparatus implanting ions, and when carrying out every one of ion implantation manufacture process, is required to
Completed using one of light shield, and required precision of the ion implantation manufacture process to light shield is harsh, while board debugging difficulty be present, take
The problems such as long.
The content of the invention
It is an object of the invention to provide a kind of preparation method of TFT substrate, can save channel doping processing procedure, simplifies system
Journey, reduce production cost.
The present invention also aims to provide a kind of TFT substrate structure, channel region completed in non-crystalline silicon film forming boron from
Son injection, without individually carrying out channel doping processing procedure.
To achieve the above object, the present invention provides a kind of preparation method of TFT substrate, comprises the following steps：
Step 1, substrate is provided, on the substrate buffer layer；
Step 2, an amorphous silicon membrane is deposited on the cushion, and hydroboration is passed through on the amorphous silicon membrane surface
Compound gas, the amorphous silicon membrane is surface-treated using the method for chemical vapor deposition so that the non-crystalline silicon is thin
The surface doping boron ion of film；
Step 3, repeat step 2 operation for several times, obtain the amorphous silicon membrane of several layer surfaces doping boron ions, described several layers
The amorphous silicon membrane superposition of surface doping boron ion forms amorphous silicon layer；
Step 4, the amorphous silicon layer is made annealing treatment, remove the hydrogen ion adulterated in amorphous silicon layer, caused simultaneously
The boron ion for being doped to every layer of amorphous silicon membrane surface is uniformly diffused into whole amorphous silicon layer, is realized to whole amorphous silicon layer
Boron ion is adulterated；
Step 5, the boron ion is adulterated using twice light shield after amorphous silicon layer carry out ion implanting twice, obtain in place
In two N-type heavily doped regions of the amorphous silicon layer both sides, the boron ion doped channel regions in the middle part of the amorphous silicon layer and
Two N-type lightly doped districts between described two N-type heavily doped regions and boron ion doped channel regions；
Step 6, gate insulator, grid, interlayer insulating film and source, drain electrode are sequentially formed on the amorphous silicon layer.
The substrate is glass substrate or plastic base.
The cushion is the composite bed of silicon oxide layer, silicon nitride layer or silicon oxide layer and silicon nitride layer.
Amorphous silicon membrane described in chemical vapor deposition is passed through using silane and hydrogen.
The hydroboron gas is diborane.
The number that repeat step 2 operates in the step 3 is more than or equal to once.
The step 5 is using boiler tube, quasi-molecule laser annealing equipment or chemical vapor deposition heating chamber to the non-crystalline silicon
Layer is made annealing treatment.
The interlayer insulating film is the composite bed of silicon oxide layer, silicon nitride layer or silicon oxide layer and silicon nitride layer.
The present invention also provides a kind of TFT substrate structure, including substrate, the cushion on the substrate, located at described
Amorphous silicon layer on cushion, the gate insulator on the amorphous silicon layer, the grid on the gate insulator,
Interlayer insulating film and the source electrode on the interlayer insulating film and the leakage of the grid are covered on the gate insulator
Pole；
The amorphous silicon layer includes corresponding to the source electrode positioned at the both sides of amorphous silicon layer and two N-types of drain electrode lower section are heavily doped
Miscellaneous area, correspond to positioned at the middle part of amorphous silicon layer boron ion doped channel regions below the grid and positioned at described two N-type weights
Two N-type lightly doped districts between doped region and boron ion doped channel regions；
The gate insulator corresponds to on interlayer insulating film to be respectively equipped with above described two N-type heavily doped regions
Hole, the source electrode are in contact with draining via the via with the N-type heavily doped region.
The cushion is the composite bed of silicon oxide layer, silicon nitride layer or silicon oxide layer and silicon nitride layer；The interlayer is exhausted
Edge layer is the composite bed of silicon oxide layer, silicon nitride layer or silicon oxide layer and silicon nitride layer.
Beneficial effects of the present invention：The preparation method of TFT substrate provided by the invention, making the process of amorphous silicon layer
In, by the way of more one-step film formings, and boron ion is carried out to amorphous silicon membrane using hydroboron gas after every one-step film forming
Injection, the amorphous silicon layer of boron ion doping is finally given, formed after raceway groove without being individually doped to raceway groove, be effectively simplified
Processing procedure, reduce production cost.The TFT substrate structure of the present invention, channel region complete boron ion injection in non-crystalline silicon film forming,
Without individually carrying out channel doping processing procedure, make simply, production cost is low.
Brief description of the drawings
In order to be further understood that the feature of the present invention and technology contents, refer to below in connection with the detailed of the present invention
Illustrate and accompanying drawing, however accompanying drawing only provide with reference to and explanation use, be not used for being any limitation as the present invention.
In accompanying drawing,
Fig. 1 is the flow chart of the preparation method of the TFT substrate of the present invention；
Fig. 2 is the schematic diagram of the step 1 of the preparation method of the TFT substrate of the present invention；
Fig. 3-Fig. 4 is the schematic diagram of the step 2 of the preparation method of the TFT substrate of the present invention；
Fig. 5-Fig. 6 is the schematic diagram of the step 3 of the preparation method of the TFT substrate of the present invention；
Fig. 7 is the schematic diagram of the step 4 of the preparation method of the TFT substrate of the present invention；
Fig. 8 is the schematic diagram of the step 5 of the preparation method of the TFT substrate of the present invention；
Fig. 9 is the schematic diagram of step 6 and the cuing open for TFT substrate structure of the present invention of the preparation method of the TFT substrate of the present invention
Face schematic diagram.
Embodiment
Further to illustrate the technological means and its effect of the invention taken, below in conjunction with being preferable to carry out for the present invention
Example and its accompanying drawing are described in detail.
Referring to Fig. 1, present invention firstly provides a kind of preparation method of TFT substrate, comprise the following steps：
Step 1, as shown in Figure 2, there is provided substrate 1, the buffer layer 2 on the substrate 1.
Specifically, the substrate 1 can be glass substrate or plastic base.
Specifically, the cushion 2 can be silica (SiOx) layer, silicon nitride (SiNx) layer or silicon oxide layer and nitrogen
The composite bed of SiClx layer.In this embodiment, the cushion 2 is the composite bed of silicon oxide layer and silicon nitride layer.
Step 2, as shown in figure 3, deposit a non-crystalline silicon (a-Si) film 301 on the cushion 2, as shown in figure 4,
The surface of amorphous silicon membrane 301 is passed through hydroboron gas, thin to the non-crystalline silicon using the method for chemical vapor deposition
Film 301 is surface-treated so that the surface doping boron ion of the amorphous silicon membrane 301.
Specifically, the amorphous silicon membrane 301 is deposited by chemical vapor deposition (CVD) method using silane and hydrogen.
Specifically, the hydroboron gas is diborane (B2H6) or other hydroborons.
Specifically, the process of the amorphous silicon membrane 301 is deposited with using non-crystalline silicon described in hydroboron gas treatment
The process of film 301 can be carried out continuously in same chamber, can also be divided among in two chambers and be carried out.
Step 3, repeat step 2 operation for several times, obtain the amorphous silicon membrane 301 of several layer surfaces doping boron ions, it is described
The superposition of amorphous silicon membrane 301 of number layer surface doping boron ion forms amorphous silicon layer 3.
Specifically, the number that repeat step 2 operates in the step 3 is more than or equal to once.
As shown in Fig. 5-Fig. 6, in embodiments of the invention, the step 3 for repeating said steps 2 operation once, i.e.
Finally deposited two layers of amorphous silicon membrane 301 on the buffer layer 2, the amorphous silicon layer 3 finally given by two layers of surface adulterate boron from
The amorphous silicon membrane 301 of son is formed by stacking.
Step 4, as shown in fig. 7, made annealing treatment to the amorphous silicon layer 3, remove the hydrogen that is adulterated in amorphous silicon layer 3 from
Son, while the boron ion for be doped to every layer of surface of amorphous silicon membrane 301 is uniformly diffused into whole amorphous silicon layer 3, is realized
The boron ion of whole amorphous silicon layer 3 is adulterated.
Specifically, boiler tube, quasi-molecule laser annealing (ELA) equipment or chemical vapor deposition heating chamber (CVD can be used
Heating Chamber) amorphous silicon layer 3 is made annealing treatment.
Step 5, as shown in figure 8, using twice light shield to the boron ion adulterate after amorphous silicon layer 3 carry out two secondary ions
Injection, obtain two N-type heavily doped regions 31 positioned at the both sides of amorphous silicon layer 3, positioned at the middle part of the amorphous silicon layer 3 boron from
Sub- doped channel regions 33 and two N-type lightly doped districts 32 between described two N-type heavily doped regions 31 and channel region 33.
Because amorphous silicon layer 3 completes the injection of boron ion in film forming, therefore without carrying out ion to channel region 33 again
Dopping process.
Step 6, as shown in figure 9, sequentially forming gate insulator 5, grid 6, interlayer insulating film on the amorphous silicon layer 3
7 and source, drain electrode 81,82.The step 6 can use prior art to realize.
Specifically, the interlayer insulating film 7 can be silicon oxide layer, silicon nitride layer or silicon oxide layer and silicon nitride layer
Composite bed.In this embodiment, the interlayer insulating film 7 is the composite bed of silicon oxide layer and silicon nitride layer.
The preparation method of above-mentioned TFT substrate, during amorphous silicon layer is made, by the way of more one-step film formings, and
Boron ion injection is carried out to amorphous silicon membrane using hydroboron gas after per one-step film forming, finally gives the non-of boron ion doping
Crystal silicon layer, formed after raceway groove without being individually doped to raceway groove, be effectively simplified processing procedure, reduce production cost.
Referring to Fig. 9, the present invention also provides a kind of TFT substrate structure, including substrate 1, the buffering on the substrate 1
Layer 2, the amorphous silicon layer 3 on the cushion 2, the gate insulator 5 on the amorphous silicon layer 3, located at the grid
Grid 6 on pole insulating barrier 5, cover on the gate insulator 5 interlayer insulating film 7 of the grid 6 and located at described
Source electrode 81 and drain electrode 82 on interlayer insulating film 7.
Specifically, the amorphous silicon layer 3 includes corresponding to the source electrode 81 and the lower section of drain electrode 82 positioned at the both sides of amorphous silicon layer 3
Two N-type heavily doped regions 31, correspond to positioned at the middle part of amorphous silicon layer 3 lower section of the grid 6 boron ion doped channel regions 33,
And two N-type lightly doped districts 32 between the N-type heavily doped region 31 and boron ion doped channel regions 33.
The top that the gate insulator 5 corresponds to described two N-type heavily doped regions 31 with interlayer insulating film 7 is respectively equipped with
Via 80, the source electrode 81 are in contact via the via 80 with the N-type heavily doped region 31 respectively with drain electrode 82.
Specifically, the boron ion doped channel regions 33 are using the boron ion doping in the preparation method of above-mentioned TFT substrate
The preparation method of channel region 33 is prepared.
Specifically, the cushion 2 can be the compound of silicon oxide layer, silicon nitride layer or silicon oxide layer and silicon nitride layer
Layer；The interlayer insulating film 7 can be the composite bed of silicon oxide layer, silicon nitride layer or silicon oxide layer and silicon nitride layer.In the reality
Apply in example, the cushion 2, interlayer insulating film 7 are the composite bed of silicon oxide layer and silicon nitride layer.
Above-mentioned TFT substrate structure, channel region completes boron ion injection in non-crystalline silicon film forming, without individually carrying out raceway groove
Dopping process, make simply, production cost is low.
In summary, the preparation method of TFT substrate provided by the invention, during amorphous silicon layer is made, using more
The mode of one-step film forming, and boron ion injection is carried out to amorphous silicon membrane using hydroboron gas after every one-step film forming, finally
The amorphous silicon layer of boron ion doping is obtained, is formed after raceway groove without being individually doped to raceway groove, is effectively simplified processing procedure, reduces
Production cost.The TFT substrate structure of the present invention, channel region completes boron ion injection in non-crystalline silicon film forming, without independent
Channel doping processing procedure is carried out, is made simply, production cost is low.
It is described above, for the person of ordinary skill of the art, can be with technique according to the invention scheme and technology
Other various corresponding changes and deformation are made in design, and all these changes and deformation should all belong to the appended right of the present invention
It is required that protection domain.
Claims (10)
1. a kind of preparation method of TFT substrate, it is characterised in that comprise the following steps：
Step 1, provide substrate (1), the buffer layer (2) on the substrate (1)；
Step 2, an amorphous silicon membrane (301) is deposited on the cushion (2), and on the amorphous silicon membrane (301) surface
Hydroboron gas is passed through, the amorphous silicon membrane (301) is surface-treated using the method for chemical vapor deposition, made
Obtain the surface doping boron ion of the amorphous silicon membrane (301)；
Step 3, repeat step 2 operation for several times, obtain the amorphous silicon membrane (301) of several layer surfaces doping boron ions, the number
Amorphous silicon membrane (301) superposition of layer surface doping boron ion forms amorphous silicon layer (3)；
Step 4, the amorphous silicon layer (3) is made annealing treatment, remove the hydrogen ion of doping in amorphous silicon layer (3), make simultaneously
The boron ion that every layer of amorphous silicon membrane (301) surface must be doped to uniformly is diffused into whole amorphous silicon layer (3), is realized to whole
The boron ion doping of amorphous silicon layer (3)；
Step 5, the boron ion is adulterated using twice light shield after amorphous silicon layer (3) carry out ion implanting twice, obtain in place
Two N-type heavily doped regions (31) in the amorphous silicon layer (3) both sides, the boron ion in the middle part of the amorphous silicon layer (3) are mixed
Miscellaneous channel region (33) and two N-types between described two N-type heavily doped regions (31) and boron ion doped channel regions (33)
Lightly doped district (32)；
Step 6, sequentially form on the amorphous silicon layer (3) gate insulator (5), grid (6), interlayer insulating film (7) and
Source, drain electrode (81,82).
2. the preparation method of TFT substrate as claimed in claim 1, it is characterised in that the substrate (1) is glass substrate or modeling
Expect substrate.
3. the preparation method of TFT substrate as claimed in claim 1, it is characterised in that the cushion (2) be silicon oxide layer,
The composite bed of silicon nitride layer or silicon oxide layer and silicon nitride layer.
4. the preparation method of TFT substrate as claimed in claim 1, it is characterised in that chemical gas is passed through using silane and hydrogen
Amorphous silicon membrane (301) described in phase deposition method.
5. the preparation method of TFT substrate as claimed in claim 1, it is characterised in that the hydroboron gas is second boron
Alkane.
6. the preparation method of TFT substrate as claimed in claim 1, it is characterised in that repeat step 2 operates in the step 3
Number be more than or equal to once.
7. the preparation method of TFT substrate as claimed in claim 1, it is characterised in that the step 5 is using boiler tube, quasi-molecule
Laser annealing apparatus or chemical vapor deposition heating chamber make annealing treatment to the amorphous silicon layer (3).
8. the preparation method of TFT substrate as claimed in claim 1, it is characterised in that the interlayer insulating film (7) is silica
Layer, silicon nitride layer or the composite bed of silicon oxide layer and silicon nitride layer.
A kind of 9. TFT substrate structure made by preparation method of TFT substrate according to claim 1, it is characterised in that
Cushion (2) including substrate (1), on the substrate (1), the amorphous silicon layer (3) on the cushion (2), set
In the gate insulator (5) on the amorphous silicon layer (3), the grid (6) on the gate insulator (5), located at described
The interlayer insulating film (7) of the grid (6) and the source electrode on the interlayer insulating film (7) are covered on gate insulator (5)
(81) with draining (82)；
The amorphous silicon layer (3) includes corresponding to below the source electrode (81) and drain electrode (82) positioned at the both sides of amorphous silicon layer (3)
Two N-type heavily doped regions (31), positioned at the middle part of amorphous silicon layer (3) correspond to the boron ion doped channel below the grid (6)
Area (33) and two N-types between described two N-type heavily doped regions (31) and boron ion doped channel regions (33) are lightly doped
Area (32)；
The top that the gate insulator (5) corresponds to described two N-type heavily doped regions (31) with interlayer insulating film (7) is set respectively
There is via (80), the source electrode (81) is with drain electrode (82) respectively via the via (80) and N-type heavily doped region (31) phase
Contact.
10. TFT substrate structure as claimed in claim 9, it is characterised in that the cushion (2) is silicon oxide layer, silicon nitride
Layer or the composite bed of silicon oxide layer and silicon nitride layer；The interlayer insulating film (7) is silicon oxide layer, silicon nitride layer or silica
The composite bed of layer and silicon nitride layer.
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| CN106601595B (en) * | 2016-12-30 | 2019-11-26 | 武汉华星光电技术有限公司 | A kind of preparation method of semiconductor, semiconductor, display panel and display device |
| CN108198754B (en) * | 2017-12-04 | 2021-01-29 | 武汉华星光电半导体显示技术有限公司 | Manufacturing method of polycrystalline silicon TFT substrate and polycrystalline silicon TFT substrate |
| CN109920796B (en) * | 2017-12-13 | 2021-06-15 | 湘潭宏大真空技术股份有限公司 | Film coating method of TFT substrate |
| TWI783583B (en) * | 2020-07-21 | 2022-11-11 | 美商應用材料股份有限公司 | Ion implantation for reduced hydrogen incorporation in amorphous silicon |
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| CN1649152A (en) * | 2004-01-29 | 2005-08-03 | 卡西欧计算机株式会社 | Transistor array and its producing method, and image processing device |
| CN1855393A (en) * | 2005-04-28 | 2006-11-01 | 三星Sdi株式会社 | Thin film transistor and method of fabricating the same |
| CN103996716A (en) * | 2014-04-25 | 2014-08-20 | 京东方科技集团股份有限公司 | Poly-silicon thin film transistor and preparation method thereof, and array substrate |
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