CN105336683A - LTPS array substrate and manufacturing method thereof and display device - Google Patents
LTPS array substrate and manufacturing method thereof and display device Download PDFInfo
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- CN105336683A CN105336683A CN201510639246.8A CN201510639246A CN105336683A CN 105336683 A CN105336683 A CN 105336683A CN 201510639246 A CN201510639246 A CN 201510639246A CN 105336683 A CN105336683 A CN 105336683A
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- 239000000758 substrate Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 149
- 229920005591 polysilicon Polymers 0.000 claims abstract description 149
- 238000000034 method Methods 0.000 claims abstract description 48
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 230000004888 barrier function Effects 0.000 claims description 43
- 239000011248 coating agent Substances 0.000 claims description 18
- 238000000576 coating method Methods 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- 229910004205 SiNX Inorganic materials 0.000 claims description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 230000002035 prolonged effect Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
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Abstract
The invention discloses an LTPS array substrate and a manufacturing method thereof and a display device. The method comprises the steps that a substrate is provided; a light shading layer, a buffer layer and a semiconductor layer are formed on the substrate in turn, wherein the semiconductor layer comprises a first polysilicon layer and a second polysilicon layer which are arranged in a spacing way; N+ doping is performed on the first polysilicon layer, and P+ doping is performed on the second polysilicon layer; a first insulating layer and a gate electrode graph layer are formed on the semiconductor layer in turn; N- doping is performed on the first polysilicon layer; and a second insulating layer and a source-drain layer are formed on the gate electrode graph layer in turn. With application of the method, an N- doping region can be protected in the ion doping process so that performance of components and parts can be enhanced and the service life of the components and parts can be prolonged.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of LTPS array base palte and preparation method thereof, display unit.
Background technology
Low-temperature polysilicon silicon technology LTPS (LowTemperaturePoly-silicon) develops at present just rapidly, and its sharpest edges are ultra-thin, lightweight, low power consumption, can provide more gorgeous color and image more clearly.
In the manufacturing process of LTPS array base palte, polysilicon is being carried out in the processing procedure of ion implantation, first N+ doping, N-doping are carried out to NMOS often, and then P+ doping is carried out to PMOS, as such, P+ doping time probably by P+ ion implantation to N-region, have influence on the performance in N-region, and N-region to the life-span of components and parts and performance impact larger.
Summary of the invention
The technical problem that the present invention mainly solves is to provide a kind of LTPS array base palte and preparation method thereof, display unit, can protect in ion doping process to N-doped region, improves the performance of components and parts, extends the useful life of components and parts.
For solving the problems of the technologies described above, the technical scheme that the present invention adopts is: the manufacture method providing a kind of LTPS array base palte, and the method comprises: provide a substrate; Substrate forms light shield layer, resilient coating and semiconductor layer successively; Wherein, semiconductor layer comprises spaced first polysilicon layer and the second polysilicon layer; N+ doping is carried out to the first polysilicon layer, P+ doping is carried out to the second polysilicon layer; Form the first insulating barrier and gate patterns layer on the semiconductor layer successively; N-doping is carried out to the first polysilicon layer; Gate patterns layer forms the second insulating barrier and source-drain layer successively.
Wherein, substrate is formed the step of light shield layer, resilient coating and semiconductor layer successively, specifically comprises: on substrate, form spaced first light shield layer and the second light shield layer; First light shield layer and the second light shield layer deposit SiNx layer; Deposited SiOx-layers on SiNx layer; SiOx layer forms semiconductor layer.
Wherein, SiOx layer is formed the step of semiconductor layer, specifically comprises: deposition of amorphous silicon layers on SiOx layer, and radium-shine annealing process is carried out to amorphous silicon layer, to form spaced first polysilicon layer and the second polysilicon layer; Wherein, the first polysilicon layer and the second polysilicon layer corresponding first light shield layer and the second light shield layer respectively.
Wherein, N+ doping is carried out to the first polysilicon layer, the second polysilicon layer is carried out to the step of P+ doping, specifically comprise: on the first polysilicon layer, the second polysilicon layer and resilient coating, cover the first photoresistance; Wherein, two N+ doped regions of the transparent area of the first photoresistance corresponding first polysilicon layer in vertical direction; First polysilicon layer comprises the undoped region between two N-doped regions inside two the N+ doped regions being arranged at both sides respectively, two two N+ doped regions and two N-doped regions; N+ doping is carried out to the N+ doped region of the first polysilicon layer; First polysilicon layer, the second polysilicon layer and resilient coating cover the second photoresistance; Wherein, two P+ doped regions of the transparent area of the second photoresistance corresponding second polysilicon layer in vertical direction; Second polysilicon layer comprises the undoped region between two P+ doped regions and two P+ doped regions being arranged at both sides respectively; P+ doping is carried out to the P+ doped region of the second polysilicon layer.
Wherein, form the step of the first insulating barrier and gate patterns layer on the semiconductor layer successively, specifically comprise: form the first insulating barrier on the semiconductor layer; Wherein, the first insulating barrier comprises SiOx and SiNx; Depositing layers on the first insulating barrier, and etch process is carried out to form first grid and second grid to grid layer; Wherein, the undoped region of first grid and second grid corresponding first polysilicon layer of difference and the second polysilicon layer.
Wherein, the first polysilicon layer is carried out to the step of N-doping, specifically comprise: on the first insulating barrier, cover the 3rd photoresistance; Wherein, two N-doped regions of the transparent area of the 3rd photoresistance corresponding first polysilicon layer in vertical direction; N-doping is carried out to the N-doped region of the first polysilicon layer.
Wherein, gate patterns layer is formed the step of the second insulating barrier and source-drain layer successively, specifically comprises: on gate patterns layer, form the second insulating barrier; Form the first through hole, the second through hole, third through-hole and the fourth hole that run through the first insulating barrier and the second insulating barrier; Form the first source electrode, the first drain electrode, the second source electrode and the second drain electrode over the second dielectric; Wherein, first source electrode and first drains and is connected two N+ doping connections of the first polysilicon layer respectively by the first through hole with the second through hole, and the second source electrode and the second drain electrode are connected two P+ doping connections of the second polysilicon layer with fourth hole respectively by third through-hole.
Wherein, N+ doping is carried out to the first polysilicon layer, before the second polysilicon layer being carried out to the step of P+ doping, also comprise: P doping is carried out to the first polysilicon layer and the second polysilicon layer, to adjust the electrology characteristic of the first polysilicon layer and the second polysilicon layer.
For solving the problems of the technologies described above, another technical solution used in the present invention is: provide a kind of LTPS array base palte, this array base palte comprises: substrate and the light shield layer, resilient coating, semiconductor layer, the first insulating barrier, grid layer, the second insulating barrier and the source-drain layer that are formed at successively on substrate; Wherein, semiconductor layer comprises spaced first polysilicon layer and the second polysilicon layer; Wherein, when carrying out ion doping to the first polysilicon layer and the second polysilicon layer, first N+ doping being carried out to the first polysilicon layer and P+ doping is carried out to the second polysilicon layer, rear N-doping being carried out to the first polysilicon layer.
For solving the problems of the technologies described above, another technical solution used in the present invention is: provide a kind of display unit, and this display unit comprises LTPS array base palte described above.
The invention has the beneficial effects as follows: the situation being different from prior art, the present invention is in the process making LTPS array base palte, first N+ doping is carried out to the first polysilicon layer and P+ doping is carried out to the second polysilicon layer, after the first insulating barrier is formed, again N-doping is carried out to the first polysilicon layer, in this way, prevent when to carry out P+ doping after first carrying out N-doping, P+ ion easily enters N-doped region, to impact N-doped region.Because the impact of N-region on the life-span of components and parts and performance is comparatively large, so the performance of components and parts can be improved by the way, increase the life-span of components and parts.In addition, because P+ dopping process is placed on before N-dopping process, namely during P+ doping, the surface of second pair of crystal silicon layer does not have the first insulating barrier, so decrease the consumption of P+ ion, saves cost.
Accompanying drawing explanation
Fig. 1 is the flow chart of manufacture method first execution mode of LTPS array base palte of the present invention;
Fig. 2 A is the first structural representation of step 103 in manufacture method first execution mode of LTPS array base palte of the present invention;
Fig. 2 B is the second structural representation of step 103 in manufacture method first execution mode of LTPS array base palte of the present invention;
Fig. 2 C is the structural representation of step 105 in manufacture method first execution mode of LTPS array base palte of the present invention;
Fig. 2 D is the structural representation of step 106 in manufacture method first execution mode of LTPS array base palte of the present invention;
Fig. 3 is the structural representation of manufacture method second execution mode of LTPS array base palte of the present invention;
Fig. 4 is the structural representation of LTPS array base palte one execution mode of the present invention;
Fig. 5 is the structural representation of display unit one execution mode of the present invention.
Embodiment
Consult Fig. 1, the flow chart of manufacture method first execution mode of LTPS array base palte of the present invention, consult Fig. 2 A-Fig. 2 D, the method comprises simultaneously:
Step 101 a: substrate 200 is provided.
This substrate 200 generally adopts glass substrate, when doing flexible curved surface display screen, also can adopt plastic, transparent substrate.
Step 102: form light shield layer 201, resilient coating 202 and semiconductor layer 203 on substrate successively.
Wherein, light shield layer 201 comprises the first light shield layer 2011 and the second light shield layer 2012, with corresponding NMOS and PMOS being about to make of difference.
The step forming resilient coating 202 is specifically as follows: on the first light shield layer 2011 and the second light shield layer 2022, deposit SiNx layer; Deposited SiOx-layers on SiNx layer.That is, resilient coating 202 is jointly superposed by layer of sin x and one deck SiOx and forms.Certainly, also can be one or both mixture in SiNx and SiOx in other embodiments.
In addition, semiconductor layer 203 comprises spaced first polysilicon layer 2031 and the second polysilicon layer 2032.In a concrete implementation process, the step making polysilicon layer is specially: first on resilient coating 202, form amorphous silicon a-si, the crystallization of amorphous silicon a-si is realized again through radium-shine annealing process, to form polysilicon p-si, then by etch process, graphical treatment is carried out to form the first polysilicon layer 2031 and the second polysilicon layer 2032 to polysilicon p-si.It should be noted that the first polysilicon layer 2031 and the second polysilicon layer 2032 are corresponding with the first above-mentioned light shield layer 2011 and the second light shield layer 2012 respectively.
Step 103: carry out N+ doping to the first polysilicon layer 2031, carries out P+ doping to the second polysilicon layer 2032.
First, because the CMOS made comprises NMOS and PMOS, it is corresponding first polysilicon layer 2031 and the second polysilicon layer 2032 respectively, when carrying out ion implantation to NMOS and PMOS, first will determine the ion implanted regions of each polysilicon layer.Wherein, the first polysilicon layer 2031 comprise inner side undoped region, the N+ doped region in outside, the N-doped region between undoped region and N+ doped region.And the second polysilicon layer 2032 comprises the undoped region of inner side and the P+ doped region in outside.
As shown in Figure 2 A, the step that the first polysilicon layer 2031 carries out N+ doping is specially: on the first polysilicon layer, the second polysilicon layer and resilient coating, cover the first photoresistance; Wherein, two N+ doped regions of the transparent area of the first photoresistance corresponding first polysilicon layer in vertical direction; First polysilicon layer comprises the undoped region between two N-doped regions inside two the N+ doped regions being arranged at both sides respectively, two two N+ doped regions and two N-doped regions; Then N+ doping is carried out to the N+ doped region of the first polysilicon layer 2031.
As shown in Figure 2 B, the step that the second polysilicon layer 2032 carries out P+ doping is specially: on the first polysilicon layer, the second polysilicon layer and resilient coating, cover the second photoresistance; Wherein, two P+ doped regions of the transparent area of the second photoresistance corresponding second polysilicon layer in vertical direction; Second polysilicon layer comprises the undoped region between two P+ doped regions and two P+ doped regions being arranged at both sides respectively; Then P+ doping is carried out to the P+ doped region of the second polysilicon layer 2032.
In addition, in step 103, first polysilicon layer 2031 being carried out to N+ doping and carries out P+ doping to the second polysilicon layer 2032 can reversed order mutually, namely first can carry out P+ doping to the second polysilicon layer 2032, rear N+ doping be carried out to the first polysilicon layer 2031.
In other embodiments, N+ doping is carried out at the first polysilicon layer 2031, before second polysilicon layer being carried out to the step of P+ doping, also comprise: P doping is carried out to the first polysilicon layer 2031 and the second polysilicon layer 2032, to adjust the electrology characteristic of the first polysilicon layer 2031 and the second polysilicon layer 2032.
Step 104: form the first insulating barrier 204 and gate patterns layer 205 on semiconductor layer 203 successively.
Wherein, in the ordinary course of things, the first insulating barrier 204 is mixtures of SiOx and SiNx, in other embodiments, also can be replaced by one or both stepped construction wherein.
The step forming gate patterns layer 205 specifically comprises: depositing layers on the first insulating barrier 204, and carries out etch process to form first grid 2051 and second grid 2052 to grid layer; Wherein, the undoped region of first grid 2051 and second grid 2052 corresponding first polysilicon layer 2031 of difference and the second polysilicon layer 2032.
Step 105: N-doping is carried out to the first polysilicon layer 2031.
As Fig. 2 C, wherein, the first polysilicon layer 2031 is carried out to the step of N-doping, specifically comprise: on the first insulating barrier, cover the 3rd photoresistance; Wherein, two N-doped regions of the transparent area of the 3rd photoresistance corresponding first polysilicon layer in vertical direction; Then N-doping is carried out to the N-doped region of the first polysilicon layer.
In above-mentioned dopping process, N+ is doped to the doping of phosphorus high dose, and N-is doped to the doping of phosphorus low dosage, and P+ is doped to the doping of boron high dose.Certainly, in other embodiments, other ion also can be used to inject.
In addition, in above-mentioned Fig. 2 A-2C, the concrete steps covering photoresistance comprise: coating one deck photoresistance, on photoresistance, then design transparent area and alternatively non-transparent district, and by series of process such as exposure, development, etchings, to form the effigurate photoresist layer of tool.Transparent area is wherein the region not covering photoresistance, and the photoresistance in this region can be stripped after the etching.
Step 106: form the second insulating barrier 206 and source-drain layer 207 on gate patterns layer 205 successively.
As Fig. 2 D, concrete, gate patterns layer 205 is formed the second insulating barrier 206; Form the first through hole, the second through hole, third through-hole and the fourth hole that run through the first insulating barrier 204 and the second insulating barrier 206; Second insulating barrier 206 is formed the first source electrode 2071, first drain electrode 2072, second source electrode 2073 and the second drain electrode 2074; Wherein, first source electrode 2071 and the first drain electrode 2072 to be connected the first polysilicon layer 2031 respectively by the first through hole two N+ doping with the second through hole connect, and the second source electrode 2073 and the second drain electrode 2074 to be connected the second polysilicon layer 2032 respectively by third through-hole two P+ doping with fourth hole connect.
What deserves to be explained is, the position of the first through hole, the second through hole, third through-hole and fourth hole does not identify in the drawings, but it will be appreciated by those skilled in the art that the first through hole, the second through hole, third through-hole and fourth hole drain with the first source electrode 2071, first respectively the 2072, second source electrode 2073 and second drain 2074 position corresponding.
Be different from prior art, present embodiment is in the process making LTPS array base palte, first N+ doping is carried out to the first polysilicon layer and P+ doping is carried out to the second polysilicon layer, after the first insulating barrier is formed, again N-doping is carried out to the first polysilicon layer, in this way, prevent when to carry out P+ doping after first carrying out N-doping, P+ ion easily enters N-doped region, to impact N-doped region.Because the impact of N-region on the life-span of components and parts and performance is comparatively large, so the performance of components and parts can be improved by the way, increase the life-span of components and parts.In addition, because P+ dopping process is placed on before N-dopping process, namely during P+ doping, the surface of second pair of crystal silicon layer does not have the first insulating barrier, so decrease the consumption of P+ ion, saves cost.
Consult Fig. 3, the structural representation of manufacture method second execution mode of LTPS array base palte of the present invention.
The process of present embodiment and manufacture method first execution mode of above-mentioned LTPS array base palte similar, difference is:
As shown in Figure 3, when carrying out N-doping to the first polysilicon layer 301, do not adopt photoresistance to block to other parts, do if so, then, when carrying out P+ doping in the processing procedure above, the concentration of P+ ion can be increased a little.
Be different from above-mentioned execution mode, present embodiment in the processing procedure of ion implantation, can reduce the usage quantity of photoresistance.
Consult Fig. 4, the structural representation of LTPS array base palte one execution mode of the present invention, this array base palte comprises: substrate 400 and the light shield layer 401, resilient coating 402, semiconductor layer 403, first insulating barrier 404, grid layer 405, second insulating barrier 406 and the source-drain layer 407 that are formed at successively on substrate 400; Wherein, semiconductor layer 403 comprises spaced first polysilicon layer 4031 and the second polysilicon layer 4032.
Wherein, when carrying out ion doping to the first polysilicon layer 4031 and the second polysilicon layer 4032, first N+ doping being carried out to the first polysilicon layer and P+ doping is carried out to the second polysilicon layer, rear N-doping being carried out to the first polysilicon layer.
By the way, prevent when to carry out P+ doping after first carrying out N-doping, P+ ion easily enters N-doped region, to impact N-doped region.Because the impact of N-region on the life-span of components and parts and performance is comparatively large, so the performance of components and parts can be improved by the way, increase the life-span of components and parts.In addition, because P+ dopping process is placed on before N-dopping process, namely during P+ doping, the surface of second pair of crystal silicon layer does not have the first insulating barrier, so decrease the consumption of P+ ion, saves cost.
Consult Fig. 5, the structural representation of display unit one execution mode of the present invention, this display unit comprises display floater 510 and backlight 520, and wherein, display floater 510 comprises color membrane substrates 511, LTPS array base palte 513 and the liquid crystal layer between color membrane substrates 511 and LTPS array base palte 513 512.Particularly, this LTPS array base palte 513 is as the array base palte in each execution mode above-mentioned.
What deserves to be explained is, in LTPS array base palte one execution mode and display unit one execution mode, the execution mode of its execution mode and above-mentioned LTPS array substrate manufacturing method is similar, repeats no more here.
The foregoing is only embodiments of the present invention; not thereby the scope of the claims of the present invention is limited; every utilize specification of the present invention and accompanying drawing content to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.
Claims (10)
1. a manufacture method for LTPS array base palte, is characterized in that, comprising:
One substrate is provided;
Form light shield layer, resilient coating and semiconductor layer successively on the substrate; Wherein, described semiconductor layer comprises spaced first polysilicon layer and the second polysilicon layer;
N+ doping is carried out to described first polysilicon layer, P+ doping is carried out to described second polysilicon layer;
Described semiconductor layer is formed the first insulating barrier and gate patterns layer successively;
N-doping is carried out to described first polysilicon layer;
Described gate patterns layer forms the second insulating barrier and source-drain layer successively.
2. method according to claim 1, is characterized in that, forms the step of light shield layer, resilient coating and semiconductor layer on the substrate successively, specifically comprises:
Form spaced first light shield layer and the second light shield layer on the substrate;
Described first light shield layer and described second light shield layer deposit SiNx layer;
Deposited SiOx-layers on described SiNx layer;
Described SiOx layer forms semiconductor layer.
3. method according to claim 2, is characterized in that, described SiOx layer is formed the step of semiconductor layer, specifically comprises:
Deposition of amorphous silicon layers on described SiOx layer, and radium-shine annealing process is carried out to described amorphous silicon layer, to form spaced first polysilicon layer and the second polysilicon layer;
Wherein, described first polysilicon layer and the second polysilicon layer corresponding described first light shield layer and the second light shield layer respectively.
4. method according to claim 1, is characterized in that, carries out N+ doping to described first polysilicon layer, described second polysilicon layer is carried out to the step of P+ doping, specifically comprises:
Described first polysilicon layer, described second polysilicon layer and described resilient coating cover the first photoresistance; Wherein, two N+ doped regions of the transparent area of described first photoresistance corresponding described first polysilicon layer in vertical direction; Described first polysilicon layer comprises the undoped region between two N-doped regions inside two the N+ doped regions being arranged at both sides respectively, described two two N+ doped regions and described two N-doped regions;
N+ doping is carried out to the N+ doped region of described first polysilicon layer;
Described first polysilicon layer, described second polysilicon layer and described resilient coating cover the second photoresistance; Wherein, two P+ doped regions of the transparent area of described second photoresistance corresponding described second polysilicon layer in vertical direction; Described second polysilicon layer comprises the undoped region between two P+ doped regions and described two P+ doped regions being arranged at both sides respectively;
P+ doping is carried out to the P+ doped region of described second polysilicon layer.
5. method according to claim 4, is characterized in that, described semiconductor layer is formed the step of the first insulating barrier and gate patterns layer successively, specifically comprises:
Described semiconductor layer is formed the first insulating barrier; Wherein, described first insulating barrier comprises SiOx and SiNx;
Depositing layers on described first insulating barrier, and etch process is carried out to form first grid and second grid to described grid layer; Wherein, the undoped region of described first grid and corresponding described first polysilicon layer of second grid difference and the second polysilicon layer.
6. method according to claim 5, is characterized in that, described first polysilicon layer is carried out to the step of N-doping, specifically comprises:
Described first insulating barrier covers the 3rd photoresistance; Wherein, two N-doped regions of the transparent area of described 3rd photoresistance corresponding described first polysilicon layer in vertical direction;
N-doping is carried out to the N-doped region of described first polysilicon layer.
7. method according to claim 1, is characterized in that, described gate patterns layer is formed the step of the second insulating barrier and source-drain layer successively, specifically comprises:
Described gate patterns layer forms the second insulating barrier;
Form the first through hole, the second through hole, third through-hole and the fourth hole that run through described first insulating barrier and described second insulating barrier;
Described second insulating barrier is formed the first source electrode, the first drain electrode, the second source electrode and the second drain electrode; Wherein, described first source electrode and first drains and is connected two N+ doping connections of described first polysilicon layer respectively by described first through hole with the second through hole, and described second source electrode and the second drain electrode are connected two P+ doping connections of described second polysilicon layer with fourth hole respectively by described third through-hole.
8. method according to claim 1, is characterized in that, carries out N+ doping to described first polysilicon layer, before carrying out the step of P+ doping, also comprises described second polysilicon layer:
P doping is carried out to described first polysilicon layer and described second polysilicon layer, to adjust the electrology characteristic of described first polysilicon layer and described second polysilicon layer.
9. a LTPS array base palte, is characterized in that, comprising:
Substrate and the light shield layer, resilient coating, semiconductor layer, the first insulating barrier, grid layer, the second insulating barrier and the source-drain layer that are formed at successively on described substrate;
Wherein, described semiconductor layer comprises spaced first polysilicon layer and the second polysilicon layer;
Wherein, when carrying out ion doping to described first polysilicon layer and the second polysilicon layer, first N+ doping being carried out to described first polysilicon layer and P+ doping is carried out to described second polysilicon layer, rear N-doping being carried out to described first polysilicon layer.
10. a display unit, is characterized in that, described display unit comprises the LTPS array base palte as described in any one of claim 1-9.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106653695A (en) * | 2016-12-27 | 2017-05-10 | 武汉华星光电技术有限公司 | Low-temperature polycrystalline silicon array substrate and manufacturing method thereof |
| CN107154381A (en) * | 2017-05-11 | 2017-09-12 | 京东方科技集团股份有限公司 | Display base plate and its manufacture method, display device |
| CN108538860A (en) * | 2018-04-27 | 2018-09-14 | 武汉华星光电技术有限公司 | The production method of top gate type amorphous-silicon TFT substrate |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1525554A (en) * | 2003-02-26 | 2004-09-01 | 友达光电股份有限公司 | Method for producing low-temperature polysilicon thin film transistor |
| US20040197967A1 (en) * | 2003-04-04 | 2004-10-07 | Kun-Hong Chen | Method for forming a low temperature polysilicon CMOS thin film transistor |
| CN103268047A (en) * | 2012-12-31 | 2013-08-28 | 厦门天马微电子有限公司 | LTPS (Low Temperature Poly-silicon) array base plate and manufacturing method thereof |
| CN104466020A (en) * | 2014-12-12 | 2015-03-25 | 深圳市华星光电技术有限公司 | LTPS pixel unit and manufacturing method thereof |
| CN104538307A (en) * | 2014-12-19 | 2015-04-22 | 深圳市华星光电技术有限公司 | Polycrystalline silicon thin film transistor manufacturing method |
-
2015
- 2015-09-30 CN CN201510639246.8A patent/CN105336683A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1525554A (en) * | 2003-02-26 | 2004-09-01 | 友达光电股份有限公司 | Method for producing low-temperature polysilicon thin film transistor |
| US20040197967A1 (en) * | 2003-04-04 | 2004-10-07 | Kun-Hong Chen | Method for forming a low temperature polysilicon CMOS thin film transistor |
| CN103268047A (en) * | 2012-12-31 | 2013-08-28 | 厦门天马微电子有限公司 | LTPS (Low Temperature Poly-silicon) array base plate and manufacturing method thereof |
| CN104466020A (en) * | 2014-12-12 | 2015-03-25 | 深圳市华星光电技术有限公司 | LTPS pixel unit and manufacturing method thereof |
| CN104538307A (en) * | 2014-12-19 | 2015-04-22 | 深圳市华星光电技术有限公司 | Polycrystalline silicon thin film transistor manufacturing method |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106653695A (en) * | 2016-12-27 | 2017-05-10 | 武汉华星光电技术有限公司 | Low-temperature polycrystalline silicon array substrate and manufacturing method thereof |
| WO2018119866A1 (en) * | 2016-12-27 | 2018-07-05 | 武汉华星光电技术有限公司 | Low-temperature polysilicon array substrate and manufacturing method thereof |
| CN106653695B (en) * | 2016-12-27 | 2018-07-06 | 武汉华星光电技术有限公司 | A kind of low temperature polycrystalline silicon array substrate and preparation method thereof |
| US10134907B2 (en) | 2016-12-27 | 2018-11-20 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Low temperature polysilicon array substrate and method for manufacturing the same |
| CN107154381A (en) * | 2017-05-11 | 2017-09-12 | 京东方科技集团股份有限公司 | Display base plate and its manufacture method, display device |
| CN107154381B (en) * | 2017-05-11 | 2020-03-13 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof and display device |
| CN108538860A (en) * | 2018-04-27 | 2018-09-14 | 武汉华星光电技术有限公司 | The production method of top gate type amorphous-silicon TFT substrate |
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