CN106847828B - Low-temperature polycrystalline silicon array substrate and manufacturing method thereof - Google Patents
Low-temperature polycrystalline silicon array substrate and manufacturing method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Abstract
The invention provides a low-temperature polysilicon array substrate structure, which comprises: a substrate; an active layer over the substrate; a first gate insulating layer over the active layer; a first gate layer over the first gate insulating layer, the first gate layer over an active layer; a second gate insulating layer covering the first gate layer; a second gate layer over the second gate insulating layer, the second gate layer being over the first gate layer. The invention is beneficial to solving the defects of uneven display caused by uneven threshold voltage of the polycrystalline silicon thin film transistor and the problem of drift of the threshold voltage in the process or the use process in the prior art, and simultaneously, the process complexity is not increased.
Description
Technical Field
The invention relates to the technical field of display devices, in particular to a low-temperature polycrystalline silicon array substrate and a manufacturing method thereof.
Background
The low-temperature polysilicon array substrate has the advantages of high mobility (which can be hundreds of times of amorphous silicon), the size of a thin film transistor can be made very small, the reaction speed is high, the low-temperature polysilicon array substrate is an array substrate of a display panel which is more and more appreciated in recent years, and the low-temperature polysilicon array substrate is more and more adopted on organic electroluminescent display and liquid crystal display panels with high resolution and high image quality. However, the low-temperature polysilicon array substrate is generally complex in structure and has various technological processes, particularly, because the polysilicon prepared by the currently mainstream excimer laser crystallization method is difficult to keep consistent in uniformity, the uniformity of the threshold voltage is poor, and the display defect is easily formed when the low-temperature polysilicon array substrate is used for driving a display device.
Since the threshold voltage of the polysilicon thin film transistor has an important influence on the display driving performance of the display device, various measures are adopted in the prior art to solve the problem that the uniformity of the threshold voltage of the polysilicon thin film transistor is not good. However, these approaches require expensive and demanding equipment, and they add new processes and complexity to the fabrication of low temperature polysilicon array substrates. The problem of uneven threshold voltage of a polycrystalline silicon thin film transistor in the prior art is solved without increasing process complexity due to lack of effective means in the prior art.
Disclosure of Invention
In view of the above problems in the prior art, an object of the present invention is to provide a low temperature polysilicon array substrate and a method for manufacturing the same, which can solve the problem of non-uniform threshold voltage of polysilicon tfts in the prior art without increasing the process complexity.
In order to achieve the purpose, the invention adopts the following technical scheme.
The invention provides a low-temperature polysilicon array substrate structure, which comprises: a substrate; an active layer over the substrate; a first gate insulating layer over the active layer; a first gate layer over the first gate insulating layer, the first gate layer over the active layer; a second gate insulating layer covering the first gate layer; a second gate layer over the second gate insulating layer, the second gate layer being over the first gate layer.
The low-temperature polysilicon array substrate structure also comprises a first capacitance electrode layer which is arranged on the first gate insulating layer and covered by the second gate insulating layer and a second capacitance electrode layer which is arranged on the second gate insulating layer, wherein the first capacitance electrode layer is arranged on one side of the substrate far away from the active layer, and the second capacitance electrode layer is arranged above the first capacitance electrode layer
Wherein the first gate insulating layer has a thickness of 10nm to 40 nm.
The first gate layer and the second gate layer are of a single-layer structure, a two-layer structure or a structure with more than two layers.
Wherein the thickness of the first gate layer and the second gate layer is 100nm to 500nm
The invention also provides a manufacturing method of the low-temperature polysilicon array substrate structure, which comprises the following steps: forming an active layer on a substrate; forming a first gate insulating layer on the substrate to cover the active layer; forming a first gate electrode layer and a first capacitor electrode layer over the first gate insulating layer, the first gate electrode layer being formed over the active layer, the first capacitor electrode layer being formed on a side of the substrate away from the active layer; forming a second gate insulating layer covering the first gate layer and the first capacitor electrode layer; and forming a second gate layer and a second capacitor electrode layer on the second gate insulating layer, wherein the second gate layer is formed over the first gate layer, and the second capacitor electrode layer is formed over the first capacitor electrode layer.
Wherein the forming of the first gate electrode layer and the first capacitor electrode layer over the first gate insulating layer includes: forming a metal layer on the first gate insulating layer, patterning the metal layer, and simultaneously forming the first gate electrode layer and the first capacitor electrode layer.
Wherein the forming of the second gate layer and the second capacitor electrode layer on the second gate insulating layer includes: and forming a metal layer on the second gate insulating layer, patterning the metal layer, and simultaneously forming the second gate electrode layer and the second capacitor electrode layer.
Wherein the first gate insulating layer has a thickness of 10nm to 40 nm.
The first gate layer and the second gate layer are of a single-layer structure, a two-layer structure or a structure with more than two layers, and the thickness of the first gate layer and the second gate layer is 100nm to 500 nm.
The low-temperature polycrystalline silicon array substrate and the manufacturing method thereof adopt a double-layer grid structure, and electrons in a channel form a hot electron effect by simultaneously applying high voltage to an upper grid and a drain, and are injected into a lower grid to accumulate charges, so that the threshold voltage uniformity of a thin film transistor is adjusted. The method is favorable for solving the defects of uneven display caused by uneven threshold voltage of the polycrystalline silicon thin film transistor in the prior art and the problems of difficult driving of a display device or screen dot defects caused by drift of the threshold voltage in the process or the use process, and simultaneously, the double-layer grid structure and the double-layer grid capacitor structure are formed simultaneously, so that the process complexity is not increased.
Drawings
Fig. 1 is a schematic structural diagram of a low temperature polysilicon array substrate according to an embodiment of the invention.
Fig. 2 shows a method for adjusting threshold voltage of a thin film transistor in a low temperature polysilicon array substrate according to an embodiment of the invention.
Fig. 3 to 8 are process flow diagrams illustrating a process of manufacturing a low temperature polysilicon array substrate according to an embodiment of the present invention.
Wherein the reference numerals are as follows:
101. a substrate; 102. an active layer; 103. a first gate insulating layer; 104. a first gate layer; 105. a first capacitance electrode layer; 106. a second gate insulating layer; 107. a second gate layer; 108. a second capacitance electrode layer; 109. a source electrode; 110. a drain electrode; 111. a charge; 501. 801, a metal layer.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
The embodiment provides a low temperature polysilicon array substrate, and fig. 1 shows the structure of the low temperature polysilicon array substrate according to the embodiment of the invention.
As shown in fig. 1, the low temperature polysilicon array substrate according to the present embodiment includes: a substrate 101; an active layer 102 disposed on the substrate 101; a first gate insulating layer 103 disposed on the active layer 102, the first insulating layer 103 covering the active layer 102 and extending on the substrate 101; a first gate layer 104 formed on the first insulating layer 103, the first gate layer 104 being above the active layer 102, the first insulating layer 103 further including a first capacitor electrode layer 105, the first capacitor electrode layer 105 being formed on the substrate 101 at a side away from the active layer 102; a second gate insulating layer 106 covering the first gate layer 104 and the first capacitor electrode layer 105 and extending over the first gate insulating layer 103; a second gate electrode layer 107 and a second capacitor electrode layer 108 over the second gate insulating layer 106, the second gate electrode layer 107 over the first gate electrode layer 104, and the second capacitor electrode layer 108 over the first capacitor electrode layer 105.
For the low temperature polysilicon array substrate according to the present embodiment, the substrate 101 may be a transparent substrate such as glass that is cleaned in advance, and a buffer layer (not shown in the figure) formed by silicon oxide, silicon nitride or a stack of the two may be further included on the substrate 101 to prevent metal ion impurities in the transparent substrate from diffusing into the active layer and affecting the operating characteristics of the thin film transistor. The substrate 101 may be a flexible substrate made of an organic thin film. The active layer 102 has a thickness of between 10nm and 300nm, preferably between 50nm and 100 nm. The first gate insulating layer 102 and the second gate insulating layer 106 may use a single layer of silicon oxide, silicon nitride, or a stack of the two, and have a thickness of 10nm to 200 nm. For the first gate insulating layer, in order to facilitate hot electron injection, the thickness of the first insulating layer is set to be between 10nm and 40 nm. The thickness of the second gate insulating layer 106 may be set according to actual requirements for the storage capacitance. The first gate layer 104, the second gate layer 107, the first capacitor electrode layer 105, and the second capacitor electrode layer 108 may be a single layer, two layers, or more than two layers, and may be formed of a metal, a metal alloy such as molybdenum, aluminum, molybdenum tungsten, or the like, and have a thickness of 100nm to 500nm, preferably 150nm to 400 nm.
The low-temperature polysilicon array substrate according to the embodiment has a double-gate structure, and can adjust the threshold voltage uniformity of the thin film transistor. Fig. 2 shows a method for adjusting threshold voltage of a thin film transistor in a low temperature polysilicon array substrate according to an embodiment of the invention. The method for adjusting the threshold voltage of the thin film transistor is described in detail below with reference to fig. 2.
As shown in fig. 2, two gate layers, i.e., a first gate layer 104 and a second gate layer 107, are formed in the left thin film transistor region in fig. 2. Charge accumulation is formed in the first gate layer 104 by channel hot electron injection (channel hot electron injection is a common "write" operation in flash memories), so that the voltage applied to the second gate layer 107 is changed, and the threshold voltage of the tft device is changed. The operation principle is that when a high voltage, such as greater than 10V (for example, an N-type tft, a P-type tft is less than-10V) is applied to the drain 110 and the second gate layer 107, electrons 111 in the channel gain high energy under the acceleration of the lateral electric field between the source 109 and the drain 110, and impact ionization occurs near the drain to generate high-energy electrons. Since the first gate layer 104 is also applied with a high voltage, electrons are attracted, and a part of the electrons jump over the barrier (3.2 ev for silicon oxide) of the first gate insulating layer 103 and enter the first gate layer 104. Since the upper and lower portions of the first gate layer 104 are covered by the insulating layer, the entered electrons are not lost, so that an additional electric field is formed to the channel, and the size of the threshold voltage of the thin film transistor can be adjusted by matching with the second gate layer 107.
Therefore, the low-temperature polysilicon array substrate according to the embodiment has a dual-gate structure, can adjust the threshold voltage uniformity of the thin film transistor, and is beneficial to solving the problems that the threshold voltage of the polysilicon thin film transistor in the prior art is not uniform, so that the display is not uniform, and the threshold voltage drifts in the process or use process, so that the display device is difficult to drive or has a dot screen defect.
Example two
The present embodiment provides a method for manufacturing a low temperature polysilicon array substrate, which is used to manufacture the low temperature polysilicon array substrate described in the first embodiment. Fig. 3 to 8 are process flow diagrams illustrating a process of manufacturing a low temperature polysilicon array substrate according to an embodiment of the present invention.
As shown in fig. 3 to 8, the method for manufacturing a polysilicon array substrate according to the present embodiment includes the following steps.
As shown in fig. 3, first, in step S1, a transparent substrate such as glass cleaned in advance is provided as the substrate 101, and a buffer layer including silicon oxide, silicon nitride or a stack of the two may be formed on the substrate 101 to prevent metal ion impurities in the transparent substrate from diffusing into the active layer and affecting the TFT operation characteristics. Or by using organic compoundsA flexible substrate made of a thin film. The active layer 102 is deposited on the substrate 101 by PECVD, LPCVD, etc. at a temperature of 600 c, and the thickness of the deposited active layer 102 is between 10nm and 300nm, preferably between 50nm and 100 nm. The ion implantation process used to form the active layer 102 may be ion implantation with a mass analyzer, ion cloud implantation without a mass analyzer, plasma implantation, or solid state diffusion implantation. In the preferred embodiment of the present invention, a mainstream ion cloud implantation method is adopted, and a mixed gas containing boron such as B2H6/H2 or phosphorus such as PH3/H2 is adopted for implantation according to design requirements, wherein the ion implantation energy can be 10-200 keV, and the preferred energy is 40-100 keV. The implantation dose can be 1x1011 to 1x1020atoms/cm3In the range of 1x1014 to 1x1018atoms/cm3. It should be noted that, in the specific process, the processes of dehydrogenation by heat treatment, metal induction by deposition, crystallization by heat treatment, crystallization by excimer laser irradiation, impurity doping activation, etc. need to be added according to the circumstances, but the invention also has beneficial effects
As shown in fig. 4, next, in step S2, a first gate insulating layer 103 is deposited on the substrate 101 by PECVD, LPCVD, APCVD, ECR-CVD or the like, and the first gate insulating layer 103 may be a single layer of silicon oxide, silicon nitride or a stack of the two, and the thickness thereof is set to be between 10nm and 200nm, so as to facilitate hot electron injection. The first gate insulating layer 103 covers the active layer 102 and extends on the substrate 101.
As shown in fig. 5, next, in step S3, a metal layer 501 is deposited on the first gate insulating layer 103, where the metal layer 501 may be a single layer, two layers or more, and is composed of metal, metal alloy such as molybdenum, aluminum, molybdenum tungsten, etc. and has a thickness of 100nm to 500 nm. The metal layer 501 covers the first gate insulating layer 103.
As shown in fig. 6, next, in step S4, the metal layer 501 is subjected to patterning processing, and the first gate layer 104 and the first capacitor electrode layer 105 are formed at the same time. A first gate layer 104 and a first capacitor electrode layer 105 are formed at different positions on the first gate insulating layer 103, the first gate layer 104 is formed on the active layer 102, and the first capacitor electrode layer 105 is formed on the first gate insulating layer 103 at a side away from the active layer 102. .
As shown in fig. 7, next, in step S5, a second gate insulating layer 106 is formed to cover the first gate electrode layer 104 and the first capacitor electrode layer 105, the second gate insulating layer 106 is formed by the same process as the first gate insulating layer 103, and the thickness of the second gate insulating layer 106 can be set according to the design requirement of the storage capacitor.
As shown in fig. 8, next, in step S6, a metal layer 801 is formed to cover the second gate insulating layer 106, wherein the metal layer 801 may have a single-layer structure, a two-layer structure, or a structure with more than two layers, and is composed of metal or metal alloy such as molybdenum, aluminum, molybdenum tungsten, etc. and has a thickness of 100nm to 500 nm. The metal layer 801 covers the second gate insulating layer 106.
Next, in step S7, the metal layer 801 is patterned to simultaneously form the second gate layer 107 and the second capacitor electrode layer 108, so as to obtain the structure of the low temperature polysilicon array substrate shown in fig. 1. The second gate layer 107 and the second capacitor electrode layer 108 are formed at different positions on the second gate insulating layer 106, and the second gate layer 107 is formed on the first gate layer 107 to form a double-gate structure of the polysilicon array substrate together with the first gate layer 104. The second capacitor electrode layer 108 is formed above the first capacitor electrode layer 105, and the first capacitor electrode layer 105, the second capacitor electrode layer 108 and the second gate insulating layer 106 together form a storage capacitor structure of the polysilicon array substrate.
Therefore, according to the method for manufacturing the low temperature polysilicon array substrate of the present embodiment, the first gate layer 104 and the second capacitor electrode layer 105 are simultaneously formed in one step by using the same process, and the second gate layer 107 and the second capacitor electrode layer 108 are also simultaneously formed in one step by using the same process, so that new process steps are not added while the dual-gate structure of the low temperature polysilicon array substrate is formed, the complexity of the process is not increased, and the threshold voltage of the thin film transistor can be adjusted at low cost.
The low-temperature polycrystalline silicon array substrate has a double-gate structure, and the threshold voltage of the thin film transistor is adjusted by simultaneously increasing the voltage of the source electrode and the drain electrode so that the gate electrode layer stores charges, so that the uniformity of the threshold voltage of the thin film transistor is adjusted, and the problems that the display is not uniform due to the non-uniform threshold voltage of the polycrystalline silicon thin film transistor and the display device is difficult to drive or has a point screen defect due to the drift of the threshold voltage in the process or the use process in the prior art are solved. The manufacturing method of the low-temperature polycrystalline silicon array substrate can form a double-gate structure of the low-temperature polycrystalline silicon array substrate under the condition of not increasing the process, does not increase the process complexity and reduces the cost.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the principles of the technology employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the appended claims.
Claims (8)
1. A low temperature polysilicon array substrate structure, comprising:
a substrate;
an active layer over the substrate;
a first gate insulating layer over the active layer;
a first gate layer over the first gate insulating layer, the first gate layer over the active layer;
a second gate insulating layer covering the first gate layer;
a second gate layer over the second gate insulating layer, the second gate layer being over the first gate layer;
the two ends of the second gate layer are overlapped with the two ends of the first gate layer in the orthographic projection of the substrate, and the thickness of the first gate insulating layer is 10nm to 40nm, so that charge accumulation can be formed in the first gate layer (104) when channel hot electrons are injected, and the voltage required to be applied on the second gate layer is changed.
2. The low temperature polysilicon array substrate structure of claim 1, further comprising a first capacitance electrode layer disposed over the first gate insulating layer and covered by the second gate insulating layer, the first capacitance electrode layer being on a side of the substrate away from the active layer, and a second capacitance electrode layer disposed over the second gate insulating layer, the second capacitance electrode layer being above the first capacitance electrode layer.
3. The LTPS array substrate structure of claim 1 or 2, wherein the first gate layer and the second gate layer are a single layer, two layers or more.
4. The LTPS array substrate structure of claim 3, wherein the thickness of the first gate layer and the second gate layer is 100nm to 500 nm.
5. A manufacturing method of a low-temperature polysilicon array substrate structure comprises the following steps:
forming an active layer on a substrate;
forming a first gate insulating layer on the substrate to cover the active layer;
forming a first gate layer and a first capacitor electrode layer on the first gate insulating layer, wherein the first gate layer is formed above the active layer, and the first capacitor electrode layer is formed on the substrate at a side far away from the active layer;
forming a second gate insulating layer covering the first gate layer and the first capacitor electrode layer;
forming a second gate layer and a second capacitor electrode layer over a second gate insulating layer, wherein the second gate layer is formed over the first gate layer and the second capacitor electrode layer is formed over the first capacitor electrode layer;
the two ends of the second grid layer are overlapped with the two ends of the first grid layer in the orthographic projection of the substrate, and the thickness of the first grid insulating layer is 10nm to 40nm, so that charge accumulation can be formed in the first grid layer when channel hot electrons are injected, and the voltage required to be applied to the second grid layer is changed.
6. The method of claim 5, wherein the forming the first gate layer and the first capacitor electrode layer on the first gate insulating layer comprises: and forming a metal layer on the first gate insulating layer, patterning the metal layer, and simultaneously forming the first gate layer and the first capacitor electrode layer.
7. The method of claim 5, wherein the forming of the second gate layer and the second capacitor electrode layer on the second gate insulating layer comprises: and forming a metal layer on the second gate insulating layer, patterning the metal layer, and simultaneously forming the second gate layer and the second capacitor electrode layer.
8. The method of claim 5, wherein the first and second gate layers are single layer, two layer or more, and have a thickness of 100nm to 500 nm.
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