CN105047603A - Processing method for hybrid bonding metal protruded interface - Google Patents
Processing method for hybrid bonding metal protruded interface Download PDFInfo
- Publication number
- CN105047603A CN105047603A CN201510355711.5A CN201510355711A CN105047603A CN 105047603 A CN105047603 A CN 105047603A CN 201510355711 A CN201510355711 A CN 201510355711A CN 105047603 A CN105047603 A CN 105047603A
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- Prior art keywords
- metal
- thin layer
- silicon nitride
- interface
- nitride layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention relates to a processing method for hybrid bonding metal protruded interface. The method comprises following steps. A to-be-processed wafer is provided. The surface of the wafer is provided with a silicon nitride layer and a thin layer is deposited on the silicon nitride layer. The upper face of the thin layer is coated with photoresist, and a groove is formed in the thin layer and the silicon nitride layer through a photoetching method and an etching method successively. A metal deposition method is utilized to deposite metal to fill the groove and cover the upper face of the thin layer. A chemical mechanical polishing method is utilized to remove metallic copper at the surface of the thin layer and partial thin layer to ensure that the metallic copper at the upper part of the groove is completely removed. The thin layer is then etched to form a metal protruded interface between the thin layer and the metal. The process of etching and stop at the silicon nitride layer continues to form a metal protruded interface between the silicon nitride layer and the metal. According to the invention, the processing method rids the difficulties of manufacturing a protruded bonding surface of metal for the hardness of an insulation material through a chemical machinery grinding method, thereby achieving a good effect.
Description
Technical field
The present invention relates to field of semiconductor manufacture, be specifically related to the processing method that a kind of hybrid bonded metal gives prominence to interface.
Background technology
When very lagre scale integrated circuit (VLSIC) development is day by day close to physics limit, the three dimensional integrated circuits all in physical size and cost aspect with advantage is the effective way extending Moore's Law and solve Advanced Packaging problem.And one of wafer bond techniques key technology that three-dimensional circuit is integrated just, especially hybrid bonded technology can realize the interconnected of thousands of chip while two panels wafer bonding, greatly can improve chip performance and cost-saving.Hybrid bonded technology refers to bonding pattern wafer bonding interface existing simultaneously metal and megohmite insulant.
There is metal and megohmite insulant in hybrid bonded surface, produce metal and to give prominence to or the bonded interface that caves in effectively can lower the requirement of bonding effects on surface flatness simultaneously.But when megohmite insulant is harder, be difficult to obtain the outstanding interface of metal by traditional chemical and mechanical grinding method.
Summary of the invention
The object of this invention is to provide a kind of process for treating surface, give prominence to bonding surface to manufacture metal required in hybrid bonded technology.
For solving the problems of the technologies described above, the invention provides the processing method that a kind of hybrid bonded metal gives prominence to interface, comprising the steps:
Step one, provide a pending wafer, described crystal column surface is formed with a silicon nitride layer, deposit one thin layer on described silicon nitride layer;
Step 2, coating photoresist covers the upper surface of described thin layer, adopts photoetching successively, lithographic method forms groove in described thin layer and silicon nitride layer;
Step 3, utilizes metal deposition depositing metal to fill described groove and covers described thin layer upper surface;
Step 4, utilizes chemical and mechanical grinding method to remove the metallic copper of described thin-film surface and the thin layer of part, guarantees that the metallic copper above described groove is all removed;
Step 5, etches described thin layer, and the metal obtained between described thin layer and metal gives prominence to interface; Continue etching, etching terminates in described silicon nitride layer, and the metal obtained between described silicon nitride layer and metal gives prominence to interface.
Preferably, the material of described thin layer is silicon dioxide or carborundum.
The invention has the beneficial effects as follows: the present invention's hardness can ignored due to megohmite insulant is brought, and cannot manufacture by conventional art (as cmp) difficulty that metal gives prominence to bonding surface.
Accompanying drawing explanation
Fig. 1 to Fig. 6 is the processing method embodiment flow process generalized section that a kind of hybrid bonded metal of the present invention gives prominence to interface.
In accompanying drawing, the list of parts representated by each label is as follows:
1, wafer, 2, silicon nitride layer, 3, thin layer, 4, metal.
Embodiment
Be described principle of the present invention and feature below in conjunction with accompanying drawing, example, only for explaining the present invention, is not intended to limit scope of the present invention.
There is metal and megohmite insulant in hybrid bonded surface, produce metal and to give prominence to or the bonded interface that caves in effectively can lower the requirement of bonding effects on surface flatness simultaneously, but when the megohmite insulant on hybrid bonded surface is harder, be difficult to obtain mixed bond wire by traditional chemical and mechanical grinding method and give prominence to interface, the present invention deposits the softer film of one deck (during as process silicon nitride and metal surface on pending crystal column surface megohmite insulant, in silicon nitride surface deposition layer of silicon dioxide), carry out traditional metal rear end interconnection technology afterwards again, when in the end carrying out surface treatment, first obtain metal and give prominence to interface compared with the metal between flexible film, find the critical point exhausted by film again, namely the metal produced between metal-insulator material gives prominence to interface, thus the hardness can ignored due to megohmite insulant is brought, and cannot manufacture by conventional art (as cmp) difficulty that metal gives prominence to bonding surface.
Fig. 1 to Fig. 6 is the processing method embodiment process structure schematic diagram that a kind of hybrid bonded metal of the present invention gives prominence to interface, and as shown in Figures 1 to 6, a kind of hybrid bonded metal gives prominence to the processing method at interface, comprises the steps:
Step one, provide a pending wafer 1, wafer 1 surface is formed with a silicon nitride layer 2, deposit one thin layer 3 on silicon nitride layer 2; The material of thin layer 3 is silicon dioxide or carborundum;
Step 2, the upper surface of coating photoresist cover layer 3, adopts photoetching successively, lithographic method forms groove in thin layer 3 and silicon nitride layer 2;
Step 3, utilizes metal deposition depositing metal 4 filling groove and cover layer 3 upper surface;
Step 4, utilizes chemical and mechanical grinding method to remove the metallic copper on thin layer 3 surface and the thin layer 3 of part, guarantees that the metallic copper above groove is all removed;
Step 5, etches thin layer 3, and the metal obtained between thin layer 3 and metal gives prominence to interface; Continue etching, etching terminates in silicon nitride layer 2, and the metal obtained between silicon nitride layer 2 and metal gives prominence to interface.
The above implementation step and method only have expressed one embodiment of the present invention, describe comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.Under the prerequisite not departing from inventional idea of the present invention, the distortion done and improvement all should belong to the protection range of patent of the present invention.
Claims (2)
1. hybrid bonded metal gives prominence to the processing method at interface, it is characterized in that, comprises the steps:
Step one, provide a pending wafer, described crystal column surface is formed with a silicon nitride layer, deposit one thin layer on described silicon nitride layer;
Step 2, coating photoresist covers the upper surface of described thin layer, adopts photoetching successively, lithographic method forms groove in described thin layer and silicon nitride layer;
Step 3, utilizes metal deposition depositing metal to fill described groove and covers described thin layer upper surface;
Step 4, utilizes chemical and mechanical grinding method to remove the metallic copper of described thin-film surface and the thin layer of part, guarantees that the metallic copper above described groove is all removed;
Step 5, etches described thin layer, and the metal obtained between described thin layer and metal gives prominence to interface; Continue etching, etching terminates in described silicon nitride layer, and the metal obtained between described silicon nitride layer and metal gives prominence to interface.
2. a kind of hybrid bonded metal gives prominence to the processing method at interface according to claim 1, it is characterized in that, the material of described thin layer is silicon dioxide or carborundum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510355711.5A CN105047603A (en) | 2015-06-24 | 2015-06-24 | Processing method for hybrid bonding metal protruded interface |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510355711.5A CN105047603A (en) | 2015-06-24 | 2015-06-24 | Processing method for hybrid bonding metal protruded interface |
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| CN105047603A true CN105047603A (en) | 2015-11-11 |
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| CN201510355711.5A Pending CN105047603A (en) | 2015-06-24 | 2015-06-24 | Processing method for hybrid bonding metal protruded interface |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109346419A (en) * | 2018-12-05 | 2019-02-15 | 德淮半导体有限公司 | Semiconductor devices and its manufacturing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101197297A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Wafer press welding and bonding method and structure thereof |
| US20100255262A1 (en) * | 2006-09-18 | 2010-10-07 | Kuan-Neng Chen | Bonding of substrates including metal-dielectric patterns with metal raised above dielectric |
| CN104167353A (en) * | 2014-08-08 | 2014-11-26 | 武汉新芯集成电路制造有限公司 | Method for processing surface of bonding substrate |
-
2015
- 2015-06-24 CN CN201510355711.5A patent/CN105047603A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100255262A1 (en) * | 2006-09-18 | 2010-10-07 | Kuan-Neng Chen | Bonding of substrates including metal-dielectric patterns with metal raised above dielectric |
| CN101197297A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Wafer press welding and bonding method and structure thereof |
| CN104167353A (en) * | 2014-08-08 | 2014-11-26 | 武汉新芯集成电路制造有限公司 | Method for processing surface of bonding substrate |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109346419A (en) * | 2018-12-05 | 2019-02-15 | 德淮半导体有限公司 | Semiconductor devices and its manufacturing method |
| CN109346419B (en) * | 2018-12-05 | 2020-11-06 | 德淮半导体有限公司 | Semiconductor device and method for manufacturing the same |
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