CN105261551B - The manufacture of multi-layer circuit assembly - Google Patents

The manufacture of multi-layer circuit assembly Download PDF

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Publication number
CN105261551B
CN105261551B CN201510393754.2A CN201510393754A CN105261551B CN 105261551 B CN105261551 B CN 105261551B CN 201510393754 A CN201510393754 A CN 201510393754A CN 105261551 B CN105261551 B CN 105261551B
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China
Prior art keywords
circuit unit
conductive part
electrical
dielectric material
layer
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Expired - Fee Related
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CN201510393754.2A
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CN105261551A (en
Inventor
L·英格兰
M·A·巴特卡
易万兵
J·B·谭
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GlobalFoundries US Inc
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GlobalFoundries Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31058—After-treatment of organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Coils Or Transformers For Communication (AREA)

Abstract

The present invention relates to the manufacture of multi-layer circuit assembly, provide to be formed seem multi-layer inductor or transformer circuit unit wafer-level method.This method includes, for example: at least one conductive part that the circuit unit is formed in at least one layer of substrate；There is provided uncured polymer dielectric material for electrical at least partly around and cover the conductive part of the component；The partially cured polymer dielectric material for electrical is to obtain the polymer dielectric material for electrical of partially hardened；And the polymer dielectric material for electrical of the partially hardened is polished as low as the height of the current-carrying part.The polishing planarizes the upper surface of the polymer dielectric material for electrical of the partially hardened and the exposure conductive part, in favor of forming at least one remaining conductive part and electrical contact of the component on the conductive part.After polishing, the solidification of the polymer dielectric material for electrical is completed.In one embodiment, the conductive part and remaining conductive part at least partly define the conductive coil of the component.

Description

The manufacture of multi-layer circuit assembly
Technical field
The present invention in more detail relates to the batch micro operations of circuit unit about the method for manufacture circuit unit (bulk-fabrication) wafer-level method seems multi-layer inductor or multi-layer transformer.
Background technique
In recent years, the feature of modern ultra high density integrated circuit steadily reduces size, makes great efforts to improve the whole of circuit Body speed, performance and functionality.Therefore, because various electronic building bricks, seem transistor, capacitor, diode etc., integrated Significant and lasting improvement in density, so semiconductor industry persistently undergoes huge growth.These improve mainly from holding Critical dimension (that is, minimum feature size) that is continuous and successfully making great efforts to reduce component, directly contributes process design personnel and has handle More and more components are integrated into the ability in the specific region of semiconductor chip.
The improvement of IC design has substantially been two-dimentional (2D)；Semiconductor core is directed primarily to i other words improving Circuit layout on piece surface.However, when device characteristic is persistently actively scaled, and more semiconductor subassemblies are placed When on the surface of one chip, circuit function need electrical interconnection requirement can significant increase, cause integrated circuit to be laid out Gradually become increasingly complex and dense pack.In addition, although the improvement of photoetching process two-dimensional circuit design integration density In have been achieved with apparent progress, the simple characteristic size that reduces can be promptly close to the limit for being only capable of realizing in two dimension at present System.
When the quantity of electronic device on a single chip increases sharply, three-dimensional (3D) integrated circuit layout, seems storehouse Formula chip design, be just considered for certain semiconductor devices or circuit, partially for overcome this feature size and with two-dimentional cloth The relevant density limitation of office.In three-dimensionally integrated design, the semiconductor chip of two or more can be combined together, and at this It will form electrical connection between a little chips.
Circuit unit seems capacitor, inductor, transformer etc., is widely used on various electronic circuits.In general, Inductor or capacitor are discrete devices, manufacture respectively via the motherboard for being coupled to such as electronic circuit and are integrated into electricity In sub-circuit.The existing design of this circuit unit may be not suitable for being easily integrated into them in three-dimensional circuit layout.
Summary of the invention
The shortcomings that method that circuit unit is formed on the substrate is provided through the invention, on the one hand overcomes the prior art, and Additional advantage is provided.Forming method of the present invention includes: that the circuit unit is formed in at least one layer of the substrate at least One conductive part；There is provided uncured polymer dielectric material for electrical at least partly around and cover the circuit unit this at least one A conductive part；The partially cured polymer dielectric material for electrical is to obtain the cured polymer dielectric material for electrical in part；It is solid to polish the part The polymer dielectric material for electrical of change makes it down to the height of at least one conductive part of the circuit unit；And form the circuit group Remaining conductive part of at least one of part, and be in electrical contact at least one conductive part of the circuit unit.
The technology of other features and advantage through the invention is realized.The other embodiment of the present invention is detailed herein with aspect State and be considered as a part of the claimed invention.
Detailed description of the invention
One or more aspects of the invention are highlighted and bright as an example in the claim of this specification conclusion It is really claimed.From being detailed below in conjunction with attached drawing, aforementioned and other purposes of the invention, feature and advantage are obvious.
Figure 1A one or more aspects according to the present invention show the implementation of the multi-layer circuit assembly formed by manufacturing process Example,；
Figure 1B one or more aspects according to the present invention show cuing open along the multi-layer circuit assembly of line 1B-1B in Figure 1A Face front view；
Fig. 1 C one or more aspects according to the present invention show cuing open along the multi-layer circuit assembly of line 1C-1C in Figure 1B Face top view；
Fig. 2A to Fig. 2 W one or more aspects according to the present invention show the wafer scale manufacture work of multiple multi-layer circuit assemblies The embodiment of skill；And
Fig. 3 one or more aspects according to the present invention, display can be used for the batch micro operations of the multi-layer circuit assembly of wafer scale General introduction.
Specific embodiment
Aspect of the invention and certain feature, advantages and wherein details, with reference to the accompanying drawings shown in non-limiting embodiment More sufficiently it is explained as follows.The description of known material, manufacture tool, process technique etc., is omitted so as not to understand optionally mould Paste details of the invention.It is to be understood, however, that the detailed description and the specific example, although showing implementation of the invention Example, but be only illustrated by way of example, rather than in a manner of limiting.Make in the spirit and scope of basic concepts of the invention Various replacements, modification, addition and/or configuration, will be apparent for those skilled in the art scholar.It is also noted that It is referenced attached drawing, is to be not drawn to scale in order to facilitate understanding, wherein the used identical ginseng in different attached drawings Examine the same or similar component of digital representation.
Hereinafter the present invention is the batch process of wafer scale, seems inductance electricity for manufacturing a large amount of discrete circuit components Road component, including inductor or transformer.It should be noted that " wafer scale (wafer-level) " used herein refers to multiple circuits Component seems the upper surface of other wafers across semiconductor crystal wafer or for manufacturing integrated circuit across the manufacture of substrate, or Person, wafer scale can refer to for example, during the manufacture of the solar battery array of solar energy industry used panel.The present invention The other application of manufacturing process be obvious for those skilled in the art scholar.It should also be noted that desired Component formative factor can be able to satisfy, seem for surface installation compatibility JEDEC square surface without pin (QFN) floor space (footprint), it is encapsulated in favor of integrating the circuit unit chip to any various two and three dimensions.
One embodiment of Figure 1A to Fig. 1 C display circuit component, be typically expressed as 100, makes according to the method for the present invention It makes.
A to Fig. 1 C, circuit unit 100 include (or disposed over) substrate 101 referring to Fig.1 jointly, seem semiconductor lining Bottom or other wafer substrates, and including, in the embodiment illustrated, lower conductive part 110, conductive hole portion 120 and upper conduction Portion 130 contacts and is electrically connected to form the multilayered structure 102 being arranged on substrate 101 as shown in the figure.Dielectric material seems polymerization Object dielectric medium 105, around the lower conductive part 110 of circuit unit 100, conductive hole portion 120 and upper conductive part 130.Shown Construction in, circuit unit 100 shows the embodiment of transformer, and thin magnetic material layer 115 is arranged on part by circuit In the region that the conductive hole portion 120 of component 100 defines.
Note that two coils are limited in multilayered structure 102, magnetic material layer 115 in the Transformer structure shown It at least partly resides in multilayered structure 102.In particular, shown lower conductive part 110 is fixed including multiple first parallel conductors To in first direction, and upper conductive part 130 includes that multiple second parallel conductors are oriented to second direction, is from the first direction Offset.Conductive contact 111,131 was formed (for example) with upper 130 same time of conductive part, and electrical connection (in example of schema) is arrived should The different conductive holes 120 of the near opposing ends of structure.These conductive holes carry out electricity from the respective different conductor of lower conductive part 110 Contact.
As a specific example, structure 101 can have about 500 to 600 microns of thickness, and multilayered structure 102 can With thickness, for example, about 70 microns, wherein lower conductive part 110 is about 20 microns of thickness, conductive hole portion 120 is about 30 microns Thickness, and upper conductive part 130 is about 20 microns of thickness.In one case, magnetic material layer 115 is about 2 microns of thickness.Pay attention to this A little thickness numbers are only for example.Furthermore, it is noted that in one embodiment, substrate 101 can be semiconductor substrate, seem silicon substrate or It is siliceous substrate, and the conductive part of circuit unit 100 can be made of metal or metal alloy, such as copper, can uses and appoint What suitable technique, such as be electroplated, to be deposited.
Pay attention to the circuit unit 100 of Figure 1A to Fig. 1 C shown in this article only for example, and other circuit units, especially It is that other inductive circuit components seem other inductors or transformer device, can be made of method disclosed herein. In one embodiment, single coil or multi-coil inductive circuit component can be formed in multilayered structure, seem in Figure 1A to Fig. 1 C Shown in embodiment.
By being explained further, Fig. 2A to Fig. 2 W shows the embodiment of a circuit unit manufacturing process, according to the present invention One or more aspects.Pay attention to being the end elevation view for showing the circuit unit manufactured in these figures, in comparison diagram 1B The example shown shows that cross-section front view is rotated by 90 °.
It with reference to Fig. 2A, shows that a structure includes substrate 101, deposits one layer thin dielectric materials layer 200 thereon and cover.Lining Bottom 101 can be any material appropriate, and circuit unit thereon can be formed as described herein.Pay attention to multiple actives and/or Passively circuit unit seems transistor, capacitor, resistor, inductor etc., can be formed in 101 top of substrate or collection At in substrate 101, in this case, substrate 101 may include the device layers of integrated circuit.Depending on whole design plan Slightly, it seems bulk Silicon Wafer that substrate 101, which can be semiconductor crystal wafer, wherein in other embodiments, substrate 101 may include Or is formed as single silicon metal, polysilicon, amorphous silicon, SON (silicon-on-nothing), covers silicon (SOI) on insulator Or SRI (silicon-on-replacement-insulator) structure or the like, as those skilled in the art scholar understands. The substrate may include other suitable just level semiconductors, seem, for example, germanium (Ge) crystal or compound semiconductor seem carbonization Silicon (SiC), GaAs (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb) or A combination thereof；Or alloy semiconductor includes gallium arsenide phosphide (GaAsP), arsenic indium aluminium (AlInAs), arsenic indium gallium (GaInAs), phosphorus Indium gallium (GaInP) or phosphorus arsenic indium gallium (GaInAsP) or combinations thereof.In other embodiments, substrate 101 may include it Its material is made from it, and seems glass or ceramic material, this depends on the required structure manufactured.In a specific embodiment In, substrate 101 can have about 500 to 700 microns of thickness.
Thin dielectric materials layer 200 can use any suitable conventional deposition processes, such as chemical gas by being vapor-deposited Mutually deposition (CVD), physical vapour deposition (PVD) (PVD), atomic layer deposition (ALD), or formed by liquid deposition, use spin-on deposition Technique.In one example, dielectric materials layer 200 may include, for example, silica (SiO2), silicon nitride (SiN or Si3N4) etc. Deng, or be made from it.As a specific example, dielectric materials layer can have about 1 micron of thickness, and be provided at least portion Dividing should be from multi-layer circuit assembly made of substrate 101 with electric isolution.
In Fig. 2 B, electroplating seed layer 201 has been used, such as physical vapour deposition (PVD) (PVD) technique, and deposition is on this structure.? In one example, electroplating seed layer 201 may include titanium or titanium tungsten (TiW) pasting material/layer and copper seed crystal material/layer, in favor of The current transmission of electroplating technology in subsequent manufacturing process.By way of example, electroplating seed layer 201 can have about 1 to 2 The thickness of micron.
As shown in FIG. 2 C, patterned photolithographic mask layer 203 is formed with one or more openings 204 wherein, in it The lower conductive part of the circuit unit in portion will be plated.Patterned photolithographic mask layer 203 can be or including one layer of photosensitive material Expect, seems, such as photoresist.The thickness of the material can change, this depends on application, and in one embodiment, pattern The thickness for changing photolithographic mask layer 203 is selected to the desired height of the lower conductive part greater than the circuit unit, to be exposed to out It is formed on electroplating seed layer 201 in mouth 204 with plating.For example, if the desired height for being formed by lower conductive part is about 20 micro- Rice, then the thickness of patterned photolithographic mask layer 203 is about 25 to 30 microns.The photoresist can be to be spin-coated on the structure On, and patterned with traditional lithographic patterning and etch process to remove the photoresist portion in any desired pattern Point, in favor of forming the lower conductive part of the circuit unit.
As about Figure 1A to Fig. 1 C, which may include multiple parallel electrically conductive channels.Therefore, patterning photoresist is covered Mold layer 203 can be with multiple openings extended in parallel or channel (the required part out of the ordinary for exposing plating underlayer seed layer 201) It is patterned.
As shown in Figure 2 D, lower conductive part 110 is in the opening against corrosion or channel defined by patterning photolithographic mask layer 203 It is electroplated.By way of example, lower conductive part 110 can be electro-coppering and/or copper alloy, and if desired, can It is exposed to heat treatment process, after its formation in favor of the grain growth and stabilization of copper film feature.Notice that the electroplating technology is being formed The electro-coppering of lower conductive part 110 or copper alloy be arranged in patterning photolithographic mask layer 203 upper surface below in the case where and Stop.Therefore, as noted, the thickness for patterning photolithographic mask layer 203 is in one embodiment according to lower conductive part 110 required thickness selects.As an example, the thickness of lower conductive part 110 is about 20 microns, and lower conductive part respectively may be used To be formed with multiple parallel electrically conductive channels, for example, in favor of forming circuit unit, as shown in Figure 1A to Fig. 1 C.
Wet type or dry type resistant to stripping technique leave the knot for being shown in Fig. 2 E for removing the patterning photolithographic mask layer Structure leaves the circuit unit being arranged on substrate 101 after carrying out seed layer etching to remove electroplating seed layer 201 Lower conductive part 110 or conducting channel, as shown in Figure 2 F.Notice that seed layer removal can be wet etch process, to remove copper crystalline substance Kind layer, and used depending on whether titanium (Ti) or titanium tungsten (TiW) have, and wet type or dry-etching adhesion layer Fig. 2 G are shown Structure in Fig. 2 F is providing dielectric material, such as polymer dielectric material for electrical 105, at least partially around and cover the circuit The case where after the lower conductive part 110 of component.Notice that polymer dielectric material for electrical used herein can be any Polymeric dielectric Matter seems, for example, polyimide resin, epoxy resin, polyacrylate resin, phenolic resin, polyamide, PBO or benzene And cyclobutane (BCB).As a specific example, polymer dielectric material for electrical 105 can be to be mentioned by the Hitachi, Ltd of Tokyo The CA-60001B polymer dielectric material for electrical of confession.The structure coating polymer dielectric material for electrical 105, then use, for example, low temperature moves back Fire carrys out soft baking, with the partially cured or partially hardened polymer dielectric material for electrical.As a specific examples, this soft Roaster Skill may relate to for the structure with polymer dielectric material for electrical to be exposed to about 100 DEG C to 110 DEG C of temperature and continue 3 minutes.? This stage, the upper surface of polymer dielectric material for electrical 105 can be non-planar, it may for example comprise the microwave (slight across the surface waves).The thickness of the polymer dielectric material for electrical is thicker, it is sufficient to cover lower conductive part 110.
Referring to Fig. 2 H, polishing process seems CMP process, the Polymeric dielectric for flattened section hardening Material 105.The flatening process can also planarize the upper surface of lower conductive part 110.For example, in one embodiment, the polishing The upper surface of the copper conductor of the lower conductive part can be planarized.In one embodiment, the chemically mechanical polishing of the structure can be with The structure is polished with standard copper slurry.After polishing, carry out at the last solidification or heat of the polymer dielectric material for electrical Reason, to harden the material for downstream process.As a specific example, which may relate to have The constant temperature for thering is the structure of the polymer material of the partially hardened to be exposed to about 375 DEG C 4 hours.If necessary from the copper surface Removing any pumping residue can be cleaned with plasma-based.Pay attention to above-mentioned soft baking and last solidification temperature and the duration is only For example, and the various change of these examples be it is possible, without departing from the scope of the present invention.
As shown in figure 2i, side on this structure can be set in dielectric materials layer 210, and magnetic material layer 115 sputters at Jie 210 top of material layer.By way of example, standard deposition process can be used for deposition of dielectric materials layer 210 to required thickness Degree, for example, about 1 micron (in an example) and then secondary, by way of example, magnetic material layer 115 can be splashed to about 2 microns of thickness.In one embodiment, dielectric materials layer 210 can be silica (SiOx) or silicon nitride (SiN) material Layer, and magnetic material layer 115 is such as nickel-base material, seems NiFe, CoNiFeB, CoNbZr.Alternatively, according to used spy Determine magnetic material, which can be formed with CoTaZr, and be sunk with physical vapour deposition (PVD) (PVD) or electroless-plating Product.Then, patterned photolithographic mask 211 is built using traditional anti-deposit with patterning techniques.Patterned photolithographic mask 211 groups of structures and it is located in required place, to retain magnetic material layer 115, including the obtained circuit unit produced.
As shown in figure 2k, magnetic material layer 115 is etched with dielectric materials layer 210 in the outside of photolithographic mask 211.One In a embodiment, this can be realized via the wet etching magnetic material layer 115 and dielectric materials layer 210 of timing.After etching, Patterning photolithographic mask 211 is removed via for example traditional wet type or dry type resistant to stripping technique, leaves the structure in Fig. 2 L.
With reference to Fig. 2 M, electroplating seed layer 220 is deposited on the superstructure.The seed layer is using such as physical vapour deposition (PVD) (PVD) technique deposits, and may include titanium or titanium tungsten pasting material/layer and copper seed crystal material/layer, in galvanizer Current transmission in skill.As a part of this technique, pay attention to magnetic material layer 115 side wall covering be it is unnecessary, because For the conductive hole portion being plated can be deviateed magnetic material layer 115 in the circuit unit.
As shown in figure 2n, required position of the patterning photolithographic mask layer 221 above the lower conductive part 110 of the circuit unit In be formed with via openings 222, in favor of forming the conductive hole portion with the circuit unit of lower conductive part electrical contact.It is available Above-mentioned anti-coating and Patternized technique, one thickness erosion resistant of spin coating on this structure, are then connected with required via openings Feature is patterned.The thickness selection for paying attention to patterning photolithographic mask layer 221 is according to the conductive hole in via openings 222 The desired height being plated, i.e., in one embodiment, the thickness of patterning photolithographic mask layer 221, which is greater than, is formed in via openings The desired height of the conductive hole in 222.
As shown in Figure 2 O, using electroplating technology in patterning photolithographic mask layer 221 via openings in conductive hole is provided 120.In one embodiment, conductive hole portion 120 is formed as being plated to the copper post of desired height for manufactured specific electricity The group structure of road component.It notes again that in the operation stage in Fig. 2 O, the height of conductive hole 120 can be covered lower than patterning photoresist The upper surface of mold layer 221.
It is formed after conductive hole portion 120, which strips via wet type or dry type are anti-etching, to obtain Fig. 2 P In structure, after this, seed layer 220 can be etched, as described above.The etching selection for paying attention to the seed layer is tool compatibility , i other words, the magnetic material layer 115 exposed will not be damaged.Obtained structure is as shown in fig. 2q.
As shown in Fig. 2 R, another uncured polymer dielectric material for electrical layer can be just set on this structure, hereon referred to as on Portion's polymer dielectric material for electrical layer 105 ', to surround and at least partly to cover, for example, extending from the lower conductive part 110 of the structure Conductive hole portion 120.In one embodiment, which is and material used by lower conductive part 110 It is identical, the top polymer dielectric material for electrical be carried out via above-mentioned soft baking or low temperature annealing process it is partially cured, then It is processed by shot blasting, for example, via CMP process, to planarize the partially cured top polymer dielectric material for electrical 105 ' upper surface.The polishing treatment also exposes the upper surface of conductive hole portion 120, and if necessary, also can be simultaneously Planarize the upper surface of the conductive hole.
After polishing, final curing or the heat treatment of the polymer dielectric material for electrical can be carried out, to harden the material To be further processed.In Fig. 2 S, the planarized upper surface of the structure forms the upper conductive part of the circuit unit manufactured Substrate.By repeating the process of Fig. 2A to Fig. 2 F, upper conductive part 130 can be formed as shown in Fig. 2 T.Upper conductive part 130 can be similarly Including individual conductive channel, it is composed and is positioned to be electrically connected and define the circuit with the lower conductive part and the conduction hole portion One or more coils of component.One embodiment of the structure is shown in the example in above-mentioned Figure 1A to Fig. 1 C.In cuing open for Fig. 2 T In the front view of face, upper conductive part 130 also extends outwardly to limit conductive contact, needed for the electrical connection of specific coil group structure Conductive hole 120, seem the transformer group structure being shown in Figure 1A to Fig. 1 C.It in further coating and patterns, such as identical Polymer dielectric material for electrical 105, and after the final solidification of patterned polymer dielectric material on this structure, bonding pad Or engagement pad 230 maintains exposure, as shown in Fig. 2 U.In one embodiment, standard light processing can be used for defining the bonding pad or Engagement pad fully wraps up resulting inductor or transformer coil with the polymer dielectric material for electrical shown in Fig. 2 U.
As shown in Fig. 2 V, the substrate or wafer can be cut, and generated required circuit unit 100 ' and are used as discrete crystal grain.Mark Quasi- blade cutting can be used in this processing stage.According to the crystallite dimension, which can be first cut into, for example, four points One of chip handled.
Fig. 2 W shows the embodiment of a final encapsulation part structure, the Polymeric dielectric with unshowned covering protection Material.The certain coil group structure of upper current-carrying part 130 is only for example.In addition, being connected to the bonding pad connection 111,131 of coil also Only it is used as example.In the present embodiment, bonding pad connection 111 assumes that each self-conductance for being connected to the conductive hole portion of the circuit unit Electric hole (not shown).The floor space of this bonding pad can profile of the reference standards square surface without pin (QFN), seem four or six Needle.If it is with six needles, center pad 140 can be used for the additional machinery integrality of surface installation, i other words, in such design It is likely to be and is not electrically connected to center pad 140.
Those skilled in the art scholar should be noted that the present invention is to manufacture the technique of multi-layer circuit assembly, seem to be manufactured in lining Multi-layer inductor or transformer above bottom.The batch processing procedure of wafer scale can be used for building a large amount of similar circuit units simultaneously. With reference to Fig. 3, manufacturing process 300 includes, for example: at least one conductive part that the circuit unit is formed on substrate 310；It provides Uncured polymer dielectric material for electrical at least partly around and cover at least one conductive part of multi-layer circuit assembly 320； Solidify the polymer dielectric material for electrical at least one conductive part upper section of multi-layer circuit assembly, to obtain partially hardened Polymer dielectric material for electrical 330；Polish the partially hardened polymer dielectric material for electrical make its down to multi-layer circuit assembly 340 this extremely The height of a few conductive part；And the solidification of the polymer dielectric material for electrical of the partially hardened is completed, and extremely in circuit unit 350 At least one other conductive part and electrical contact of the circuit unit are formed on a few conductive part.
In one embodiment, after with the polishing treatment, which includes that the polymer dielectric material for electrical completes solidification, with Obtain the polymer dielectric material for electrical of hardening.The hardening dielectric material is conductive at least partly around at least one of the circuit unit Portion, and there is the upper surface coplanar with the upper surface of at least one conductive part of the circuit unit.The technique can be wrapped further One layer of dielectric material of deposition is included above the polymer dielectric material for electrical of the hardening, and at least one for forming the circuit unit Before other conductive parts, provides above the dielectric material and at least one conductive part of the circuit unit and pattern magnetic Property material layer.This technique is particularly advantageous, and wherein the circuit unit is inductive circuit component, including, for example, inductor or Transformer.
In one embodiment, which includes the lower conductive part of the circuit unit, and the polishing is into one Step planarizes the upper surface of the lower conductive part.At least one other conductive part of the circuit unit may include leading for the circuit unit Electric hole portion, lower conductive part is practical contacts with this.In one embodiment, the conductive hole portion for forming the circuit unit may include (at least partly) and in individual mask vias opening on the lower conductive part of the circuit unit selectively It is electroplated and forms the conduction hole portion.
In a further embodiment, after with the conductive hole portion of the circuit unit is formed, another layer is uncured poly- Closing object dielectric material can be used at least partly around and covers the conductive hole portion of the circuit unit.Then, another layer is not solid The polymer dielectric material for electrical of change can be obtained the top polymer dielectric material for electrical of partially hardened by partially cured.The technique can be into one Step includes polishing the top polymer dielectric material for electrical of the partially hardened to make it down to the height of the conductive hole portion of the circuit unit, In the partially hardened top polymer dielectric material for electrical polishing may include planarize the top polymer dielectric material for electrical, and expose The upper surface of the conductive hole portion of the circuit unit, in favor of forming the circuit unit.By way of example, the circuit unit Upper conductive part may be provided on the conduction hole portion and electrical contact.In one embodiment, the lower conduction of the circuit unit Portion includes the lower part conductive coil of the circuit unit, and the upper conductive part of the circuit unit includes the top conduction of the circuit unit Coil, and the lower part conductive coil of the circuit unit, conductive hole portion and top conductive coil be at least partially formed it is one or more A coil.In one embodiment, magnetic material layer may be provided above the lower part conductive coil, and the coil may extend away and enclose Around the magnetic material layer.
In one embodiment, which may include the chemically mechanical polishing of the polymer dielectric material for electrical of the partially hardened, To planarize its upper surface, and planarize the exposed upper surface of at least one conductive part of the circuit unit.It is partially cured to be somebody's turn to do Uncured polymer dielectric material for electrical may include soft baking or the low-temperature annealing uncured polymer dielectric material for electrical, to be somebody's turn to do The polymer dielectric material for electrical of partially hardened.Advantageously, forming the circuit unit may include being formed with required profile, it seem four The circuit unit of square plane non-connection pin (QFN) profile.
Those skilled in the art scholar should be noted that provided in this article is for manufacturing multiple discrete circuit components or crystal grain Special wafer scale solution.Advantageously, being allowed using polymer dielectric material for electrical and polymer polishing process relatively thick The full planarization of film, and the succeeding layer of the circuit unit is successfully built, and meet defined size requirement.According to entirety The demand of circuit unit, seems the inductance requirement of inductor or transformer, and technique proposed by the present invention is conducive to height expandability Solution.Magnetic material layer or band can be incorporated into that in the circuit unit, to improve one or more lines of the circuit unit The inductance of circle.Wafer-level process allows the batch micro operations of extensive discrete circuit components to be converted into lower manufacturing cost.JEDEC Standard floor space can be realized, for example, surface installation compatibility, two dimension or three-dimensional collection in favor of higher levels of circuit unit At arrive more advanced encapsulation.
The term as used herein is only for the purpose of describing particular embodiments, to be not intended to the limitation present invention.Such as this paper institute Singular " one ", "one" and "the" are also intended to include plural form, unless in addition explicitly pointing out within a context. It will be further appreciated that term " includes " (and any type of include seem " comprising " and " comprising "), " having " (with And it is any type of have, seem " having " and " having "), " comprising " (and it is any type of include seem " comprising " and " comprising ") and "comprising" (and any type of include seem "comprising" and "comprising") be open connection verb.As a result, One method or apparatus " comprising ", " having ", one or more steps of " include " or " contain " or component have those one or more Step or component, but it is not limited to that only there is those one or more steps or component.Similarly, the component of the step of method or device " comprising ", " having ", one or more features of " include " or " contain " have one or more features, but be not limited to only have those one Or multiple features.In addition, organize the device of structure in some way or structure is at least to organize structure in this way, but it can also be with unlisted Mode carry out a group structure.
All method or steps of equivalent in corresponding structure, material, behavior and following claims add function Energy component, if any, be intended to include any structure, material or movement to be to execute to combine other that the function of component is required to make For clearly claim.Description of the invention is presented for illustrating and describing, but is not intended to exhaustion or limits this hair Bright disclosed form.In many modifications and variation for not departing from scope and spirit of the present invention for the technology of those this fields Personage will be apparent.Selection and description of the embodiments are for the one or more aspects to the present invention or practical application Principle makes best interpretations, and makes those skilled in the art scholar it will be appreciated that one or more aspects of the invention have various repair The various embodiments changed are to be suitble to desired special-purpose.

Claims (20)

1. a kind of method for manufacturing circuit unit, comprising:
The circuit unit is formed in substrate, comprising:
At least one conductive part of the circuit unit is formed in at least one layer of the substrate；
Uncured polymer dielectric material for electrical is provided, surround and cover at least partially the circuit unit this at least one lead Electric portion；
Partially cured polymer dielectric material for electrical, to obtain the polymer dielectric material for electrical of partially hardened；
The polymer dielectric material for electrical for polishing the partially hardened makes it as low as the height of at least one conductive part of the circuit unit；
Formed at least one conductive part of the circuit unit at least one remaining conductive part of the circuit unit and with It is in electrical contact, at least one remaining conductive part of the circuit unit includes the conduction of the circuit unit contacted with lower conductive part Hole portion,
After the conduction hole portion for forming the circuit unit, the other one layer uncured polymer dielectric material for electrical is provided, At least partially surrounding and cover the conduction hole portion of the circuit unit, partially hardened is above the conduction hole portion of the circuit unit Other one layer of uncured polymer dielectric material for electrical, to obtain the top polymer dielectric material for electrical of partially hardened；And
Magnetic material layer is provided on the lower conductive part of the circuit unit, wherein the magnetic material layer is at least partly stayed It stays in the region as defined in the conduction hole portion of the circuit unit.
2. the method as described in claim 1 further includes completing the solidification of the polymer dielectric material for electrical after the polishing to obtain The polymer dielectric material for electrical that must be hardened, the polymer dielectric material for electrical of the hardening at least partly around the circuit unit this at least One conductive part, and there is the upper surface coplanar with the upper surface of at least one conductive part of the circuit unit.
3. method according to claim 2 further includes one dielectric material of polymer dielectric material for electrical disposed thereon in the hardening Layer, and before at least one remaining conductive part for forming the circuit unit, above the dielectric materials layer and the circuit group Simultaneously patterned magnetic material layer is provided at least one conductive part of part.
4. the method for claim 1, wherein at least one conductive part includes the lower conductive part of the circuit unit, and Wherein the polishing further planarizes the upper surface of the lower conductive part.
5. method as claimed in claim 4, wherein at least one remaining conductive part of the circuit unit includes leading under this The conductive hole portion of the circuit unit of electric portion's contact.
6. method as claimed in claim 5, wherein the circuit unit includes wherein the one of multilayer inductor or multi-layer transformer It is a.
7. method as claimed in claim 5, wherein formed the circuit unit the conduction hole portion include at least partially through It is electroplated on the lower conductive part of the circuit unit to form the conduction hole portion.
8. method as claimed in claim 5, further include polish the partially hardened top polymer dielectric material for electrical make its as low as The polishing of the height of the conduction hole portion of the circuit unit, the top polymer dielectric material for electrical of the partially hardened planarizes the portion Divide the top polymer dielectric material for electrical of hardening, and exposes the upper surface of the conduction hole portion of the circuit unit, it should in favor of being formed Circuit unit.
9. method according to claim 8 further includes providing the circuit unit on the conduction hole portion of the circuit unit Upper conductive part and electrical contact.
10. method as claimed in claim 9, wherein the lower conductive part of the circuit unit includes the lower part of the circuit unit Conductive coil part, and the circuit unit this on conductive part include the circuit unit top conductive coil part, and wherein The lower part conductive coil part, the conduction hole portion and top conductive coil part of the circuit unit are at least partially formed At least one coil extends around the magnetic material layer on the lower part conductive coil part of the circuit unit.
11. the method for claim 1, wherein at least one conductive part includes the lower conductive part of the circuit unit, and Forming the circuit unit in the substrate includes:
Square deposition of dielectric materials layer over the substrate；
Seed layer deposition is provided above the dielectric materials layer in favor of plating；
It is coated with photoresist above the seed layer and patterns the photoresist to define multiple channels wherein；
It is electroplated in multiple channel, to define the lower conductive coil part of the circuit unit；And
It removes the photoresist and etches the seed layer.
12. the method for claim 1, wherein at least one conductive part includes lower conductive part, and the circuit unit Conductive hole portion is arranged above the lower conductive part and electrical contact, and the wherein uncured polymer dielectric material for electrical at least portion Surround and cover the conduction hole portion of the circuit unit with dividing, and wherein the polishing planarizes the Polymeric dielectric of the partially hardened Material, and the upper surface of the conduction hole portion of the exposure circuit unit, in favor of formed the circuit unit this at least one its Remaining conductive part is simultaneously in electrical contact with it.
13. method as claimed in claim 12, wherein at least one remaining conductive part includes the upper conduction of the circuit unit Simultaneously electrical contact is arranged in above the conduction hole portion of the circuit unit in portion.
14. method as claimed in claim 13, wherein the circuit unit includes one of them of inductor or transformer, and The lower conductive part, the conduction hole portion and conductive part defines at least one coil of the circuit unit together on this.
15. method as claimed in claim 14 further includes providing at least one magnetic material layer, is at least partially disposed on In the region as defined at least one coil of the circuit unit.
16. the method for claim 1, wherein the polishing includes polymer Jie for chemically-mechanicapolish polishing the partially hardened Electric material is to planarize its upper surface, and planarizes the exposed upper surface of at least one conductive part of the circuit unit.
17. it includes the uncured polymer dielectric material for electrical of annealing that the method for claim 1, wherein this is partially cured To obtain the polymer dielectric material for electrical of the partially hardened, and wherein the polishing includes chemically-mechanicapolish polishing the polymerization of the partially hardened Object dielectric material.
18. the method for claim 1, wherein the substrate includes semiconductor crystal wafer.
19. the method for claim 1, wherein the circuit unit is wherein the one of multi-layer inductor or multi-layer transformer It is a.
20. method as claimed in claim 19, wherein forming circuit unit includes forming square surface leadless packages external form Circuit unit, and cut the substrate to separate the circuit unit.
CN201510393754.2A 2014-07-09 2015-07-07 The manufacture of multi-layer circuit assembly Expired - Fee Related CN105261551B (en)

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