CN105021865B - A kind of compensable voltage measurement method - Google Patents
A kind of compensable voltage measurement method Download PDFInfo
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- CN105021865B CN105021865B CN201510304278.2A CN201510304278A CN105021865B CN 105021865 B CN105021865 B CN 105021865B CN 201510304278 A CN201510304278 A CN 201510304278A CN 105021865 B CN105021865 B CN 105021865B
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Abstract
The invention discloses a kind of compensable voltage measurement method, the current value that this method is superimposed upon ground wire by measuring twice measurable is measured voltage twice, test equipment also obtainable voltage tester value twice, thus the contact resistance of ground wire is obtained, the magnitude of voltage of chip under test output is calculated afterwards, that is, is carried out the magnitude of voltage after voltage compensation, be the process eliminate the harmful effect caused by loose contact causes contact resistance difference, voltage can be accurately measured, improves the precision of voltage measurement.
Description
Technical field
The invention belongs to the technical field of chip, more particularly to chip voltage detection method.
Background technology
Digital-analog mix-mode chip typically has internal reference voltage, in order to ensure the absolute precision of reference voltage and uniformity,
Chip dispatch from the factory Shi Douhui volume production test in carry out reference voltage calibration.Although chip reference voltage itself can be calibrated to precision
It is very high, but measuring accuracy can be influenceed because chip contacts situation with tester table, so precision voltage reference calibration is limited
In contact situation of the chip with tester table.Contact situation is embodied in contact resistance difference, so as to influence voltage calibration precision.
Patent application 201210312733.X discloses a kind of output voltage of internal power source of chip measuring system and method.Should
Output voltage of internal power source of chip measuring system includes：Test machine and probe card；Wherein described test machine passes through the probe
Card is connected to chip to be measured；Wherein, the test machine includes driving voltage applying unit and PMU；And its
In, the driving voltage applying unit is used for internally power supply power supply to ensure the accuracy of power supply supply；The power management
Unit applies driving current for described to the chip to be measured, to measure the internal electric source output voltage of the chip to be measured；
And wherein, the first passage of the test machine and second channel in the mutual short circuit of output end and are connected to the one of the probe card
Individual input port；Moreover, the input port of the probe card corresponds to a pin of the chip to be measured..
The content of the invention
To solve the above problems, it is an object of the invention to provide a kind of compensable voltage measurement method, this method carries
For a kind of compensable voltage measurement method, contact situation that can be different with measuring apparatus to chip under test carries out voltage compensation
Improve voltage measurement accuracy.
To achieve the above object, technical scheme is as follows.
A kind of compensable voltage measurement method, it is characterised in that this method is superimposed upon the electric current of ground wire by measuring twice
Be worth it is measurable measured voltage twice, test equipment can also obtain voltage tester value twice, thus obtain ground wire contact electricity
Resistance, the magnitude of voltage of chip under test output is calculated afterwards, that is, carries out the magnitude of voltage after voltage compensation, the process eliminate due to contact
It is bad to cause harmful effect caused by contact resistance difference, voltage can be accurately measured, improves the precision of voltage measurement.
Methods described, the reference voltage of first time test equipment measurement chip under test is VBC, and chip under test reality output
Reference voltage be VEF, due to contact resistance be present between the ground pin C of test equipment and the ground pin F ground wires of test equipment,
It can obtain following formula：
VBC=VEF+I1* (R0+R0X) ... (1)
During second of test, test equipment need to supply the power pins A ends power supply of chip under test, while volume in test equipment
The power pins of the common input and output pin I2 of outer increase chip under test driving current, then test equipment supply chip under test
Electric current with the power pins AD of chip under test is I1+I2；
Meanwhile test equipment need to pass through the common defeated of chip under test at the pin H ends to current excitation of test equipment
Enter output pin I ends and pour into electric current I2 to chip under test, then the ground pin C of test equipment and the ground pin F of test equipment electricity
Flow for I1+I2, the reference voltage of test equipment measurement chip under test is VBC2, and the reference voltage of chip under test reality output is
VEF, it can obtain following formula：
VBC2=VEF+ (I1+I2) * (R0+R0X) ... (2)
By formula (1), (2) can obtain
(R0+R0X)=(VBC2-VBC)/I2 ... (3)
VEF=VBC-I1* (VBC2-VBC)/I2 ... (4)
By the result tested twice, then formula (4) can accurately draw the reference voltage level of chip output, wherein I1*
(VBC2-VBC)/I2 is the magnitude of voltage that contact resistance compensation is returned.
The present invention obtains voltage tester value twice, thus obtains ground wire by the voltage measurement twice to chip under test
Contact resistance, voltage compensation is carried out afterwards, calculate the magnitude of voltage of chip under test output.It the process eliminate because loose contact is led
Harmful effect caused by causing contact resistance difference, can accurately measure voltage, improve the precision of voltage measurement.
Brief description of the drawings
Fig. 1 is the circuit diagram that the present invention is implemented.
Fig. 2 is the circuit diagram of another planted embodiment of the present invention.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
It is the power pins of chip under test with reference to figure 1 and Fig. 2, D, F is the ground pin of test equipment, and E is chip under test
Reference voltage output pin, I are the common input and output pin of chip under test；A is the power supply that test equipment supplies chip under test
Pin, C are the ground pin of test equipment, and B is the pin of test test measurement voltage, and H gives current excitation for test equipment
Pin.
Resistance when R0 is test equipment and good chip under test ground contact, R0X is for test equipment and chip under test
Increase resistance when linear contact lay is bad.
Resistance when R1 is test equipment and good chip under test internal reference voltage linear contact lay, R1X be test equipment and
Increase resistance during chip under test reference voltage line loose contact.
Resistance when R2 is test equipment and good chip under test power supply linear contact lay, R2X are test equipment and chip under test
Increase resistance during power line loose contact.
Resistance when R3 is test equipment and good chip under test I/O port contact, R3X is test equipment and chip under test IO
Increase resistance during mouth loose contact.
Because the impedance at BE both ends is very big, so electric current can be neglected.
For Fig. 1 (A), test equipment A ports power to chip under test D ends, and I1 is that the operating current of chip (can be by surveying
Examination device measuring obtains)；To Fig. 2 (A), test equipment H ends input high resistant input, then HI does not walk electric current.
The reference voltage of first time test equipment measurement chip under test is VBC, and the reference of chip under test reality output is electric
Press as VEF, due to contact resistance be present between CF ground wires, can obtain following formula：
VBC=VEF+I1* (R0+R0X) ... (1)
During second of test, for Fig. 1 (B), test equipment need to power at A ends, while extra increase I2 driving
Electric current, then AD electric current is I1+I2；For Fig. 2 (B), test equipment need to be given by the I ends of chip under test at H ends and is tested
Chip pours into electric current I2, then CF electric current is I1+I2, and the reference voltage of test equipment measurement chip under test is VBC2, and is tested
The reference voltage of chip reality output is VEF, can obtain following formula：
VBC2=VEF+ (I1+I2) * (R0+R0X) ... (2)
By formula (1), (2) can obtain
(R0+R0X)=(VBC2-VBC)/I2 ... (3)
VEF=VBC-I1* (VBC2-VBC)/I2 ... (4)
By the result tested twice, then formula (4) can accurately draw the reference voltage level of chip output, I1* (VBC2-
VBC)/I2 is the magnitude of voltage that contact resistance compensation is returned.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
All any modification, equivalent and improvement made within refreshing and principle etc., should be included in the scope of the protection.
Claims (1)
1. a kind of compensable voltage measurement method, it is characterised in that this method is superimposed upon the current value of ground wire by measuring twice
Measurable to be measured voltage twice, test equipment can also obtain voltage tester value twice, thus obtain the contact resistance of ground wire,
The magnitude of voltage of chip under test output is calculated afterwards；The reference voltage of first time test equipment measurement chip under test is VBC, and is tested
The reference voltage of chip reality output is VEF, due to existing between the ground pin C of test equipment and the ground pin F of chip under test
Contact resistance, it can obtain following formula：
VBC=VEF+I1* (R0+R0X) ... (1)
During second of test, test equipment need to supply the power pins A ends power supply of chip under test in test equipment, while additionally increase
Add the common input and output pin I2 of chip under test driving current, then the power pins and quilt of test equipment supply chip under test
The electric current for surveying the power pins AD of chip is I1+I2；
Meanwhile test equipment need to be defeated by the commonly input of chip under test at the pin H ends to current excitation of test equipment
Go out pin I ends and pour into electric current I2 to chip under test, then the ground pin F of the ground pin C of test equipment and chip under test electric current is
I1+I2, the reference voltage of test equipment measurement chip under test is VBC2, and the reference voltage of chip under test reality output is VEF,
It can obtain following formula：
VBC2=VEF+ (I1+I2) * (R0+R0X) ... (2)
By formula (1), (2) can obtain
(R0+R0X)=(VBC2-VBC)/I2 ... (3)
VEF=VBC-I1* (VBC2-VBC)/I2 ... (4)
By the result tested twice, then formula (4) can accurately draw the reference voltage level of chip output, wherein I1* (VBC2-
VBC)/I2 is the magnitude of voltage that contact resistance compensation is returned.
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| CN201510304278.2A CN105021865B (en) | 2015-06-04 | 2015-06-04 | A kind of compensable voltage measurement method |
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| CN201510304278.2A CN105021865B (en) | 2015-06-04 | 2015-06-04 | A kind of compensable voltage measurement method |
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| CN105021865A CN105021865A (en) | 2015-11-04 |
| CN105021865B true CN105021865B (en) | 2017-12-01 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108333411B (en) * | 2018-01-12 | 2020-06-16 | 上海华虹宏力半导体制造有限公司 | Circuit and method for reducing analog voltage measurement error |
| CN110265081B (en) * | 2019-06-26 | 2021-04-23 | 建荣半导体（深圳）有限公司 | Method and device for calibrating chip voltage, burner and storage medium |
| CN113514758B (en) * | 2021-09-15 | 2022-02-22 | 绅克半导体科技(苏州)有限公司 | Chip testing method, tester and storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1291724A (en) * | 1999-10-07 | 2001-04-18 | 广州擎天实业有限公司电工分公司 | Automatic sampling correction method for voltage of battery |
| CN1609621A (en) * | 2004-11-19 | 2005-04-27 | 天津市纳百山科贸发展有限公司 | Double-parameter measuring instrument |
| CN101713794A (en) * | 2009-10-23 | 2010-05-26 | 广州蓝奇电子实业有限公司 | Method for detecting poor contact of battery voltage testing terminals |
| CN104238619A (en) * | 2014-09-26 | 2014-12-24 | 深圳市芯海科技有限公司 | Temperature compensation circuit for reference voltage |
| CN104483537A (en) * | 2014-11-12 | 2015-04-01 | 深圳市芯海科技有限公司 | Low-voltage detection circuit with temperature compensation function |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120139495A1 (en) * | 2010-12-06 | 2012-06-07 | Coda Automative, Inc. | Electrochemical cell balancing circuits and methods |
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2015
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1291724A (en) * | 1999-10-07 | 2001-04-18 | 广州擎天实业有限公司电工分公司 | Automatic sampling correction method for voltage of battery |
| CN1609621A (en) * | 2004-11-19 | 2005-04-27 | 天津市纳百山科贸发展有限公司 | Double-parameter measuring instrument |
| CN101713794A (en) * | 2009-10-23 | 2010-05-26 | 广州蓝奇电子实业有限公司 | Method for detecting poor contact of battery voltage testing terminals |
| CN104238619A (en) * | 2014-09-26 | 2014-12-24 | 深圳市芯海科技有限公司 | Temperature compensation circuit for reference voltage |
| CN104483537A (en) * | 2014-11-12 | 2015-04-01 | 深圳市芯海科技有限公司 | Low-voltage detection circuit with temperature compensation function |
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Address after: 518067 Nanshan District, Shenzhen, Nanhai Avenue, garden city, No. 1079, building A, block, floor 9 Patentee after: Chipsea Technology (Shenzhen) Co., Ltd. Address before: 518067 Nanshan District, Shenzhen, Nanhai Avenue, garden city, No. 1079, building A, block, floor 9 Patentee before: Xinhai Science and Technology Co., Ltd., Shenzhen City |