CN108333411B - Circuit and method for reducing analog voltage measurement error - Google Patents
Circuit and method for reducing analog voltage measurement error Download PDFInfo
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- CN108333411B CN108333411B CN201810029278.XA CN201810029278A CN108333411B CN 108333411 B CN108333411 B CN 108333411B CN 201810029278 A CN201810029278 A CN 201810029278A CN 108333411 B CN108333411 B CN 108333411B
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R19/0084—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring voltage only
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Abstract
The invention discloses a circuit and a method for reducing measurement errors of analog voltage, wherein the circuit comprises a first impedance network, a second impedance network, a third impedance network, a fourth impedance network and a bare chip to be tested, and an Iload load current source which is equivalent to or has the same amplitude as the working current Icc of the bare chip to be tested is connected to a certain digital input pin IN of the bare chip to be tested.
Description
Technical Field
The present invention relates to the field of voltage measurement technologies, and in particular, to a circuit and a method for reducing analog voltage measurement errors.
Background
Generally, in the measurement of high precision analog voltage, the ground potential is ensured to be 0, and the accurate value can be measured.
At present, in analog voltage measurement, particularly in CP (Chip Probe, middle test) test, a pin card (a bare Chip test fixture with many capillary pins) is generally used for testing, because a Probe for electrical contact is thin, the diameter of a needle point is about 10-100um, the strength is limited, and the force of pricking on a pad cannot be too large, a contact resistance exists in the pricking, 0 potential of a Chip to the ground can be affected when power consumption is large, so that the measured voltage deviates from an actual voltage, and a capacitance or inductance effect exists in the Probe at high frequency.
Disclosure of Invention
In order to overcome the above-mentioned deficiencies of the prior art, the present invention provides a circuit and a method for reducing the measurement error of the analog voltage, so as to reduce the adverse effect caused by the contact resistance of the probe and ensure the accuracy of the measurement of the analog voltage.
To achieve the above and other objects, the present invention provides a circuit for reducing an analog voltage measurement error, including a first impedance network, a second impedance network, a third impedance network, a fourth impedance network, and a die under test, wherein an Iload load current source having a value equal to or a magnitude of an operating current Icc of the die under test is connected to a digital input pin IN of the die under test.
Further, the input pin of the bare chip to be tested is connected to the hot end of the Iload load current source through the second impedance network, and the cold end of the Iload load current source is connected with a power supply Vee.
Further, the Iload load current source is a controllable constant current source.
Further, an output pin OUT of the bare chip to be tested is connected to a Vbg node of the voltage to be tested through the first impedance network, a power supply voltage Vcc is connected to a positive power supply pin Vpos of the bare chip to be tested through the third impedance network, and a negative power supply pin Vneg of the bare chip to be tested is grounded through a fourth impedance network.
Further, inside the die to be tested, a cathode of the first ESD diode and a cathode of the third ESD diode are connected to a pad of the positive power supply pin Vpos of the die to be tested, an anode of the second ESD diode and an anode of the fourth ESD diode are connected to a pad of the negative power supply pin Vneg of the die to be tested, an anode of the first ESD diode and a cathode of the second ESD diode are connected to a pad of the output pin OUT of the die to be tested, and an anode of the third ESD diode and a cathode of the fourth ESD diode are connected to a pad of the input pin IN of the die to be tested.
Furthermore, the first impedance network, the second impedance network, the third impedance network and the fourth impedance network are all impedance networks formed by the probe of the pin card pricking on the bonding pad of the bare chip to be tested.
Furthermore, the first impedance network, the second impedance network, the third impedance network and the fourth impedance network are simplified into a first resistor, a second resistor, a third resistor and a fourth resistor, and are used for measuring the impedance formed by the probe of the pin card on the bonding pad of the bare chip to be tested.
Further, the equivalent resistance of the first impedance network, the second impedance network, the third impedance network and the fourth impedance network is 1-100 ohms.
In order to achieve the above object, the present invention further provides a method for reducing the measurement error of the analog voltage, comprising the following steps:
measuring and obtaining the working current Icc of a bare chip to be tested;
and step two, connecting an Iload load current source equivalent to the working current Icc in value or amplitude to a certain digital input pin of the bare chip to be tested.
Furthermore, the hot end of the Iload load current source is connected with the input pin of the bare chip to be tested through an impedance network, and the cold end of the Iload load current source is connected with the power supply Vee.
Compared with the prior art, the circuit and the method for reducing the analog voltage measurement error connect a load current source equivalent to or equal to the working current Icc of the bare chip to be measured on a certain digital input pin of the bare chip to be measured, so as to reduce the adverse effect caused by the contact resistance of the probe and ensure the accuracy of the analog voltage measurement.
Drawings
FIG. 1 is a circuit diagram of a circuit for reducing analog voltage measurement errors according to the present invention;
FIG. 2 is a flowchart illustrating steps of a method for reducing measurement errors of an analog voltage according to the present invention.
Detailed Description
Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.
FIG. 1 is a circuit diagram of a circuit for reducing the measurement error of analog voltage according to the present invention. As shown in fig. 1, a circuit for reducing an analog voltage measurement error according to the present invention includes a first impedance network 10, a second impedance network 20, a third impedance network 30, a fourth impedance network 40, a Die under test (Die)50, and an Iload load current source 60.
The first impedance network 10, the second impedance network 20, the third impedance network 30 and the fourth impedance network 40 are impedance networks formed by probe needles of a probe card being stuck on a pad of a Die (Die)50 to be tested, and are generally equivalent to RLC (resistance, inductance and capacitance) networks, because the test speed is not high in the invention, 4 impedance networks are simplified into a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4 for measuring the impedance formed by the probe needles of the probe card being stuck on the pad of the Die (Die)50 to be tested, the equivalent resistor is generally 1-100 ohms, and the typical value is 10 ohms; the bare chip (Die)50 to be tested is composed of a core circuit, a metal bonding pad and an ESD network, and generally comprises a digital input pin IN, an output pin OUT, a power supply positive terminal pin Vpos, a power supply negative terminal pin Vneg, ESD diodes D3-D4 connected to the digital input pin IN, and ESD diodes D1-D2 connected to the output pin OUT; the Iload load current source 60 is a controllable constant current source for generating a load current having a value equal to the operating current Icc of the Die under test (Die) 50.
The output probe of the voltage Vbg node to be tested is pricked on a bonding pad of an output pin OUT of a bare chip (Die)50 to be tested, the equivalent resistance is a first resistance R1, and the output pin OUT of the bare chip (Die)50 to be tested is connected to the voltage Vbg node to be tested through a first resistance R1 in principle; a load current probe connected with an Iload load current source 60 is pricked on a pad of a certain digital input pin IN of a Die (Die)50 to be tested, an equivalent resistor is a second resistor R2, the input pin IN of the Die (Die)50 to be tested is connected to the hot end of the Iload load current source 60 through a second resistor R2 IN principle, and the cold end of the Iload load current source 60 is connected with a power supply Vee; a power supply voltage Vcc node input probe is pricked on a pad of a power supply positive terminal pin Vpos of a Die (Die)50 to be tested, and an equivalent resistor is a third resistor R3, which seems to be the power supply voltage Vcc connected to the power supply positive terminal pin Vpos of the Die (Die)50 to be tested through a third resistor R3 in principle; the ground Gnd node input probe is pricked on a pad of a power supply negative terminal pin Vneg of the Die (Die)50 to be tested, the equivalent resistance is a fourth resistance R4, and the power supply negative terminal pin Vneg of the Die (Die)50 to be tested is connected to the ground Gnd through a fourth resistance R4 in principle; inside the Die (Die)50 to be tested, the cathode of the first ESD diode D1 and the cathode of the third ESD diode D3 are connected to the pad of the positive power supply pin Vpos of the Die (Die)50 to be tested, the anode of the second ESD diode D2 and the anode of the fourth ESD diode D4 are connected to the pad of the negative power supply pin Vneg of the Die (Die)50 to be tested, the anode of the first ESD diode D1 and the cathode of the second ESD diode D2 are connected to the pad of the output pin OUT of the Die (Die)50 to be tested, and the anode of the third ESD diode D3 and the cathode of the fourth ESD diode D4 are connected to the pad of the input pin IN of the Die (Die)50 to be tested.
During testing, firstly, the working current Icc of the Die (Die)50 to be tested is measured, then the current of the Iload load current source 60 is set to be equal to the Icc, and the pin card is connected to test the analog voltage of the output pin OUT.
Since an Iload load current source 60 having the same value or amplitude as the operating current Icc is connected to a certain digital input pin of the Die (Die)50 to be tested, the current Icc that originally needs to pass through the grounding probe is divided into two paths, one path enters the ground Gnd through the grounding probe (fourth equivalent resistor R4) and has the size of Ig, the other path enters the ground power supply Vee through the fourth ESD diode D4, the load current probe (second equivalent resistor R2) and the Iload load current source 60 and has the size of It, since the load current probe (second equivalent resistor R ic 2) is connected to the digital pin that consumes almost no current, the voltage of the output pin OUT to be tested is higher than the voltage of the ground Gnd, no current flows through the second ESD diode gd 2, the current Ig-It-i-D, and the voltage of the power supply vgg of the Die (Die)50 to be tested is 4, if the magnitude of the current of the Iload load current source 60 is sufficiently close to the operating current Icc of the Die (Die)50 to be tested, the current flowing through the ground Gnd node input probe will be sufficiently small, and the generated system error, namely Vg, will be sufficiently small, so that the adverse effect caused by the contact resistance of the probe is reduced.
The probe of the prior art pin card is directly pricked on the corresponding pad, so the working current Icc of the Die (Die)50 to be tested needs to flow back to the ground Gnd through the ground probe, and the current flowing through the ground probe (the fourth equivalent resistor R4) is Ig ═ Icc, so the voltage of the power supply negative terminal Vneg of the Die (Die)50 to be tested is Vg ═ Ig × R4, and the voltage of all nodes of the Die (Die)50 to be tested is Vg based on the voltage of the power supply negative terminal Vneg thereof, so the analog voltage of the output voltage pin to be tested is raised Vg correspondingly. For example, the power consumption of the chip is 10mA, and at this time, the resistance generated by the needle is 10Ohm, the voltage Vg of the actual power supply negative terminal Vneg of the Die (Die)50 to be tested is 0.1V — Ig × R4 — 10mA × 10 Ω, and if the voltage generated by bgr (bandgap reference) is 0.8V, the actually measured value is 0.8V +10mA — 10Ohm — 0.9V, and the measurement result is seriously deviated from the actual value.
FIG. 2 is a flowchart illustrating steps of a method for reducing measurement errors of an analog voltage according to the present invention. As shown in fig. 2, a method for reducing the measurement error of the analog voltage of the present invention includes the following steps:
in step 202, an Iload load current source with the same value or amplitude as the working current Icc is connected to a digital input pin of the Die (Die) to be tested.
In summary, the circuit and the method for reducing the analog voltage measurement error of the present invention connect a load current source with the same value or amplitude as the working current Icc of the die to be measured to a digital input pin of the die to be measured, so as to reduce the adverse effect caused by the contact resistance of the probe and ensure the accuracy of the analog voltage measurement.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (8)
1. A circuit for reducing analog voltage measurement errors comprises a first impedance network, a second impedance network, a third impedance network, a fourth impedance network and a bare chip to be tested, and is characterized in that:
a digital input pin IN of the bare chip to be tested is connected to the hot end of an Iload load current source through the second impedance network, an output pin OUT of the bare chip to be tested is connected to a Vbg node of voltage to be tested through the first impedance network, a power supply voltage Vcc is connected to a power supply positive terminal pin Vpos of the bare chip to be tested through the third impedance network, and a power supply negative terminal pin Vneg of the bare chip to be tested is grounded through a fourth impedance network;
an Iload load current source equivalent to the working current Icc of the bare chip to be tested IN value or amplitude is connected to a certain digital input pin IN of the bare chip to be tested, wherein IN the bare chip to be tested, a cathode of a first ESD diode and a cathode of a third ESD diode are connected to a bonding pad of a power supply positive pin Vpos of the bare chip to be tested, an anode of a second ESD diode and an anode of a fourth ESD diode are connected to a bonding pad of a power supply negative pin Vneg of the bare chip to be tested, an anode of the first ESD diode and a cathode of the second ESD diode are connected to a bonding pad of an output pin OUT of the bare chip to be tested, and an anode of the third ESD diode and a cathode of the fourth ESD diode are connected to a bonding pad of the digital input pin IN of the bare chip to be tested.
2. The circuit for reducing analog voltage measurement errors of claim 1, wherein: and the cold end of the Iload load current source is connected with a power supply Vee.
3. A circuit for reducing analog voltage measurement errors as defined in claim 2, wherein: the Iload load current source is a controllable constant current source.
4. A circuit for reducing analog voltage measurement errors as defined in claim 3, wherein: the first impedance network, the second impedance network, the third impedance network and the fourth impedance network are all impedance networks formed by the probe of the pin card pricked on the bonding pad of the bare chip to be tested.
5. The circuit for reducing analog voltage measurement errors of claim 4, wherein: the first impedance network, the second impedance network, the third impedance network and the fourth impedance network are simplified into a first resistor, a second resistor, a third resistor and a fourth resistor, and are used for measuring the impedance formed by the probe of the probe card pricked on the bonding pad of the bare chip to be tested.
6. The circuit for reducing analog voltage measurement errors of claim 5, wherein: the equivalent resistance of the first impedance network, the second impedance network, the third impedance network and the fourth impedance network is 1-100 ohms.
7. A method of reducing analog voltage measurement errors, comprising a circuit for reducing analog voltage measurement errors as claimed in any one of claims 1 to 6, the method comprising the steps of:
measuring and obtaining the working current Icc of a bare chip to be tested;
and step two, connecting an Iload load current source equivalent to the working current Icc IN value or amplitude to a certain digital input pin IN of the bare chip to be tested.
8. The method of reducing analog voltage measurement error of claim 7, wherein: the hot end of the Iload load current source is connected with the digital input pin IN of the bare chip to be tested through an impedance network, and the cold end of the Iload load current source is connected with the power supply Vee.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810029278.XA CN108333411B (en) | 2018-01-12 | 2018-01-12 | Circuit and method for reducing analog voltage measurement error |
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| CN201810029278.XA CN108333411B (en) | 2018-01-12 | 2018-01-12 | Circuit and method for reducing analog voltage measurement error |
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| CN108333411B true CN108333411B (en) | 2020-06-16 |
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| US7825678B2 (en) * | 2008-08-22 | 2010-11-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Test pad design for reducing the effect of contact resistances |
| DE102010036847B4 (en) * | 2010-08-04 | 2015-01-08 | Phoenix Contact Gmbh & Co. Kg | Method and device for external current detection |
| CN102707214B (en) * | 2012-05-14 | 2013-06-12 | 江阴新顺微电子有限公司 | Method for detecting positive and saturation voltage drop of transistor chip of discrete device |
| CN103091617B (en) * | 2013-01-29 | 2017-08-15 | 无锡华润上华科技有限公司 | A kind of semiconductor test method |
| JP6155725B2 (en) * | 2013-03-19 | 2017-07-05 | 富士電機株式会社 | Semiconductor device inspection method and semiconductor device manufacturing method using the same |
| CN105021865B (en) * | 2015-06-04 | 2017-12-01 | 深圳市芯海科技有限公司 | A kind of compensable voltage measurement method |
| CN107843762B (en) * | 2017-12-01 | 2023-08-15 | 北京华峰测控技术有限公司 | Measuring circuit and method for on-state voltage drop of wafer die |
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