CN105009275A - 具有由虚栅极分隔的连续有源区的金属氧化物半导体(mos)隔离方案及相关方法 - Google Patents

具有由虚栅极分隔的连续有源区的金属氧化物半导体(mos)隔离方案及相关方法 Download PDF

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Publication number
CN105009275A
CN105009275A CN201480013153.8A CN201480013153A CN105009275A CN 105009275 A CN105009275 A CN 105009275A CN 201480013153 A CN201480013153 A CN 201480013153A CN 105009275 A CN105009275 A CN 105009275A
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CN
China
Prior art keywords
gate
mos
work function
type metal
mos device
Prior art date
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Pending
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CN201480013153.8A
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English (en)
Chinese (zh)
Inventor
B·杨
X·李
P·齐达姆巴兰姆
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Qualcomm Inc
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Qualcomm Inc
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Publication of CN105009275A publication Critical patent/CN105009275A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H10D30/0243—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET] using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/765—Making of isolation regions between components by field effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • General Engineering & Computer Science (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
CN201480013153.8A 2013-03-13 2014-03-10 具有由虚栅极分隔的连续有源区的金属氧化物半导体(mos)隔离方案及相关方法 Pending CN105009275A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/799,955 2013-03-13
US13/799,955 US9997617B2 (en) 2013-03-13 2013-03-13 Metal oxide semiconductor (MOS) isolation schemes with continuous active areas separated by dummy gates and related methods
PCT/US2014/022263 WO2014159160A1 (en) 2013-03-13 2014-03-10 Metal oxide semiconductor (mos) isolation schemes with continuous active areas separated by dummy gates and related methods

Publications (1)

Publication Number Publication Date
CN105009275A true CN105009275A (zh) 2015-10-28

Family

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Application Number Title Priority Date Filing Date
CN201480013153.8A Pending CN105009275A (zh) 2013-03-13 2014-03-10 具有由虚栅极分隔的连续有源区的金属氧化物半导体(mos)隔离方案及相关方法

Country Status (6)

Country Link
US (2) US9997617B2 (enExample)
EP (1) EP2973682A1 (enExample)
JP (2) JP2016516301A (enExample)
KR (1) KR20150131090A (enExample)
CN (1) CN105009275A (enExample)
WO (1) WO2014159160A1 (enExample)

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CN107424932A (zh) * 2016-05-02 2017-12-01 台湾积体电路制造股份有限公司 FinFET结构及其形成方法
CN109417033A (zh) * 2016-06-28 2019-03-01 株式会社索思未来 半导体装置以及半导体集成电路
CN109716529A (zh) * 2016-09-21 2019-05-03 高通股份有限公司 FinFET中布图效应减缓
CN115117148A (zh) * 2022-06-28 2022-09-27 上海华力集成电路制造有限公司 Mos晶体管的伪有源区的结构和制造方法

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US9318476B2 (en) * 2014-03-03 2016-04-19 Qualcomm Incorporated High performance standard cell with continuous oxide definition and characterized leakage current
US9209185B2 (en) * 2014-04-16 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for FinFET device
US10468528B2 (en) 2014-04-16 2019-11-05 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device with high-k metal gate stack
US9178067B1 (en) 2014-04-25 2015-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET device
US9721955B2 (en) 2014-04-25 2017-08-01 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for SRAM FinFET device having an oxide feature
US9224736B1 (en) 2014-06-27 2015-12-29 Taiwan Semicondcutor Manufacturing Company, Ltd. Structure and method for SRAM FinFET device
KR102202754B1 (ko) * 2014-08-14 2021-01-15 삼성전자주식회사 반도체 장치
US10361195B2 (en) * 2014-09-04 2019-07-23 Samsung Electronics Co., Ltd. Semiconductor device with an isolation gate and method of forming
US9502414B2 (en) * 2015-02-26 2016-11-22 Qualcomm Incorporated Adjacent device isolation
KR102240021B1 (ko) 2017-03-03 2021-04-14 삼성전자주식회사 저항을 포함하는 반도체 소자
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US10679994B1 (en) * 2018-11-28 2020-06-09 Qualcomm Incorporated Circuits employing asymmetric diffusion breaks in different type semiconductor diffusion regions, and related fabrication methods
US11145550B2 (en) 2020-03-05 2021-10-12 International Business Machines Corporation Dummy fin template to form a self-aligned metal contact for output of vertical transport field effect transistor
US12199152B2 (en) 2021-01-18 2025-01-14 Samsung Electronics Co., Ltd. Selective single diffusion/electrical barrier
US11646361B2 (en) 2021-03-04 2023-05-09 Globalfoundries U.S. Inc. Electrical isolation structure using reverse dopant implantation from source/drain region in semiconductor fin
US12142637B2 (en) * 2021-06-29 2024-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacturing the same
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CN107424932A (zh) * 2016-05-02 2017-12-01 台湾积体电路制造股份有限公司 FinFET结构及其形成方法
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CN109716529A (zh) * 2016-09-21 2019-05-03 高通股份有限公司 FinFET中布图效应减缓
CN115117148A (zh) * 2022-06-28 2022-09-27 上海华力集成电路制造有限公司 Mos晶体管的伪有源区的结构和制造方法

Also Published As

Publication number Publication date
EP2973682A1 (en) 2016-01-20
JP2016516301A (ja) 2016-06-02
US20180240890A1 (en) 2018-08-23
JP2018113485A (ja) 2018-07-19
KR20150131090A (ko) 2015-11-24
WO2014159160A1 (en) 2014-10-02
US20140264610A1 (en) 2014-09-18
US9997617B2 (en) 2018-06-12

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