CN1050007C

CN1050007C - Layout method of integrated circuit

Info

Publication number: CN1050007C
Application number: CN95103182A
Authority: CN
Inventors: 曾信闵; 王国会
Original assignee: Holtek Semiconductor Inc
Current assignee: Holtek Semiconductor Inc
Priority date: 1995-04-05
Filing date: 1995-04-05
Publication date: 2000-03-01
Anticipated expiration: 2015-04-05
Also published as: CN1132938A

Abstract

The present invention relates to a layout method of an integrated circuit, wherein the output of a logic gate in a first direction is used as the layout of a circuit mode of the input of a logic gate. An integrated circuit comprises a plurality of logic gate structures in the first direction and a plurality of logic gate structures in a second direction. A plurality of polycrystal areas are arranged above each logic gate structure. The present invention comprises the following steps: P+ transplanted and n+ buried layers are made in the polycrystal areas above logic gate structures in the first direction and the second direction to form input ends of logic gates in the first and the second directions according to the required number of the input ends in the first direction and the second direction. The present invention makes the layout of the integrated circuit have extensibility.

Description

The layout method of integrated circuit

The present invention relates to a kind of layout method, relate in particular to layout (layout) method of a kind of integrated circuit (IC).

See also Fig. 1, NOT-AND gate (NANDgate) Y1 of Y direction that Fig. 1 has comprised a plurality of (is example with 4) ..., Y4, and the NAND door X1 of a plurality of directions Xs ..., X4, and Y1 ..., Y4 output YO1 ..., YO4 can be used as directions X NAND door X1 ..., X4 input, and Y direction NAND door Y1 ..., Y4 can have the input of different numbers, this sentences Y1 and has 2 (YI1, YI2), Y2 has 2 (YI1, YI2), Y3 has 3 (YI1, YI2, YI3), and Y4 has 4 inputs (YI1, YI2, YI3, YI4) and is example; X1 ..., also can the have nothing in common with each other input of number of X4, this sentences X1 and has 2 (YO1, YO2), X2 has 2 (YO1, YO2), X3 has 3 (YO1, YO2, YO3), X4 has 4 inputs (YO1, YO2, YO3, YO4) and is example; With the output of Y direction gate as in the most normal circuit that is applied to encoder (encoder) and decoder (decoder) of the logical construction of directions X gate input.

With each 4 NAND door of Fig. 1 X, Y direction is that example illustrates usually the layout method to Fig. 1 logic gates: common layout method is to get 2 unit (cell) with 2 inputs (Fig. 2 a), unit (Fig. 2 b) with 3 inputs, unit (Fig. 2 c) with 4 inputs, as Y1 ..., Y4; Directions X is as the same, those unit is coupled together thereafter again.

By above description as can be known, common layout method is to get a plurality of unit those unit to be coupled together again.Common layout method has following shortcoming, after the layout of entire I C has been finished, if want to change Y1 ..., Y4, X1 ..., any one input number among the X4, unit taking-up that then must be original is changed another unit again and is entered, for example, desire changes the Y1 of original 2 inputs into 4 inputs, then the unit shown in Fig. 2 a must be taken out, and replaces with the unit shown in Fig. 2 c again; But the layout of entire I C is finished, if change the unit again, must destroy the layout of entire I C, for example increase to 4 inputs by 2 inputs, can't find on the IC circuit that layout is finished probably can be for the arrangement space that holds 4 inputs, or must change the original layout of entire I C, just can increase the input number of gate again.That is to say that common layout method lacks flexibility and extendibility.

Main purpose of the present invention is to provide a kind of layout method of integrated circuit, makes layout have elasticity and extendibility.

The present invention is a kind of layout method of integrated circuit, this method is used for the layout of first direction gate output as the circuit-mode of second direction gate input, this integrated circuit comprises that a plurality of first direction gate structures are connected in a plurality of second direction gate structures, and each gate superstructure has a plurality of polycrystalline zone; This method comprises: according to the required input number of first and second direction gate, be p in the polycrystalline zone of first and second direction gate superstructure ⁺Inject and n ⁺Buried regions forms the input of first and second direction gate.

The first direction gate is connected with the polycrystal layer of its metal level with the second direction gate; Here, first direction is meant the Y direction, and second direction is meant directions X; X, Y direction gate structure is formed with PMOS and NMOS.

Wherein, p is in the polycrystalline zone of PMOS in zone that can become input of each polycrystalline domain representation of gate top ⁺Inject, represent that this polycrystalline zone is an effective input, is n in the polycrystalline zone of NMOS ⁺Buried regions represents that this polycrystalline zone is an invalid input.The PMOS of each gate is identical with effective input number of NMOS.This gate can be the NAND door.

Following accompanying drawing of mat and detailed description can be understood the present invention in depth.

Fig. 1 is the logical circuit schematic diagram that is used to decipher coding.

Fig. 2 is that several of common IC layout have the schematic diagram of the unit of different number inputs.

Fig. 3 is the schematic diagram of the IC layout preferred embodiment that obtains of layout method of the present invention.

See also Fig. 3, it is the layout of the inventive method, be the structure of NAND door below metal level, and each NAND door is made up of PMOS and NMOS, and aspect PMOS, if wish to get an input, then p is in the polycrystalline zone above metal level ⁺Inject, and aspect NMOS, be n in the polycrystalline zone for non-input ⁺Buried regions, all the other are not n ⁺The polycrystalline zone of buried regions is input, and wherein, the input number of the PMOS of each NAND door must be identical with the input number of NMOS.

In the Y direction, be benchmark with the maximum fan-in that gate was had of fan-in, the polycrystalline number of regions that decides each gate to have, in the present embodiment, the fan-in of Y4 is maximum, has 4, so each gate all has 4 polycrystalline zones that can become input for you to choose; Directions X is as the same.

With the logical circuit of Fig. 1, Y1 has 4 polycrystalline zones that can become input, but only uses 2 input Y11, Y12 herein, so p is in the 1st, 2 polycrystalline zone above the PMOS metal level of NAND door Y1 ⁺Inject, obtain input YI1, YI2, and aspect NMOS, then be n in the 3rd, 4 the polycrystalline zone right by a left side ⁺Buried regions lost efficacy the 3rd, 4 input of NMOS, and staying Y11, Y12 is input; In like manner, p is in the YI1 above the PMOS metal level of NAND door Y2, YI2 polycrystalline zone ⁺Inject, be n in YI3, the YI4 zone of NMOS ⁺Buried regions lost efficacy YI3, YI4, stayed 2 inputs of YI1, YI2; YI1, YI2, YI3 at PMOS are p ⁺Inject, be n at the YI4 of NMOS ⁺Buried regions, 3 inputs of formation NAND door Y3; YI1-YI4 at PMOS is p ⁺Inject, then be not n at the YI1-YI4 of NMOS ⁺Buried regions obtains 4 inputs of Y4.At directions X, X1 has YO1 and 2 inputs of YO2, so be n in the NMOS of X1 part for the polycrystalline zone that connects YO3, YO4 ⁺Buried regions makes YO3, YO4 invalid, and in the PMOS of X1 part, is p for the polycrystalline zone that connects YO1, YO2 ⁺Inject, make YO1, YO2 become effective input of X1; In like manner, X2 has YO1 and 2 inputs of YO2, so be n in the NMOS of X2 part for the polycrystalline zone that connects YO3, YO4 ⁺Buried regions makes YO3, YO4 invalid, and is p in the PMOS of X2 part for the polycrystalline zone that connects YO1, YO2 ⁺Inject, make YO1, YO2 become effective input of X2; X3 has YO1, YO2 and 3 inputs of YO3, so be n in the NMOS of X3 part for the polycrystalline zone that connects YO4 ⁺Buried regions makes YO4 invalid, and is p in the PMOS of X3 part for the polycrystalline zone that connects YO1, YO2, YO3 ⁺Inject, make YO1, YO2, YO3 become effective input of X3; X4 has YO1 is arranged, YO2, YO3,4 inputs of YO4, so be not n in the polycrystalline zone of the NMOS of X4 part ⁺Buried regions, and be p for the polycrystalline zone that connects YO1, YO2, YO3, YO4 in the PMOS of X4 part ⁺Inject, make YO1, YO2, YO3, YO4 become effective input of X4.

By the above embodiments as can be known, integrated circuit layout method provided by the invention is a kind of method with systematicness and extendibility, with regard to above-mentioned example, supposes after the layout of entire I C is finished, if desire to make Y1, Y2, Y3, Y4, X1, X2, X3, X4 increase or reduce input again, then only need to insert/remove p at original polycrystalline ⁺Inject or n ⁺Buried regions gets final product, do not influence the whole IC circuit distributing position of having finished layout fully, the expandability that has fully shown the IC layout, and, the layout of overall logic is an overall zone, rather than the irregular area as getting up with the unit pocket usually, so in the application of spatial area, also can come efficiently than common layout type.

Though those skilled in the art that scholar can do various modifications to above-mentioned specific practice with the principle that the present invention discloses, they are all among the scope of appended claims desire protection.

Claims

1. the layout method of an integrated circuit, this method is used for the layout of first direction gate output as the circuit-mode of second direction gate input, it is characterized in that, described integrated circuit comprises that a plurality of first direction gate structures are connected in a plurality of second direction gate structures, and each described gate superstructure has a plurality of polycrystalline zone; Described layout method comprises:

According to the required input number of described first and second direction gate, be p in the polycrystalline zone of described first and second direction gate superstructure ⁺Inject and n ⁺Buried regions forms the input of described first and second direction gate.

2. the layout method of integrated circuit as claimed in claim 1 is characterized in that, described first direction gate is connected with the polycrystal layer of its metal level with described second direction gate.

3. the layout method of integrated circuit as claimed in claim 1 is characterized in that, described first direction is meant the Y direction, and described second direction is meant directions X.

4. the layout method of integrated circuit as claimed in claim 3 is characterized in that, described X, and Y direction gate structure is formed with PMOS and NMOS.

5. the layout method of integrated circuit as claimed in claim 4 is characterized in that, each zone that can become input of described polycrystalline domain representation of described gate top.

6. the layout method of integrated circuit as claimed in claim 5 is characterized in that, is p in the polycrystalline zone of described PMOS ⁺Inject, represent that described polycrystalline zone is an effective input.

7. the layout method of integrated circuit as claimed in claim 6 is characterized in that, is n in the polycrystalline zone of described NMOS ⁺Buried regions represents that described polycrystalline zone is an invalid input.

8. the layout method of integrated circuit as claimed in claim 7 is characterized in that, the described PMOS of described each gate is identical with effective input number of NMOS.

9. the layout method of integrated circuit as claimed in claim 1 is characterized in that, described gate is the NAND door.