CN104981807A - Alteration of a signal value for an fpga at runtime - Google Patents

Abstract

The invention relates to a method for altering a signal value for an FPGA (5) at runtime, comprising the steps of loading an FPGA hardware configuration (24) with at least one signal value onto the FPGA (5), executing the FPGA hardware configuration (24) on the FPGA (5), setting the signal value for transmission to the FPGA (5), determining write back data from the signal value, writing the write back data as state data to a configuration memory (8) of the FPGA (5), and transmitting the state data from the configuration memory (8) to the functional level (6) of the FPGA (5). The invention furthermore relates to a method for performing an FPGA build on the basis of an FPGA model (20) in a hardware description language, comprising the steps of creating an FPGA hardware configuration (24) with a plurality of signal values, arranging signal values in adjacent regions of the FPGA hardware configuration (24), ascertaining memory locations (9) in a configuration memory (8) for state data for the plurality of signal values on the basis of the FPGA hardware configuration (24), creating a list containing signal values that can be accessed at runtime and the corresponding memory locations (9).

Description

Be in operation and change the signal value of FPGA

Technical field

The present invention relates to a kind of for the method changing signal value that is in operation.

Equally, the present invention relates to a kind of data processing equipment, described data processing equipment has processor unit and FPGA, and wherein data processing equipment is embodied as performing said method.The present invention also relates to a kind of computer program, described computer program has computer-implemented instruction, this computer program implements the step of said method after loading in suitable data processing equipment and implementing, and relate to a kind of digital memory me, it has the control signal that electronically readable is got, and described control signal can make to implement said method with the mating reaction of programmable data treating apparatus.Finally, the present invention includes a kind of method for performing FPGA structure with hardware description language based on FPGA model.Hardware description language can such as VHDL or figure or exist as Simulink program in the form of text.

Background technology

The real-time simulation of complicated dynamic model proposes high request to modern computing node due to strict time boundary condition itself.In automobile hardware-in-loop simulation (HiL), especially such model is used in the place that fast control loop must close, such as, for the very dynamic part of environmental model.This such as when emulating internal cylinder pressure sensor situation like this, internal cylinder pressure sensor plays increasing effect when consuming or waste gas reduces.Even if but in the regulating system with high dynamic such as in the motor, short cycling time and little delay are indispensable.Described short cycling time and little delay utilize the emulation based on CPU almost no longer can realize in practice.FPGA enters the field of rapid control prototyping (RCP) more and more, because the environmental model emulated (such as emulated motor) or opertaing device must more and more accurately and become increasingly complex.On this point, such as complicated control section is extended in FPGA, thus guarantees to keep enough accurately and reaction time fast.

Mode aided solving node when real-time simulation that field programmable gate array (FPGA) can bear the calculating of the dynamic part of model by it.Due to possibility and the high flexibility of the parallel processing of signal, also can easily meet hard real time requirement by using FPGA.FPGA can be used as the hardware accelerator of the CPU of computing node.To the DS5203-FPGA plate of such embodiment of HiL emulator dSPACE in this way.Correspondingly, the very high dynamic part of such as environmental model expands in FPGA, thus guarantees the enough accurately and fast reaction time of opertaing device.FPGA hardware configuration produces with hardware description language based on FPGA model usually in building process.

The model of regulating system becomes increasingly complex owing to improving accuracy requirement and therefore also can be difficult to operation.In automobile HiL environment, such model utilizes the tool set Matlab/Simulink of MathWorks company to create usually.Simulink presents block-based view in form of a block diagram for such model.Model part can be combined into several subsystem in block diagrams and connect with signal each other.Data stream between these blocks is illustrated by signal line at this.

Based in the real-time simulation of CPU, first the block diagram of model translates into C/C++ source file by Simulink scrambler.Then, these C/C++ source files translate into executable application program by compiler, and described application program can utilize the operating system with real-time capacity to perform on computing node.

Additionally, produce trace file when CPU builds, described trace file is topological file, topological file modelling to graphically, such as modelling in Simulink.In TRC file, comprise all addressable variablees and variable mappings to memory location.Variable is preferably by the network topology storage of topological close copy.

Model translation becomes CPU application program to perform with fixing step-length with making the computation sequence emulated.All the time all model states or the consistent mapping of model variable (the I/O value of the data such as on signal line or block) is had thus in the primary memory of computing node.By directly accessing primary memory, model variable can analyzed and/or operation in experimental tool such as ControlDesk.Can the variable that emulates of unrestricted choice ground write/read access HiL.Signal value such as motor rotary speed can be selected by trace file and exported by display or operate.In HiL environment, this mode of operation is summarised as term " measurement " and " adjustment ".

The emulation that can be similar to based on CPU by the FPGA programming module collection of dSPACE and Xilinx system generator (XSG) based on the emulation of FPGA utilizes Simulink modelling in block diagrams.

But with emulate contrary based on CPU, this model is not translated into the programming language of iteration, but translates into hardware description language, and described hardware description language describes the specific digital circuit of client.The building-up process that is described through of the specific circuit of client is translated into FPGA configuration data stream.Especially need to economize on resources in the field of the calibration of the opertaing device of the parameter more than must adjusting very and time-saving method.Calibration data is embodied as constant usually, and wrong high two-way is everlasting during FPGA runs and is there is not change.

For some FPGA likely in order to debugging purpose stops and reading the good working condition of FPGA.But the primary memory that can not be similar to computing node by the closed I/O attribute of FPGA at random access module state and change these model states if desired.Application person wants any model variable measured or adjust must be guided to the interface of FPGA via signal line by explicit model.After being next to this coupling, model must be translated again, and this can continue several hours.This situation can cause the construction cycle based on the real-time simulation of FPGA very long.Especially, in the field of (such as opertaing device) calibration, when adjusting very many parameters, this can require very many resources.

Summary of the invention

Based on above-mentioned prior art, the present invention therefore based on task be propose a kind of method, a kind of data processing equipment, a kind of computer program and a kind of digital memory me, the control signal that its electronically readable with the above-mentioned type is got, they can realize the model variable operationally changed in FPGA and the overlapping development cycle shortened when creating the real-time simulation based on FPGA.

The solution of this task is realized by the feature of independent claims according to the present invention.Favourable implementations of the present invention is explained in the dependent claims.

According to the present invention, therefore a kind of method for the signal value changing FPGA that is in operation is proposed, it comprises the steps: the FPGA hardware configuration with at least one signal value to be loaded on FPGA, FPGA implements FPGA hardware configuration, signal value for transferring to FPGA is set, by signal value determination write-back, write-back is written in the config memory of FPGA as status data, and status data is transferred to the functional layer of FPGA from config memory.

According to the invention allows for a kind of data processing equipment, described data processing equipment has processor unit and FPGA, and wherein, data processing equipment is embodied as performing said method.

According to the present invention, it is also proposed a kind of computer program, it has computer-implemented instruction, and this computer program performs the step of said method after loading and performing in suitable data processing equipment.

In addition, according to the present invention proposes a kind of digital storage media, described digital storage media has the control signal that electronically readable is got, described control signal can with the mating reaction of programmable data treating apparatus, said method is performed on data processing equipment.

So basic thought of the present invention is can realize being in operation to change the signal value of FPGA, its mode is: at FPGA run duration by status data write-in functions layer, to change signal value.Status data is changed as required, to realize thus changing the signal value in FPGA, does not wherein need the structural change to FPGA.The operation interrupting FPGA is not needed yet.Therefore can unrestricted choice accessing FPGA signal value in order to change.The change of signal value can be carried out as known by the enforcement of software on CPU, comprises and to access via (ü ber) topological file (trace file) and to utilize Simulink graphically modelling.Signal value such as ignition time point correspondingly can be selected and shows and/or change.

The change of the signal value of FPGA only requires the value for this signal value to be written on FPGA.Do not need write value different from the value of the prior setting of signal value.Owing to usually changing the value of signal value in practice, so have selected the term of change at this.

Equally, can realize accessing the signal value of FPGA, its mode is, determines signal value at FPGA run duration thus from FPGA reads status data.Status data is read and combines as required, wherein Structure of need does not change FPGA.The operation interrupting FPGA is not needed yet.Therefore the signal value of FPGA can selectively be accessed.Interrogation signal value can be carried out as known by the execution of software, comprises and to access via topological file (trace file) and to utilize Simulink graphically modelling.Signal value such as motor rotary speed correspondingly can be selected and shows or operate.

In addition, propose a kind of method of the signal value for the access FPGA that is in operation, described method comprises the steps: FPGA hardware configuration to be loaded on FPGA, FPGA implements FPGA hardware configuration, the signal value of request FPGA, status data is transferred in the config memory the configuration layer of FPGA from the functional layer of FPGA, from config memory reads status data as write-back, and by back read data determination signal value.Each step corresponds to the step of the method for changing signal value described above.

Advantageously, the realization of FPGA does not need to change, make to the performance of FPGA and the demand of resource constant.Correspondingly, on normal, not impact is run to the access of signal value, neither in produced FPGA hardware configuration also not the term of execution have an impact.The state of different model variables can as one man store, can realize access.The access to desired signal value can be carried out, and do not produce the FPGA hardware configuration of coupling and need not transmit it in FPGA, can the development time be shortened thus.The real-time characteristic of FPGA and the impact of available resource are avoided or reduced.Especially, different signal values can be read from FPGA as required when not changing FPGA hardware configuration.

Configuration layer relates to the logical layer of FPGA, and this logical layer is used for initialization FPGA.In initial configuration process, configuration data is written in config memory, thus functional layer then pattern drawing turn use into.At run duration, so such as all content of registers of functional layer are mirrored in configuration layer to returning by trigger.The content of config memory then can be read to determine signal value thus.Otherwise, so such as all the elements can be transferred to the content of registers of functional layer from the config memory configuration layer by trigger at run duration.Such trigger can be such as reset signal.Reset signal can arrange for a part of FPGA or set for the multiple registers in FPGA program clearly.When the change in configuration layer directly acts on functional layer, such trigger can not be needed to the change of look-up table and multiplexer.

The selection of signal value at random can change at run duration.Preferably, multiple signal value is conducted interviews as back read data and/or write-back.

Back read data and/or write-back can comprise the arbitrary data unit of FPGA.Back read data and/or write-back can comprise each register value of FPGA or larger memory block.Memory block can be such as the retaking of a year or grade row of FPGA.Back read data and write-back are structurally identical and only conceptually different.Preferably, the signal value that change is implemented as the constant in FPGA, and such as implement as Simulink constant block, described Simulink constant block only must be mated between development stage.

The ordering principle of illustrated method can change and be not limited to the order illustrated by this.Especially, the method performs to change signal value and/or access described signal value in loading with after implementing FPGA hardware configuration, so that repeated accesses signal value or to change signal value.

Produce the write access to FPGA.Described access is operationally carried out, and does not affect FPGA.Described details is correspondingly applicable to carry out write access for change signal value and can separately respective application to the read access of the signal value of FPGA and being applicable to respectively.

The signal value for changing FPGA carry out write access time carry out reshuffling of the dynamic part of FPGA, the corresponding relevant portion comprising signal value wherein in FPGA is in operation capped.Reconfigurable look-up table, reconfigurable register or reconfigurable multiplexer can be mapped at this such as Simulink constant block or other modellings any to signal value.The signal value that can change mapping in the operation of FPGA is reshuffled dynamically by the part to look-up table, register or multiplexer.The signal value comprising multiple can be mapped on multiple element if desired dividually.According to used FPGA and FPGA program, signal value can be favourable to the different mappings of FPGA element.Favourable mapping can be determined by the analysis before structure FPGA program.

Data processing equipment principle can at random be implemented.FPGA is typically arranged in data processing equipment or with this data processing equipment as expansion module and is connected.Data processing equipment can be connected via data cube computation with remote control computer.Particularly preferably via the application program interrogation signal value on computer for controlling.

The display of signal value can be carried out as graphics view.At this, signal value preferably can pass through " drag and drop " and move on the instrument of display, for display signal value from list.Otherwise, the signal value that " drag and drop " are selected to change from list can be passed through equally.Equally, the value of the signal value that can be changed by " drag and drop " is set on selected signal value.

From config memory, reads status data does not comprise change to data as back read data, but only relates to notional definition.Corresponding contents is applicable to write-back.Term " write-back " only will illustrate, signal value is written in FPGA, to change the signal value in FPGA.

By back read data determination signal value and/or by signal value determination write-back in principle can at an arbitrary position on carry out, such as carry out on the CPU or computer for controlling of FPGA, data processing equipment.Correspondingly, status data, register data or signal value can be transmitted respectively as required strategic point.

Via interface, read access and/or write access are carried out to the config memory of FPGA from FPGA outside.The common framework of config memory comprises interface, and this interface has the clock frequency of 32 bit widths and 100MHz when the minimum read volume of a frame.Corresponding contents is applicable to carry out write access.Thus, utilize common at present FPGA to access accurately with the circulation within the FPGA cycle by the meaning of FPGA debugger or FPGA indicator (Scope) and described method can not be used.A frame can also comprise about the information of look-up table and about multiplexer configuration or the information configured that connects up except comprising register value.Such as comprised by back read data determination signal value and to find out from frame and to extract register value.Correspondingly, be such as included in frame by signal value determination write-back and find out register value and register value is set according to signal value.Also that can carry out read access from the inner interface via inside of FPGA to the config memory of FPGA and/or write access.Such internal interface is such as " the inner configuration access port (ICAP) " of Xilinx company.

In favourable embodiment of the present invention, the method functional layer status data being transferred to FPGA from config memory before comprise additional step: status data is transferred to from the functional layer of FPGA in the config memory the configuration layer of FPGA.Correspondingly, to be transferred in the configuration layer of FPGA as status data in write-back before, such as, the initialization of the configuration layer of FPGA can be performed.To the Change Example of signal value as also carried out from the signal value read in advance.When status data to transfer to from config memory with the unit being greater than the signal value that will change the functional layer of FPGA, config memory can carry out initialization by the status data of prior transfer function layer, thus after in state transfer to functional layer, is regenerating virgin state except the external of modified signal value.Correspondingly, can signal value be changed, and be in operation do not change FPGA in all the other attributes of FPGA.This is especially applicable to, and the status data that be transferred in functional layer represents constant value, and described value is in operation and does not change.In principle, be also suitable for, do not changing functional layer by status data transfers to configuration layer and between in status data transfers to functional layer.By status data transfers to the functional layer of FPGA time, write-back can comprise the information being additional to signal value.Therefore, preferably first reads status data, as the basis of write-back, and adds to signal value in described status data.Thus, the data integrity of FPGA can be ensure that.

Preferably, when creating FPGA program, by changeable signal value and FPGA, the element in functional layer has been arranged dividually jointly, and the configuration of described functional layer is in operation and can such as changes with type of variables.Like this, can guarantee when the reshuffling of part, the FPGA part changed that is in operation can not by mistake be capped.Because FPGA can continue to run during the method, usually only must transmitted from functional layer by status data and can produce change by the function of FPGA between write-back being transferred to functional layer, these changes are eliminated by described method.

When be not in operation in the region that will write the element carrying out changing time, before each change of signal value, do not need the status data transfers in the region that will write to configuration layer and reads status data.Just enough to the once reading of status data in principle, because status data does not change at the run duration of FPGA.

Due to element be configured in FPGA initialization time determined, alternatively can preserve the basic initialization of FPGA and use these values when the write in the region of configuration layer.

In favourable embodiment of the present invention, comprised by the step of signal value determination write-back and signal value is mapped to write-back.In favourable embodiment of the present invention, comprised by the step of back read data determination signal value and back read data is mapped on signal value.For coordinating mutually as the expression of register, look-up table, multiplexer in FPGA with signal value by signal value determination write-back or by the mapping of back read data determination signal value, or realized by wiring.Register is such as the storer in functional layer, and its data can copy simply and can be used for determining signal value.This can realize identifying the data for determining signal value.Can not be read due to each register or write and configuration layer can only work in subregional, so signal value must be mapped on the configuration bit in described region.

In favourable embodiment of the present invention, comprised at least one register value being determined FPGA by described signal value by the step of signal value determination write-back.In favourable embodiment of the present invention, comprised by least one register value determination signal value of FPGA by the step of back read data determination signal value.The tissue of signal value at least one register described can be arbitrary, and therefore content of registers must be processed, to determine signal value or to be determined the status data of the change desired by signal value by content of registers.Especially, signal value can be distributed on multiple register, and the content of register is processed together, to determine signal value, or is determined the status data of the change desired by signal value by multiple content of registers.

In favourable embodiment of the present invention, using write-back as the step that status data is written in the config memory of FPGA comprise determine config memory for the region changed needed for signal value and the status data writing the desired zone of config memory as back read data.In favourable embodiment of the present invention, from configuration register reads status data as the step of back read data comprise determine config memory for the region determined needed for signal value and the status data reading the desired zone of config memory as write-back.Determine the address of config memory, the configuration bit addressing of register, look-up table or the multiplexer that can be encoded wherein to signal value by described address, and select according to the signal value that will regulate in the operation of FPGA, thus write access or read access can be carried out to config memory, and without the need to mating FPGA hardware configuration in advance.By determining desired zone, reading and/or the write of status data can be limited to described region, and less data must be read, transmit and/or write thus.

In favourable embodiment of the present invention, by status data from the step that config memory is transferred to the functional layer of FPGA comprise the functional layer determining FPGA for the part needed for write state data and by this fractional transmission of status data in functional layer.In favourable embodiment of the present invention, status data is comprised from the step that the functional layer of FPGA is transferred to the config memory of its configuration layer the described part of preservation state data to the part determined needed for signal value and in its config memory determining status data.Region/part that is that transmit and/or that will write is in operation and is determined, thus can transmit and/or write state data, and need not mate FPGA hardware configuration in advance.By determining required region/part, preservation/or the storage of status data can be limited to described region, and less data must be saved and/or store thus.

In favourable embodiment of the present invention, determine config memory for the region changed needed for signal value and/or determine that the comprising for the part needed for write state data of functional layer of FPGA identifies corresponding region by identification code.Identification code principle can be determined at any time.Preferably, identification code is determined when using the model of FPGA hardware configuration.Particularly preferably, for attaching troops to a unit the identification code of univocality in each region, conducted interviews by described identification code.Signal value such as can be addressed to the region of config memory by the identification code in region thus.Identification code such as may be embodied as the block ID for identification model block.Block ID can be followed the tracks of by the different step creating FPGA program.So by block ID can simply by FPGA element as register, look-up table or multiplexer are attached to model block.

In favourable embodiment of the present invention, the step arranging the signal value for transferring to FPGA comprises the list of the signal value providing available and selects signal value from described list.In favourable embodiment of the present invention, the step of the signal value of request FPGA comprises the list of the signal value providing available and selects signal value from described list.Described list principle can be created at any time.Preferably, described list is created when using the model of FPGA hardware configuration.Particularly preferably, for each signal value is attached troops to a unit the identification code of univocality, conducted interviews by described identification code.

In favourable embodiment of the present invention, status data is comprised from the step that config memory is transferred to the functional layer of FPGA and sends reset signal to FPGA.Reset signal is following signal, and status data is transferred to the functional layer of FPGA from config memory by its startup.Corresponding transmission can be carried out in short time, such as several circulation, wherein by arranging the time point that reset signal can control for being transferred to from config memory by status data functional layer.Reset signal can be global reset signal, and it acts on following all elements of FPGA, and the region of the configuration layer of described element participates in resetting.

In favourable embodiment of the present invention, the step to FPGA transmission reset signal comprises transmission reset signal and is partly transferred to the functional layer of FPGA from config memory for by status data.Can the change of executive signal value effectively by partly transmission state data.Only need the less resource of FPGA, especially make the application in real-time system become easy thus.Less desirable effect can be avoided, as it may be formed by Global reset by the Special reset circuit of the register that only should be able to regulate in response to (ansprechen).

If the signal value regulated realizes with the form of look-up table or multiplexer, then can save reset circuit when the data of configuration layer are directly received by look-up table or multiplexer.

In favourable embodiment of the present invention, the step that FPGA implements FPGA hardware configuration comprises hardware configuration is embodied as real-time application, and is performed in the operation of application in real time for the method for the signal value changing FPGA.Being applied in real time in sequential requires very strictly, thus the change of the resource provided can cause the attribute of application in real time to change.In a situation in which the method according to the present invention is applied, signal value can be changed or read access is carried out to it, and the resource of FPGA hardware configuration need not change.Independently can carry out with the enforcement of FPGA hardware configuration the change of signal value, thus the relative influence to FPGA hardware configuration that caused by the change of signal value does not occur.

In addition, provide a kind of method for performing FPGA structure with hardware description language based on FPGA model, described method comprises the steps: to create FPGA hardware configuration.Determine the memory location of the config memory of the status data at least one signal value based on FPGA hardware configuration, and create there is be in operation addressable signal value and the list of memory location that corresponds.

In addition, according to the present invention proposes a kind of method for performing FPGA structure with hardware description language based on FPGA model, described method comprises the steps: to create the FPGA hardware configuration with multiple signal value, signalization value in the adjacent region of FPGA hardware configuration, determine the memory location of the config memory of the status data for multiple signal value based on FPGA hardware configuration, and create the list be in operation addressable and/or changeable signal value and memory location corresponding with it.

So the basic thought of the method is, data needed for having been detected by signal value when creating FPGA hardware configuration and processing, make the status data based on detecting when FPGA runs form signal value.Otherwise, the signal value in FPGA also can be changed simply by the known relation between status data and signal value.

Additionally, guaranteed by being disposed adjacent of signal value, in a straightforward manner and can conduct interviews to signal value when only using less resource, for carrying out read access to signal value or changing signal value.

Memory location is preferably the register of FPGA.Register in a model can explicitly modelling or such as by having the block implicitly modelling of delay.This model preferably produces to graphically.

The ordering principle of illustrated method can change and be not limited to the order illustrated by this.Such as, from model, can have in comparatively early time point establishment the list that is addressable and/or the changeable signal value that is in operation that is in operation with hardware description language.

Preferably, be a part for the construction method for the data processing equipment with FPGA in this method built for performing FPGA proposed, wherein, data processing equipment comprises FPGA or coupled.In the method, additionally perform the structure of the CPU to data processing equipment, in CPU trace file maker, wherein carry out the generation of CPU trace file.Additionally, there is be in operation addressable signal value and the list of memory location that corresponds and be converted into machine-readable file, wherein memory location at this also referred to as " assignment of logical file ".Additionally, the trace file for FPGA is produced equally with the trace file of CPU.In a further step, trace file is gathered in trace file combiner by CPU and FPGA.Such as can independently be conducted interviews to signal value by computer for controlling and the realization for the enforcement in CPU or FPGA and/or signal value is changed thus.

In favourable embodiment of the present invention, the method comprises additional step: realize reset signal for being transferred to the functional layer of FPGA by status data from config memory, is wherein comprised from the functional layer that config memory is transferred to FPGA by status data and partly being transmitted by the adjacent area of status data from the FPGA hardware configuration with signal value.Reset signal is following signal, and status data is transferred to the functional layer of FPGA from config memory by its startup.Corresponding transmission can be carried out in short time, such as several circulation, wherein by arranging the time point that reset signal can control for being transferred to from config memory by status data functional layer.At this, run duration by the part of FPGA, reshuffle the corresponding relevant part that can cover in FPGA dynamically.Signal value such as Simulink constant block is mapped to FPGA, namely reconfigurable look-up table, register or multiplexer.Then, by part, reshuffle signal value changed to arbitrary value dynamically.

In favourable embodiment of the present invention, realize reset signal and realize reset signal partly transfer to the functional layer of FPGA from config memory for by status data for status data is comprised from the step that config memory is transferred to the functional layer of FPGA.Can the change of executive signal value effectively by partly transmission state data.Only need the less resource of FPGA, especially make the application in real-time system become easy thus.

In favourable embodiment of the present invention, create and there is addressable and/or changeable signal value and the step of the list of memory location that corresponds comprise and determine that the link of memory location is for formation signal value.How therefore this list comprises determines illustrating of signal value by status data.

In favourable embodiment of the present invention, described method comprises the additional step of FPGA code produced for determining signal value, and wherein FPGA code comprises from config memory reads status data as back read data and by back read data based on having the signal value that can read and the list determination signal value to it corresponding memory location.Therefore can carry out in FPGA completely to status data with aftertreatment to determine signal value.Correspondingly, can only transmit by FPGA the signal value determined, alleviate the burden of its interface thus.

In favourable embodiment of the present invention, the method comprises additional step: produce the FPGA code for changing signal value, wherein, FPGA code comprises based on having the list of the signal value that can read and the memory location corresponded by signal value determination write-back, and write-back is written in the config memory of FPGA as status data.Therefore can carry out in FPGA completely to signal value with aftertreatment to determine status data.Correspondingly, the signal value that only will change transfers to FPGA, alleviates the burden of its interface thus.FPGA can read and write its oneself config memory by internal interface.Such internal interface is such as " the inner configuration access port (ICAP) " of Xilinx company.Alternatively, microprocessor such as Microblaze can be utilized to implement.

The configuration layer of FPGA can only be read by retaking of a year or grade by row or be described by reshuffling of part.Below these row are called retaking of a year or grade row.In favourable embodiment of the present invention, described method comprises additional step: utilize memory location arranging in the retaking of a year or grade row of FPGA to optimize FPGA hardware configuration, described memory location comprises the status data for signal value.Accelerate the access of the status data of signal value by arranging in retaking of a year or grade row and/or change the signal value in FPGA.When all memory locations for signal value are arranged in retaking of a year or grade row, an operation can be utilized to conduct interviews to signal value.Therefore before producing FPGA hardware configuration, the memory location in retaking of a year or grade row is classified.

In favourable embodiment of the present invention, the method comprises additional step: utilize memory location arranging in the adjacent area of FPGA to optimize FPGA hardware configuration, described memory location comprises the state for signal value.Adjacent region can relate to single retaking of a year or grade row or multiple adjacent retaking of a year or grade row of FPGA.By being disposed adjacent the access accelerated memory location.When the memory location for two signal values is arranged in retaking of a year or grade row, an operation can be utilized to conduct interviews to these two signal values.Corresponding contents is applicable to write access, and the signal value wherein only at least temporarily existed in memory location can be written in FPGA.

In favourable embodiment of the present invention, described method comprises additional step: output memory location being added to logical block, in order to provide status data.Memory location (being generally register) can realize reads status data to determine signal value accordingly.When the number of available status data improves, can conduct interviews to the signal value of the number improved.

In favourable embodiment of the present invention, FPGA is Xilinx FPGA.XilinxFPGA also provides the possibility in the reading of run duration part and configuration FPGA equally except providing the possibility repeatedly configured to FPGA.

Accompanying drawing explanation

The present invention is set forth in more detail by preferred form of implementation referring to appended accompanying drawing.In figure:

Fig. 1 shows the schematic diagram of the data handling system with computer for controlling and real-time system,

Fig. 2 shows the detail view of the FPGA of the real-time system in Fig. 1,

Fig. 3 shows the diagram of the method for the structure for performing the real-time system in Fig. 1,

Fig. 4 shows the detail view that the FPGA in Fig. 3 builds,

Fig. 5 shows the detail view of the tissue of config memory in retaking of a year or grade row of the FPGA in Fig. 2,

Fig. 6 shows the schematic diagram of the relational storage content in the retaking of a year or grade row of config memory, wherein left side view shows the distribution in not optimization situation, medial view shows with the optimization of concentrating of associated memory location in retaking of a year or grade row, and right side view shows the optimization be disposed adjacent arranged with relevant retaking of a year or grade

Fig. 7 shows the framework of XML model,

Fig. 8 shows the result of the construction method in Fig. 3 to the distribution on the different parts of the data handling system of Fig. 1,

Fig. 9 show for by the status data transfers of FPGA to the time curve carrying out the computing machine inquired about,

Figure 10 shows the process flow diagram of the method for the signal value for accessing FPGA according to a preferred form of implementation,

Figure 11 shows the process flow diagram of the method for the signal value for changing FPGA according to a preferred form of implementation,

Figure 12 shows the schematic diagram realizing signal value by register on FPGA,

Figure 13 shows the schematic diagram realizing signal value by look-up table on FPGA,

Figure 14 shows the schematic diagram realizing signal value by multiplexer on FPGA,

Figure 15 shows the schematic diagram realizing signal value by the route to VCC/GND on FPGA, and

Figure 16 shows diagram based on the method for the structure for performing the real-time system in Fig. 1 in figure 3 together with the additional details for modeled signal.

Embodiment

Fig. 1 show data handling system 1 according to structure of the present invention, this data handling system has computer for controlling 2 (at this also referred to as host computer system) and real-time system 3.This real-time system 3 connects via the network clearly do not illustrated with computer for controlling 2.

It is Xilinx FPGA in this embodiment that this real-time system 3 comprises with the computing node 4 (also referred to as CN) of unshowned CPU and FPGA 5, described FPGA.Real-time system 3 is arbitrary data processing equipment at this.This FPGA 5 is schematically shown in Figure 2 and comprise functional layer 6 and configuration layer 7.The config memory 8 with multiple memory location 9 is set in configuration layer 7.Configuration layer 7 be FPGA 5 for its initialized logical layer.During initial configuration process, configuration data to be written in config memory 8 and to be transferred in functional layer 6.Memory location 9 corresponds to the register 60 of FPGA 5 in this embodiment, as such as in fig. 12 shown in.Alternative form of implementation relates to by look-up table 61 (as shown in Figure 13), multiplexer 62 (as shown in Figure 14) or realizes memory location 9 according to Figure 15 by the route to VCC/GND, described route is implemented with ConvertBox 63, and relate to supply voltage or to the alternative wiring of ground connection as the realization of basic binary value.

FPGA 5 to be arranged on FPGA plate 10 and to be connected with the controller 12 for access interface 11 by interface 11.Interface 11 when this when clock frequency is 100MHz in the minimum read volume of a frame there is the width of 32.Frame can comprise register value, in any combination about the information of look-up table 61 and/or multiplexer 62 or wiring configuration.FPGA plate 10 is stored the FPGA variable mappings file 13 being used for being conducted interviews by controller 12.Follow-up signal value for accessing FPGA 5 or for the signal value that changes FPGA 5 embodiment respectively corresponding being applicable to change or access.Signal value can be corresponding alternatively by register 60, look-up table 61, multiplexer 62 or realize via the route to VCC/GND at this.

In order to use real-time system 3, following perform structure with reference to such described by Fig. 3 or Figure 16.FPGA model 20 and CPU model 21 are used as the starting base of structure, and both utilizes Simulink to produce.Produced via the hardware description language of VHDL, expansion, assignment of logical file 23 and FPGA hardware configuration 24 in FPGA structure 22 by FPGA model 20.Store list in assignment of logical file 23, this list has the memory location 9 in FPGA 5 config memory 8 of the status data of addressable signal value of being in operation.Also determine the link of memory location 9, in order to form signal value, and be stored in assignment of logical file 23, thus can by status data determination signal value from assignment of logical file 23s, and vice versa.

The machine-readable FPGA variable mappings file 13 addressed before being produced by assignment of logical file 23, described FPGA variable mappings file comprises attaching troops to a unit of the signal value of memory location 9 and machine-readable form.For this reason as being shown specifically in figure 16, form signal XML model 70 by using FPGA model 20 and assignment of logical file 23.In mapped file maker 71, FPGA variable mappings file 13 is produced by signal XML model 70.Built the application program 27 creating in 26 and can implement on the CPU of real-time system 3 at CPU by CPU model 21.In addition, in CPU trace file maker 28, also build 26s from CPU and produce CPU trace file 29.Similarly, produce FPGA trace file 31 at FPGA trace file maker 30, this FPGA trace file maker obtains the signal XML model 70 as input information.In a further step, trace file 29,31 is combined into complete trace file 33 in trace file combiner 32.

This construction method is provided for the down load application program 34 of real-time system 3 as overall result, and described down load application program has application program 27, complete trace file 33, FPGA variable mappings file 13 and FPGA hardware configuration 24.

FPGA structure 22 is shown in Figure 4 in detail.As input, FPGA builds the block diagram 40 that 22 obtain FPGA subsystem, and this FPGA subsystem comprises the combination of fundamental block as addition, multiplication etc.The result of process is Model.ini document 41, and the bit stream that this model document has comprised and interface describe.Interface describes the list comprising total interface, the instantiation in FPGA subsystem of described interface.The cpu i/f corresponding with FPGA interface can be produced by this description.Build at FPGA in the first step of 22, generate HDL describe by the block diagram 40 of FPGA subsystem by Xilinx system generator (XSG) 42, it is that VHDL describes in this embodiment that this HD describes.Then, this is described through synthetics (XST) and is compiled into network list.

The network list of Simulink model is aggregated into complete network list after XSG builds together with common frame parts.Then, whole design is compiled into bit stream by implementation procedure.

Opening relationships between the memory location 9 belonging to FPGA parts in FPGA parts (d type flip flop) or config memory 8 is exported at the block of Simulink block diagram.Progressively build during FPGA builds 22 or refinement (refine) mapping.

If the block diagram of FPGA subsystem is compiled into HDL by XSG, then these two kinds describe in its configuration aspects is similar.This may be used for exporting at the block of such as Simulink block setting up direct relation between the port of entity.

The method is additionally included in memory location 9 arranging in the retaking of a year or grade row of FPGA 5 optimizes FPGA hardware configuration 24, and described memory location comprises the status data of signal value.Config memory 8 retaking of a year or grade row in organize shown in Figure 5.Frame config memory 8 comprise 1 bit wide and 1312 long row and extending on CLB row of functional layer 6.One in the frame correlativity between position and the function element configuring this can be determined by Xilinx instrument.In order to determine a part for signal value therefore interested just frame.By the access arranging the status data that can accelerate signal value in retaking of a year or grade row.When all memory locations 9 for signal value are arranged in retaking of a year or grade row, an operation can be utilized to conduct interviews to signal value.In a preferred form of implementation, in the operation of FPGA 5 and immovable signal value and the changeable FPGA that is in operation configure and be arranged on during retaking of a year or grade arranges dividually.

As shown in left side view in figure 6, first relevant retaking of a year or grade row are distributed on whole config memory 8.The memory location 9 comprising the state of signal value can be arranged in the adjacent area of FPGA 5 by optimizing FPGA hardware configuration 24.Adjacent area can relate to single retaking of a year or grade row or multiple adjacent retaking of a year or grade row of FPGA5.By being disposed adjacent the access accelerated memory location 9.By the memory location 9 of two signal values being arranged in retaking of a year or grade row, an operation can be utilized to conduct interviews to these two signal values.View in the middle of Fig. 6 shows the optimization to the concentration degree of relevant memory location 9 in the retaking of a year or grade that number reduces arranges.Be arranged in FPGA 5 according to the retaking of a year or grade row additional neighbor that Fig. 6 right side view is relevant in further optimizing.

The framework comprising the XML model 70 of the relevant information of signal illustrates to modular form in the figure 7.

The element of the type FPGA subsystem forms the root of each retaking of a year or grade model instance.FPGA subsystem recursively comprises other subsystem examples according to the model hierarchy structure of Simulink.Subsystem not only may be embodied as fundamental block (such as totalizer) in the present context but also may be embodied as Simulink subsystem.The title of subsystem or block and this name storage of HDL entity belonging are in the Property Name or hdl example of subsystem classification.

Each subsystem can comprise multiple signal, and described signal is signal in Simulink model or I/O port.Each signal obtains the identifier of univocality by id attribute.Direction (I/O) due to signal is inoperative and can avoid the redundancy in modelling, so signal classification is the output of block in Simulink model or subsystem as usual.If multiple subsystem shares identical signal, then can with reference to the signal of other subsystem examples by other example of signal reference class.

Signal can be associated with register 60 by synthesis.Equally signal classification with again obtain this between register class and associate.Register 60 to store register 60 initial value frame between relation carry out modelling by corresponding classification.The attribute of signal carrys out modelling by attribute classification.For retaking of a year or grade and then processing signals, especially attribute BinaryPoint, DataType and Width (width) is important.

Register element is associated with multiple position by frame category.Register 60 width attribute that have oneself the same as signal, because the width of signal and this width of register 60 belonging may change.First one illustrated by the position (pos) of position: which position relating to register 60.In addition, position example comprises following information, the value of position can be sheltered from frame word in which word (framewordOffset) of register-bit in this frame with which kind of bitmask (mask).

Retaking of a year or grade model storage is in XML document.Like this, model such as can process by instrument (tool ü bergreifend) widely.This model is by verifying that to XSD framework maintenance is correct on syntax and structure.

The method comprises additional step: produce FPGA code 44 as the retaking of a year or grade application program for determining signal value, and wherein FPGA code 44 comprises and determines signal value by back read data based on FPGA variable mappings file 13 as back read data from config memory 8 reads status data.

The method comprises additional step: produce FPGA code 44 as the write-back application program for changing signal value, and wherein FPGA code 44 comprises by signal value determination write-back and write-back write in the config memory 8 of FPGA 5 as status data based on FPGA variable mappings file 13.Details is described referring to especially Figure 11.

Fig. 8 shows the distribution of results of construction method on different parts.Utilize FPGA to build 22 by Simulink model 20,21 and perform structure.Produce FPGA hardware configuration 24 and be loaded on FPGA 5.This corresponds to step S100 in reference to the method described by Figure 10.Application program 27 is loaded on computing node 4, and complete trace file 33 is transferred to computer for controlling 2.

Be in operation, FPGA hardware configuration 24 is activated and is implemented on FPGA 5.This corresponds to step S110 in reference to the method described by Figure 10.Application program 27 is activated and is implemented on computing node 4.Computer for controlling 2 starts control software design 50, and described control software design is that dSPACE controls desktop software in this embodiment.Control desktop 50 to be communicated by computing node 4 with real-time system 3, as shown in Figure 1.

In order to the signal value at run duration display FPGA 5, this signal value can be asked by controlling desktop 50.This corresponds to step S120 in reference to the method described by Figure 10.To the access of unlike signal value by complete trace file 33 with utilize the graphical modeling of Simulink to carry out.The expression of signal value represents as figure to be carried out, wherein, for display signal value on the instrument that signal value is pulled to display by " drawing " from list.Identification code by univocality carrys out the signal value in identification list.

Signal value is asked from computing node 4 by controlling desktop 50.For this reason, computing node 4 realizes data acquisition service 51, this data acquisition service receives request from control desktop 50.By data acquisition service 51 from the controller 12 request msg value for FPGA 5.The functional layer 6 of status data from FPGA 5 transfers to the config memory 8 of FPGA in the startup of FPGA 5 run duration by it.This step corresponds to step S130 in reference to the method described by Figure 10.At run duration, so be mirrored in configuration layer 7 by all content of registers of trigger by functional layer 6.In the alternative form of implementation, determine status data this part is only stored in config memory 8 by the part determined needed for signal value by FPGA variable mappings file 13.

In addition, in FPGA 5 by retaking of a year or grade application program 44 from config memory 8 reads status data as back read data.This corresponds to step S140 in reference to the method described by Figure 10.The back read data read comprises one or more frame at this, i.e. one or more retaking of a year or grade row of FPGA 5.At this, first determine the retaking of a year or grade row for determining required for signal value, and only read these retakings of a year or grade row.Information about required retaking of a year or grade row is determined by FPGA variable mappings file 13.

In FPGA 5, signal value is determined based on back read data.This corresponds to step S150 in reference to the method described by Figure 10.For this reason, search from frame and extract register value.These information is produced from FPGA variable mappings file 13.Back read data is mapped at least one register value.At this, if needed, just form signal value by the status data of multiple register 60.Correspondingly, the content of register 60 is processed, to determine signal value together according to FPGA variable mappings file 13.

The signal value determined like this is transferred to controller 12 by the interface 11 of FPGA 5, and signal value is transferred to the control desktop 50 of computer for controlling 2 by this controller by the data acquisition service 51 of computing node 4.

Fig. 9 shows the time curve for status data to be transferred to the computing machine carrying out inquiring about from the functional layer of FPGA.

Be similar to the signal value to FPGA 5 described above and carry out read access, also can carry out write access for the signal value changing FPGA 5, this write access describes referring to Figure 11.

Method for changing the signal value of FPGA 5 starts FPGA hardware configuration to be loaded on FPGA 5 in step s 200.Step S200 corresponds to previously described step S100.

With step S110 described above consistently, start on FPGA 5 in step S210 and implement FPGA hardware configuration 24.

The FPGA signal value that will arrange is selected in step S215.As the basis for changing FPGA signal value, in step S220 to S250, consistently read signal value from the functional layer 6 of FPGA 5 with corresponding step S120 to S150 described above.

Signalization value in step S260.First show read signal value to user, then for signal value arranges new value for this reason.

By signal value determination write-back in step S270.Based on the determination being carried out write-back by the principle of back read data determination signal value above described by reference step S150.Correspondingly, signal value is mapped to the write-back for one or more register 60.In step S230, the change carried out in the status data transmitted because the change of signal value causes is carried out above.

In step S280, write-back is written in the config memory 8 of FPGA as status data.Based on reference to the principle of the reading to status data described by step S140, write-back being written in config memory 8 above.Correspondingly, all status datas comprising the region of the configuration of signal value in functional layer 6 are mirrored onto there.

In step S290, write-back is transferred to the functional layer 6 of FPGA 5 from config memory 8.Based on reference to the principle of the transmission of the status data to functional layer 6 described by step S130, write-back being transferred in config memory 8 above.

The different realization of signal value is described referring to Figure 12 to 15.

Figure 12 illustrates the realization by register 60 pairs of signal values according to preferred form of implementation.At this, by each single position of register 60 mapping signal value.Register 60 is used as the entity of the relevant range in the configuration flow (bit stream) determining FPGA, and the described relevant range that is in operation must change according to desired signal.Therefore, register 60 need not have input.Also the connection with system clock can be implemented alternatively.In force, must realize realizing corresponding signal value with the form of register 60.Alternatively, design hardware description in, namely VHDL describe in, signal value replaces by corresponding register is grand.After realizing initial FPGA and designing, the accurate address of each register-bit of all signal values in FPGA bit stream can be determined by report file and assignment of logical file 23.After loading and driving initial data stream, can change signal value at run duration, wherein the analog value of register 60 is changed by reshuffling of part.Then, reset signal is set, the new value of signal value is activated for changed register.

When using register 60, resource requirement is limited to each register 60 in each position for the signal value that will adjust.Represent that the necessary register 60 of signal value is no longer supplied to user.By using the special Global reset network in FPGA 5, additional reseting network just affects the route possibility that all the other FPGA design indistinctively.Can must being easily determined by the determination operating to change the part of signal value of the configuration data stream of FPGA 5.

Figure 13 illustrates the realization by representing each signal value by the output of look-up table 61 (LUT) according to a kind of alternative form of implementation.Each FPGA processing unit (CLB) comprises multiple look-up table 61, and described look-up table is generally used for realizing any logic function.At this, look-up table 61 is used as the source of signal value, and its logic function can be in operation and be changed by reshuffling of part.

It is in the implementation, responsible in VHDL describes that for signal value, correspondingly the multiple LUT of instantiation is grand respectively.After FPGA implementation procedure, must determine which part of configuration data stream must be operated to operate the content of look-up table 61.So correspondingly change signal value at run duration, its mode is: the corresponding region in the configuration data stream of FPGA 5 is determined and is changed by reshuffling of part.

Figure 14 illustrates the realization by multiplexer 62 pairs of signal values according to another alternative form of implementation.The position of signal value is embodied as the output of multiplexer 62.Two input ends of multiplexer 62 are connected with 0 (S1) and 1 (S2).The position that the selector switch (C) of multiplexer 62 is configured by FPGA controls, to switch between the input of multiplexer 62.In this implementation, must guarantee: signal value realizes with the form of multiplexer 62, and knownly again must can find which position of multiplexer 62 in configuration flow after realization.So correspondingly change signal value at run duration, its mode is: the corresponding region in the configuration data stream of FPGA 5 is determined and is changed by reshuffling of part.

Representing signal value with respect to register 60 or look-up table 61, using less logical resource when utilizing multiplexer 62 to realize signal value.

Figure 15 illustrates according to another form of implementation again by the route implementing signal value to VCC/GND.This is the possibility economized on resources especially realizing signal value.In ConvertBox 63, if each position of signal value is just wired to 0 or 1 connector on the realization of constraint condition form without impact.Each route of signal value can be changed by reshuffling of the part in ConvertBox 63 at run duration, makes to become illustrate by a dotted line 0 from by original 1 shown in solid line, or in contrast.

At run duration by reshuffling the corresponding relevant part that can cover in FPGA 5 to the part of FPGA 5.Signal value (in this case Simulink constant block) is mapped on reconfigurable look-up table 61, register 60 or multiplexer 62.Then, by part, reshuffle signal value changed into arbitrary value dynamically.

The method is embodied as a kind of computer program, and described computer program has computer implemented instruction, and this computer program implements the step of said method after loading in real-time system 3 and implementing.

The control signal that digital memory me provides electronically readable to get, described control signal and real-time system 3 mating reaction, make to implement said method on implementation system 3.

Reference numeral table

Data handling system 1

Computer for controlling 2

Real-time system, data processing equipment 3

Computing node 4

FPGA 5

Functional layer 6

Configuration layer 7

Config memory 8

Memory location 9

FPGA plate 10

Interface 11

Controller 12

FPGA variable mappings file 13

FPGA model 20

CPU model 21

FPGA builds 22

Assignment of logical file 23

FPGA hardware configuration 24

FPGA builds 26

Application program 27

CPU trace file maker 28

CPU trace file 29

FPGA trace file maker 30

FPGA trace file 31

Trace file combiner 33

Complete trace file 33

Block diagram 40

Model.ini document 41

Xilinx system generator 42

Retaking of a year or grade file generated 43

FPGA code, retaking of a year or grade application program 44

Retaking of a year or grade application program source 45

Control software design, control desktop 50

Data acquisition service 51

Register 60

Look-up table 61

Multiplexer 62

ConvertBox 63

Signal XML model 70

Mapped file maker 71

Claims (15)

1., for the method for the signal value changing FPGA (5) that is in operation, comprise the steps:

The FPGA hardware configuration (24) with at least one signal value is loaded on FPGA (5),

At FPGA (5) upper enforcement FPGA hardware configuration (24),

Setting is used for the signal value transferring to FPGA (5),

By described signal value determination write-back,

Described write-back is written in the config memory (8) of described FPGA (5) as status data, and

Status data is transferred to the functional layer (6) of described FPGA (5) from described config memory (8).

2. method according to claim 1, is characterized in that,

Before the functional layer (6) status data being transferred to described FPGA (5) from described config memory (8), the method comprises additional step:

Status data is transferred to from the functional layer (6) of described FPGA (5) in the config memory (8) the configuration layer (7) of described FPGA.

3., according to the method one of the claims 1 or 2 Suo Shu, it is characterized in that,

Comprised by the step of described signal value determination write-back and described signal value is mapped to described write-back.

4., according to the method one of the claims Suo Shu, it is characterized in that,

Described write-back is comprised as the status data step be written in the config memory (8) of FPGA (5) and determines described config memory (8) the status data in the required region of described config memory (8) is write as write-back by the region changed needed for described signal value.

5. according to the method one of the claims Suo Shu, it is characterized in that, by status data from described config memory (8) step be transferred to the functional layer (6) of described FPGA (5) comprise the functional layer (6) determining described FPGA (5) for write described status data needed for part and by the described fractional transmission of described status data in described functional layer (6).

6., according to the method one of the claims Suo Shu, it is characterized in that,

Determine described config memory (8) for the region changed needed for described signal value and/or determine that the comprising for the part needed for the described status data of write of functional layer (6) of described FPGA (5) identifies corresponding region by identification code.

7., according to the method one of the claims Suo Shu, it is characterized in that,

The step that setting is used for the signal value transferring to described FPGA (5) comprises the list of the signal value providing available and select signal value from described list.

8., according to the method one of the claims Suo Shu, it is characterized in that,

Comprise in the upper step implementing FPGA hardware configuration (24) of described FPGA (5) and described hardware configuration (24) is embodied as real-time application, and perform described for changing the method for the signal value of FPGA (5) in the operation of application in real time.

9., according to the method one of the claims Suo Shu, it is characterized in that,

Status data is comprised from described config memory (8) step be transferred to the functional layer (6) of described FPGA (5) reset signal is sent to FPGA (5).

10. method according to claim 9, is characterized in that,

Step reset signal being sent to described FPGA (5) comprises transmission reset signal and is partly transferred to the functional layer (6) of described FPGA (5) from described config memory (8) for by status data.

11. for performing the method for FPGA structure with hardware description language based on FPGA model (20), described method comprises the steps:

Create the FPGA hardware configuration (24) with multiple signal value,

Signalization value in the adjacent region of FPGA hardware configuration (24),

Determine the memory location (9) of config memory (8) for the status data of multiple signal value based on FPGA hardware configuration (24),

Create and there is be in operation signal value that is that can access and/or that can change and the list of memory location (9) corresponded.

12. methods according to claim 11, is characterized in that,

Described method comprises and realizes reset signal for the additional step be transferred to from described config memory (8) by status data the functional layer (6) of described FPGA (5), wherein,

Status data is comprised from the functional layer (6) that described config memory (8) is transferred to described FPGA (5) the adjacent region of status data from the FPGA hardware configuration (24) with signal value is partly transmitted.

13. data processing equipments (3), have processor unit and FPGA, and wherein, described data processing unit is embodied as performing according to the method one of claim 1 to 10 Suo Shu.

14. computer programs, have computer implemented instruction, and described computer program implements the step according to the method one of claim 1 to 10 Suo Shu after loading in suitable data processing equipment (3) and implementing.

15. data-carrier store media, there is the control signal that electronically readable is got, described control signal with data processing equipment (3) mating reaction that can programme, can make in the upper enforcement of described data processing equipment (3) according to the method one of claim 1 to 10 Suo Shu.