CN104979354A - structure and manufacture method of ETOX NOR flash memory - Google Patents
structure and manufacture method of ETOX NOR flash memory Download PDFInfo
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- CN104979354A CN104979354A CN201410128739.0A CN201410128739A CN104979354A CN 104979354 A CN104979354 A CN 104979354A CN 201410128739 A CN201410128739 A CN 201410128739A CN 104979354 A CN104979354 A CN 104979354A
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- SJHPCNCNNSSLPL-CSKARUKUSA-N (4e)-4-(ethoxymethylidene)-2-phenyl-1,3-oxazol-5-one Chemical compound O1C(=O)C(=C/OCC)\N=C1C1=CC=CC=C1 SJHPCNCNNSSLPL-CSKARUKUSA-N 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 230000003647 oxidation Effects 0.000 claims description 50
- 238000007254 oxidation reaction Methods 0.000 claims description 50
- 229920005591 polysilicon Polymers 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 3
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 238000000151 deposition Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 4
- 238000003486 chemical etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Abstract
The invention discloses structure and a manufacture method of an ETOX NOR flash memory. The ETOX NOR flash memory comprises a P-type substrate, a deep N-type well region, a P-type well region, a first trench, a surface channel layer, an inner wall, a tunnel oxide layer, a floating gate, an active region, a polycrystalline silicon interpoly dielectric layer, and a control gate. The deep N-type well region and P-type well region are arranged in the P-type substrate and the P-type well region is arranged over the deep N-type well region. The first trench is arranged in the P-type well region. The surface channel layer is arranged in the P-type well region. The inner wall is arranged on the first trench. The tunnel oxide layer covers the surface of the surface channel layer. The floating gate is arranged on the tunnel oxide layer. The active region is arranged under the tunnel oxide layer. The polycrystalline silicon interpoly dielectric layer is arranged on the floating gate and the control gate is arranged on the polycrystalline silicon interpoly dielectric layer. According to the ETOX NOR flash memory and on the premise that enough long channel of a memory unit is guaranteed, the width of the floating gate is decreased such that the ETOX NOR flash memory can be reduced below 45nm node.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to structure of a kind of ETOX NOR type flash memory and preparation method thereof.
Background technology
ETOX(EPROM with Tunnel Oxide or Erasable Programmable Read OnlyMemory with Tunnel Oxide, erasable programmable read-only register tunnel oxidation layer) NOR(or non-) type flash memory belongs to a kind of non-volatile flash memory, be characterized in that application program can directly be run in flash memory, need not again code be read in system random asccess memory, thus make it have higher efficiency of transmission, therefore, the Application comparison of the type flash memory is extensive.
At present, for ETOX NOR type flash memory, most advanced processing procedure is 45nm node, reason is because the writing mechanism of ETOXNOR type flash memory is HCI(Hot Carrier Injection, hot carrier in jection) effect, but HCI effect needs the raceway groove long enough of corresponding device to ensure source-drain electrode not short circuit, needs the energy accelerating to improve electronics to the electric field that electronics is enough simultaneously, so will make the micro of ETOX NOR type flash memory below 45nm node, be limited to channel length to a great extent.
Fig. 1 is the schematic cross-section of the structure of the ETOX NOR type flash memory of prior art.In the prior art, as shown in Figure 1, floating boom (Floating Gate) 16 be arranged in be formed in P type trap zone (P-Well) 13 surface channel layer 14 above, there is tunnel oxidation layer (Tunnel Oxide) 15 between, and tunnel oxidation layer 15 and floating boom 16 are planar structure.The ETOX NOR type flash memory of this structure can normally work, need the channel length of corresponding memory cell (under this planar structure, the channel length of memory cell equals the width of its floating boom) must 100nm be greater than, namely the width of floating boom also must be greater than 100nm, therefore, the size of this channel length define ETOX NOR type flash memory can only micro to 45nm node, and below micro to 45nm node can not be continued.
Summary of the invention
In view of this, the embodiment of the present invention provides structure of a kind of ETOX NOR type flash memory and preparation method thereof, in the sufficiently long situation of channel length ensureing corresponding memory cell, solve ETOXNOR type flash memory in prior art and can not continue the technical problem of below micro to 45nm node.
First aspect, embodiments provides a kind of structure of ETOX NOR type flash memory, comprising:
P type substrate;
Be arranged in deep n-type well region and the P type trap zone of described P type substrate, wherein, described P type trap zone is positioned on described deep n-type well region;
Be arranged in the first groove of described P type trap zone;
Be arranged in the surface channel layer of described P type trap zone, and lining described first groove inwall and cover the tunnel oxidation layer on surface of described surface channel layer;
Be positioned at the floating boom on described tunnel oxidation layer and the active area under being positioned at described tunnel oxidation layer; And
The control gate being positioned at the inter polysilicon dielectric layer on described floating boom and being positioned on described inter polysilicon dielectric layer.
Further, the degree of depth of described first groove is that 500 dusts are to 2000 dusts.
Further, described P type substrate is P-type silicon substrate.
Further, the material of described tunnel oxidation layer is silicon dioxide.
Second aspect, the embodiment of the present invention additionally provides a kind of manufacture method of structure of ETOX NOR type flash memory, comprising:
One P type substrate is provided;
In described P type substrate, form deep n-type well region and P type trap zone successively, wherein, described P type trap zone is on described deep n-type well region;
Described P type trap zone is etched, forms the first groove;
In described P type trap zone, form surface channel layer, then form tunnel oxidation layer, wherein, described tunnel oxidation layer lining described first groove inwall and cover the surface of described surface channel layer;
On described tunnel oxidation layer, form floating boom successively and be formed with source region under described tunnel oxidation layer; And
Form inter polysilicon dielectric layer and control gate successively on the floating gate.
Further, described P type trap zone is etched, forms the first groove, comprising:
Described P type trap zone forms photoresist layer;
Photoetching is carried out to described photoresist layer, exposed portion P type trap zone;
The part P type trap zone exposed is etched, forms the first groove;
Remove described photoresist layer.
Further, the degree of depth of described first groove is that 500 dusts are to 2000 dusts.
Further, described P type substrate is P-type silicon substrate.
Further, the material of described tunnel oxidation layer is silicon dioxide.
Structure of the ETOX NOR type flash memory that the embodiment of the present invention provides and preparation method thereof, by forming the first groove in P type trap zone, and fill the first groove with the tunnel oxidation layer of follow-up formation and floating boom, tunnel oxidation layer and floating boom is made to define the stereochemical structure different from the planar structure of prior art, and the degree of depth sum making the channel length of the memory cell corresponding to this stereochemical structure imbed the first groove by the width of the floating boom of memory cell and floating boom decides, like this in the sufficiently long situation of channel length ensureing memory cell, the width of the floating boom of memory cell can be reduced, make the width micro of floating boom, thus below ETOXNOR type flash memory micro to 45nm node can be enable.
Accompanying drawing explanation
By reading the detailed description done non-limiting example done with reference to the following drawings, other features, objects and advantages of the present invention will become more obvious:
Fig. 1 is the schematic cross-section of the structure of the ETOX NOR type flash memory of prior art;
Fig. 2 is the schematic cross-section of the structure of a kind of ETOX NOR type flash memory of the embodiment of the present invention one;
Fig. 3 is the flow chart of the manufacture method of the structure of the ETOX NOR type flash memory of the embodiment of the present invention two;
Fig. 4 a-Fig. 4 f is the schematic cross-section of structure corresponding to each stage of the manufacture method of the structure of the ETOX NOR type flash memory of the embodiment of the present invention two;
Fig. 5 a-Fig. 5 c is the schematic cross-section realizing the structure that each stage of step S303 is corresponding in Fig. 3.
The technical characteristic that Reference numeral in figure refers to respectively is:
11, P type substrate; 12, deep n-type well region; 13, P type trap zone; 14, surface channel layer; 15, tunnel oxidation layer; 16, floating boom; 17, inter polysilicon dielectric layer; 18, control gate;
21, P type substrate; 22, deep n-type well region; 23, P type trap zone; 24, surface channel layer; 25, tunnel oxidation layer; 26, floating boom; 27, inter polysilicon dielectric layer; 28, control gate; A, the first groove;
41, P type substrate; 42, deep n-type well region; 43, P type trap zone; 44, surface channel layer; 45, tunnel oxidation layer; 46, floating boom; 47, inter polysilicon dielectric layer; 48, control gate; B, the first groove;
51, photoresist layer.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.Be understandable that, specific embodiment described herein is only for explaining the present invention, but not limitation of the invention.It also should be noted that, for convenience of description, illustrate only part related to the present invention in accompanying drawing but not full content.
Embodiment one
The embodiment of the present invention one provides a kind of structure of ETOX NOR type flash memory.Fig. 2 is the schematic cross-section of the structure of a kind of ETOX NOR type flash memory of the embodiment of the present invention one.As shown in Figure 2, the structure of described ETOX NOR type flash memory comprises: P type substrate (P-Substrate) 21; Be arranged in deep n-type well region (Deep N-Well) 22 and the P type trap zone (P-Well) 23 of described P type substrate 21, wherein, described P type trap zone 23 is positioned on described deep n-type well region 22; Be arranged in the first groove A of described P type trap zone 23; Be arranged in the surface channel layer 24 of described P type trap zone 23, and lining is at described first groove A inwall and the tunnel oxidation layer 25 covering described surface channel layer 24 surface; Be positioned at the floating boom 26 on described tunnel oxidation layer 25 and the active area (not shown in fig. 2) under being positioned at described tunnel oxidation layer 25; And the control gate (Control Gate) 28 being positioned at inter polysilicon dielectric layer on described floating boom 26 (Inter Poly Dielectric is called for short IPD) and being positioned on described inter polysilicon dielectric layer 27.
It should be noted that, in manufacturing process, deep n-type well region 22 and P type trap zone 23 are formed successively in P type substrate 21, and the mode of doping can be adopted to be formed, and wherein, alternatively, P type substrate 21 can be P-type silicon substrate; Then, in P type trap zone 23, the first groove A is formed; After formation first groove A, then form surface channel layer 24 in P type trap zone 23, and surface channel layer 24 also can adopt the mode of doping to be formed.
Particularly, see Fig. 2, because the first groove A is arranged in P type trap zone 23, and tunnel oxidation layer 25 serves as a contrast at the first groove A inwall and covers surface channel layer 24 surface, and floating boom 26 is positioned on tunnel oxidation layer 25, the floating boom 26 formed like this is filled with the remaining space that the first groove A removes its inwall, that is, tunnel oxidation layer 25 in the structure of the ETOX NOR type flash memory of the present embodiment is different from planar structure of the prior art with the structure of floating boom 26, all belongs to stereochemical structure.The channel length of memory cell corresponding to planar structure in prior art is defined by the width of the floating boom of memory cell, but, the degree of depth (floating boom fills the degree of depth of the first groove) sum that the channel length of memory cell corresponding to stereochemical structure in the present embodiment imbeds the first groove by the width of the floating boom of memory cell and floating boom decides, like this when ensureing the channel length long enough (being greater than 100nm) of memory cell, the width of the floating boom of memory cell can be reduced, make the width micro of floating boom, thus below ETOX NOR type flash memory micro to 45nm node can be enable, and change very little to the processing procedure of prior art, only increase once extra chemical etching can complete.
Alternatively, the degree of depth of described first groove A can be that 500 dusts are to 2000 dusts.When processing procedure allows, if the degree of depth of the first groove A is darker, then in the sufficiently long situation of channel length ensureing memory cell, the width of the floating boom of memory cell reduces more, make the width micro of floating boom must be more, thus below ETOX NOR type flash memory easier micro to 45nm node can be enable.
Alternatively, the material of described tunnel oxidation layer 25 can be silicon dioxide.
The structure of the ETOX NOR type flash memory that the embodiment of the present invention one provides, by forming the first groove in P type trap zone, and fill the first groove with the tunnel oxidation layer of follow-up formation and floating boom, tunnel oxidation layer and floating boom is made to define the stereochemical structure different from the planar structure of prior art, and the degree of depth sum making the channel length of the memory cell corresponding to this stereochemical structure imbed the first groove by the width of the floating boom of memory cell and floating boom decides, like this in the sufficiently long situation of channel length ensureing memory cell, the width of the floating boom of memory cell can be reduced, make the width micro of floating boom, thus below ETOX NOR type flash memory micro to 45nm node can be enable.
Embodiment two
The embodiment of the present invention two provides a kind of manufacture method of structure of ETOX NOR type flash memory.Fig. 3 is the flow chart of the manufacture method of the structure of the ETOX NOR type flash memory of the embodiment of the present invention two; The schematic cross-section of the structure that each stage of the manufacture method of the structure of the ETOX NOR type flash memory of Fig. 4 a-Fig. 4 f embodiment of the present invention two is corresponding.As shown in Fig. 3 and Fig. 4 a-Fig. 4 f, the manufacture method of the structure of described ETOX NOR type flash memory comprises:
S301, provide a P type substrate 41.
See Fig. 4 a, provide a P type substrate 41.Alternatively, described P type substrate 41 can be P-type silicon substrate.
S302, in P type substrate 41, form deep n-type well region 42 and P type trap zone 43 successively, wherein, P type trap zone 43 is on deep n-type well region 42.
See Fig. 4 b, form deep n-type well region 42 and P type trap zone 43 in P type substrate 41 successively, wherein, P type trap zone 43 is on deep n-type well region 42.Wherein, deep n-type well region 42 and P type trap zone 43 can be formed successively by carrying out doping to P type substrate 41.
S303, P type trap zone 43 to be etched, form the first groove B.
See Fig. 4 c, P type trap zone 43 is etched, form the first groove B.
Fig. 5 a-Fig. 5 c is the schematic cross-section realizing the structure that each stage of step S303 is corresponding in Fig. 3.Alternatively, see Fig. 5 a-Fig. 5 c, P type trap zone 43 is etched, form the first groove B, specifically can comprise: in described P type trap zone 43, form photoresist layer 51, see Fig. 5 a; Photoetching is carried out, exposed portion P type trap zone 43, see Fig. 5 b to described photoresist layer 51; The part P type trap zone 43 exposed is etched, forms the first groove B, see Fig. 5 c; Remove described photoresist layer 51, the schematic cross-section of corresponding structure as illustrated in fig. 4 c can be obtained.
Alternatively, the degree of depth of described first groove B can be that 500 dusts are to 2000 dusts.
S304, in P type trap zone 43, form surface channel layer 44, then form tunnel oxidation layer 45, wherein, tunnel oxidation layer 45 serve as a contrast the first groove B inwall and cover the surface of surface channel layer 44.
See Fig. 4 d, in P type trap zone 43, form surface channel layer 44, then form tunnel oxidation layer 45, wherein, tunnel oxidation layer 45 serve as a contrast the first groove B inwall and cover the surface of surface channel layer 44.Wherein, surface channel layer 44 can be formed by adulterating to P type trap zone 43; Tunnel oxidation layer 45 can utilize the technology such as deposition well known in the art or epitaxial growth to be formed, wherein, deposition includes but not limited to physical vapour deposition (PVD) (Physical Vapor Deposition, be called for short PVD) or chemical vapour deposition (CVD) (Chemical Vapor Deposition is called for short CVD).
Alternatively, the material of described tunnel oxidation layer 45 can be silicon dioxide.
S305, on tunnel oxidation layer 45, form floating boom 46 and be formed with source region 45 times at tunnel oxidation layer successively.
See Fig. 4 e, on tunnel oxidation layer 45, form floating boom 46 successively and be formed with source region (not shown in figure 4e) for 45 times at tunnel oxidation layer.Wherein, floating boom 46 can be formed by polysilicon.Floating boom 46 can utilize the technology such as deposition well known in the art or epitaxial growth to be formed, and wherein, deposition includes but not limited to physical vapor deposition (PVD) or chemical vapor deposition (CVD).
It should be noted that, in previous step and step S304, tunnel oxidation layer 45 is formed at the inwall of the first groove B and the surface of surface channel layer 44, next, in this step, tunnel oxidation layer 45 is formed floating boom 46, the floating boom 26 of such formation is filled with the remaining space that the first groove B removes its inwall, that is, tunnel oxidation layer 25 in the structure of the ETOX NOR type flash memory that the present embodiment is formed is different from planar structure of the prior art with the structure of floating boom 26, all belongs to stereochemical structure.The channel length of memory cell corresponding to planar structure in prior art is defined by the width of the floating boom of memory cell, but, the degree of depth (floating boom fills the degree of depth of the first groove) sum that the channel length of memory cell corresponding to stereochemical structure in the present embodiment imbeds the first groove by the width of the floating boom of memory cell and floating boom decides, like this when ensureing the channel length long enough (being greater than 100nm) of memory cell, the width of the floating boom of memory cell can be reduced, make the width micro of floating boom, thus below ETOX NOR type flash memory micro to 45nm node can be enable, and change very little to the processing procedure of prior art, only increase once extra chemical etching can complete, specifically refer to Fig. 5 b and Fig. 5 c and relevant description.
Further, when processing procedure allows, if the degree of depth of the first groove B is darker, then in the sufficiently long situation of channel length ensureing memory cell, the width of the floating boom of memory cell reduces more, make the width micro of floating boom must be more, thus below ETOX NOR type flash memory easier micro to 45nm node can be enable.
S306, on floating boom 46, form inter polysilicon dielectric layer 47 and control gate 48 successively.
See Fig. 4 f, floating boom 46 forms inter polysilicon dielectric layer 47 and control gate 48 successively.Wherein, control gate 48 can be formed by polysilicon; Inter polysilicon dielectric layer 47 is used for separating floating boom 46 and control gate 48, and it can be formed, such as silicon oxide-silicon nitride-silicon dioxide by oxidenitride oxide (Oxide-Nitride-Oxide is called for short ONO).Further, inter polysilicon dielectric layer 47 and control gate 48 can utilize the technology such as deposition well known in the art or epitaxial growth to be formed, and wherein, deposition includes but not limited to physical vapor deposition (PVD) or chemical vapor deposition (CVD).
The manufacture method of the structure of the ETOX NOR type flash memory that the embodiment of the present invention two provides, by forming the first groove in P type trap zone, and fill the first groove with the tunnel oxidation layer of follow-up formation and floating boom, tunnel oxidation layer and floating boom is made to define the stereochemical structure different from the planar structure of prior art, and the degree of depth sum making the channel length of the memory cell corresponding to this stereochemical structure imbed the first groove by the width of the floating boom of memory cell and floating boom decides, like this in the sufficiently long situation of channel length ensureing memory cell, the width of the floating boom of memory cell can be reduced, make the width micro of floating boom, thus below ETOX NOR type flash memory micro to 45nm node can be enable.
Note, above are only preferred embodiment of the present invention and institute's application technology principle.Skilled person in the art will appreciate that and the invention is not restricted to specific embodiment described here, various obvious change can be carried out for a person skilled in the art, readjust and substitute and can not protection scope of the present invention be departed from.Therefore, although be described in further detail invention has been by above embodiment, the present invention is not limited only to above embodiment, when not departing from the present invention's design, can also comprise other Equivalent embodiments more, and scope of the present invention is determined by appended right.
Claims (9)
1. a structure for ETOX NOR type flash memory, is characterized in that, comprising:
P type substrate;
Be arranged in deep n-type well region and the P type trap zone of described P type substrate, wherein, described P type trap zone is positioned on described deep n-type well region;
Be arranged in the first groove of described P type trap zone;
Be arranged in the surface channel layer of described P type trap zone, and lining described first groove inwall and cover the tunnel oxidation layer on surface of described surface channel layer;
Be positioned at the floating boom on described tunnel oxidation layer and the active area under being positioned at described tunnel oxidation layer; And
The control gate being positioned at the inter polysilicon dielectric layer on described floating boom and being positioned on described inter polysilicon dielectric layer.
2. the structure of ETOX NOR type flash memory according to claim 1, is characterized in that, the degree of depth of described first groove is that 500 dusts are to 2000 dusts.
3. the structure of ETOX NOR type flash memory according to claim 1, it is characterized in that, described P type substrate is P-type silicon substrate.
4. the structure of ETOX NOR type flash memory according to claim 1, is characterized in that, the material of described tunnel oxidation layer is silicon dioxide.
5. a manufacture method for the structure of ETOX NOR type flash memory, is characterized in that, comprising:
One P type substrate is provided;
In described P type substrate, form deep n-type well region and P type trap zone successively, wherein, described P type trap zone is on described deep n-type well region;
Described P type trap zone is etched, forms the first groove;
In described P type trap zone, form surface channel layer, then form tunnel oxidation layer, wherein, described tunnel oxidation layer lining described first groove inwall and cover the surface of described surface channel layer;
On described tunnel oxidation layer, form floating boom successively and be formed with source region under described tunnel oxidation layer; And
Form inter polysilicon dielectric layer and control gate successively on the floating gate.
6. the manufacture method of the structure of ETOX NOR type flash memory according to claim 5, is characterized in that, etch described P type trap zone, form the first groove, comprising:
Described P type trap zone forms photoresist layer;
Photoetching is carried out to described photoresist layer, exposed portion P type trap zone;
The part P type trap zone exposed is etched, forms the first groove;
Remove described photoresist layer.
7. the manufacture method of the structure of the ETOX NOR type flash memory according to any one of claim 5-6, is characterized in that, the degree of depth of described first groove is that 500 dusts are to 2000 dusts.
8. the manufacture method of the structure of ETOX NOR type flash memory according to claim 5, it is characterized in that, described P type substrate is P-type silicon substrate.
9. the manufacture method of the structure of ETOX NOR type flash memory according to claim 5, is characterized in that, the material of described tunnel oxidation layer is silicon dioxide.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110277393A (en) * | 2019-06-19 | 2019-09-24 | 上海华力微电子有限公司 | Flash memory and its manufacturing method |
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| CN1254189A (en) * | 1998-11-16 | 2000-05-24 | 世大积体电路股份有限公司 | Low-voltage high-speed store unit and its making method |
| US20040266135A1 (en) * | 2003-06-30 | 2004-12-30 | Dong Cha Deok | Method for forming floating gate in flash memory device |
| CN1677648A (en) * | 2004-03-29 | 2005-10-05 | 力晶半导体股份有限公司 | Structure of non-volatile memory and its making method |
| CN1787218A (en) * | 2004-12-08 | 2006-06-14 | 三星电子株式会社 | Nonvolatile memory device and method of manufacturing the same |
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2014
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1254189A (en) * | 1998-11-16 | 2000-05-24 | 世大积体电路股份有限公司 | Low-voltage high-speed store unit and its making method |
| US20040266135A1 (en) * | 2003-06-30 | 2004-12-30 | Dong Cha Deok | Method for forming floating gate in flash memory device |
| CN1677648A (en) * | 2004-03-29 | 2005-10-05 | 力晶半导体股份有限公司 | Structure of non-volatile memory and its making method |
| CN1787218A (en) * | 2004-12-08 | 2006-06-14 | 三星电子株式会社 | Nonvolatile memory device and method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110277393A (en) * | 2019-06-19 | 2019-09-24 | 上海华力微电子有限公司 | Flash memory and its manufacturing method |
| US11374014B2 (en) | 2019-06-19 | 2022-06-28 | Shanghai Huali Microelectronics Corporation | Flash with shallow trench in channel region and method for manufacturing the same |
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