CN104953824B - DC/DC converters - Google Patents
DC/DC converters Download PDFInfo
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- CN104953824B CN104953824B CN201410114285.1A CN201410114285A CN104953824B CN 104953824 B CN104953824 B CN 104953824B CN 201410114285 A CN201410114285 A CN 201410114285A CN 104953824 B CN104953824 B CN 104953824B
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Abstract
The present invention provides DC/DC converters, it generates underloading signal to the 2nd error signal compared with defined threshold value.Generation represents the zero cross signal of situation about terminating during the regeneration of inductor.When exporting underloading signal and zero cross signal, intermitten enabling signal is being exported after the time as defined in the 1st and is carrying out intermitten.At this time, big time constant when low-pass filter is switched to than operating stably.In intermitten, during continue for during zero cross signal is not exported as defined in the 2nd and when the 2nd error amplification signal is less than threshold value, end switch element, when the 2nd error amplification signal becomes more than threshold value, make switching elements conductive.When switch element ends, overlapping pulses and make the 1st error signal decline as defined in the time.Moreover, in the case where output voltage is lower than defined value, low-pass filter is switched to the small time constant identical with during operating stably.
Description
Technical field
The present invention relates to DC/DC converters.
Background technology
As the method for the voltage for generating the stabilization lower than input voltage, the buck chopper for being widely used for nonisulated type is electric
Road.But due to as it is standby when etc. become underloading in the case of also continue with switch motion, underloading electricity
Source transfer efficiency is lower.
Invention to solve this problem, it is proposed that the DC/DC converters shown in Figure 11（Patent document 1）.By error signal COMP
Be compared to detection underloading with defined threshold value Vsk_Lo, error signal COMP be to voltage FB and reference voltage V ref into
What row relatively generated, voltage FB is to output voltage V by resistance Rfb1 and resistance Rfb2outObtained from being split.
When as at light load, since voltage FB rises, the error signal COMP exported from error amplifier 14 declines.Therefore, when
When error signal COMP drops to lower than threshold value Vsk_Lo, light condition is judged as YES.At this time, threshold value Vsk_Lo is switched to compare
The Vsk_Hi of Vsk_Lo high.
In steady load, set is carried out to PWM latch 2 by the output of oscillator 1, by high-side driver 4 come
Turn on high-end MOSFET8.By PWM comparators 17 to superior MCU signal VtripCompared with error signal COMP
Compared with as superior MCU signal VtripDuring more than error signal COMP, reset trigger 2 and end high-end MOSFET8,
Wherein, superior MCU signal VtripElectric current I with flowing through high-end MOSFET8DHIt is proportional.In addition, low side MOSFET21
Turn on when high-end MOSFET8 ends, end when high-end MOSFET8 conductings or zero cross detection circuit 22 detect zero passage.
Situation about terminating during regeneration of the zero cross detection circuit 22 to inductor 9 is detected.
When being judged as YES at light load, the output SKIP of underloading detection comparator 23 becomes high level, therefore on oscillator 2
Signal, being output into for inverter 18 be low（low）, signal is not transferred to high-end MOSFET8.As output voltage VoutDecline
And error signal COMP, when exceeding threshold value Vsk_Hi, the output SKIP of underloading detection comparator 23 becomes low level, inverter 18
High-side driver 4 is delivered to as the signal of high level, therefore oscillator 2, turns on high-end MOSFET8.In addition, low side
MOSFET21 is turned on when high-end MOSFET8 ends, and zero passage is detected in high-end MOSFET8 conductings or zero cross detection circuit 22
When end.By the above process repeatedly, intermitten is being repeated at light load.Detected at light load when as described above, it is high-end
MOSFET8 prevents the output of oscillator 2 and cannot be turned on by the output of oscillator 2, therefore frequency declines, and can reduce high-end
The gate drive current of MOSFET8 and low side MOSFET21 and improve efficiency.
In patent document, as the motion in reduction on-off times at light load, it is proposed that following content：In voltage-dropping type
In chopper, make voltage amplitude as defined in the 2nd threshold value to hot side offset at light load, wherein, which is
Act as follows：Output voltage is being detected by hysteresis comparator, is being made out when the voltage detected is 1 threshold value
Element cut-off is closed, when the voltage detected is 2 threshold value smaller than the 1st threshold value, makes switching elements conductive.
Patent document 1：No. 5481178 publications of United States Patent (USP)
Patent document 2：Japanese Unexamined Patent Publication 2007-020352 publications
But in patent document 1, as the 1st problem, due in PWM comparators 17 there are transmission delay, i.e.,
Make superior MCU signal VtripReach error amplification signal COMP, reset signal rapidly can not be output to PWM locks
Storage 2 and end high-end MOSFET8.Therefore, error amplification signal COMP is previously controlled as the voltage lower than target level.
Since the transmission delay is constant, as depicted in fig. 13 a, in output voltage VoutBigger condition（Input voltage VinWith output
Voltage VoutBetween voltage difference it is small）Under, during the conducting of high-end MOSFET8（High-side current inspection is outputed corresponding to Figure 13 a
Survey signal VtripDuring）Fully grown relative to transmission delay Δ T, therefore will not especially become problem.
But in output voltage VoutThe smaller condition of setting（Input voltage VinWith output voltage VoutBetween electricity
Pressure difference is big）Under, during the conducting of high-end MOSFET8（Superior MCU signal V is outputed corresponding to Figure 13 btripPhase
Between）Shorten, it is impossible to ignore the influence of transmission delay, error amplification signal COMP is controlled as the electricity more much smaller than target level
Pressure.Carried out compared with underloading detection comparator 23 detects the 1st threshold value Vsk_Lo to error amplification signal COMP with underloading
Underloading detects, and accordingly, there exist following problem：In output voltage VoutUnder conditions of small, the current level that underloading judges is (light
Carry detection threshold value) become bigger, also carrying out intermittent oscillation in the original heavily loaded region for wanting to carry out stable oscillation stationary vibration action moves
Make.
In addition, as the 2nd problem, when the high-end MOSFET8 conductings during intermittent oscillation, due to output voltage VoutOn
Rise, the voltage difference increase between FB terminal voltages and voltage Vref, therefore error amplification signal COMP declines, underloading detection signal
SKIP is changed to height from undercut again, stops the action of high-end MOSFET8 and low side MOSFET21.But in fact, in error
There are operating lag in amplified signal COMP, error amplification signal COMP cannot rapidly be less than underloading and detect the 1st threshold value, therefore
As shown in figure 12, multiple switching action is carried out within an intermittent oscillation cycle sometimes.At this time, output voltage V is overlappedoutOn
Ripple voltage become larger, be accompanied by this, be further elongated during the cut-off of intermittent oscillation.Therefore, intermittent oscillation frequency compares the mankind
Audible range（Below 20kHz）It is low, when having used ceramic capacitor as output capacitor 10, exist because of its piezoelectric effect and
The problem of producing sound.
In addition, as the 3rd problem, there are the following problems：Due to enter intermittent oscillation action load current with from
There is no difference between current between the load current that intermittent oscillation action departs from, therefore become not in the load area of Near Threshold, action
Stablize.
For patent document 2, although above-mentioned 2nd problem can be reduced, the 1st and the 3rd problem cannot be solved the problems, such as.
The content of the invention
It is an object of the present invention to provide following DC/DC converters：Under conditions of output voltage is small, also can
It is enough not increase underloading detection threshold value and forbid carrying out intermittent oscillation action in the region of heavy duty.
To solve the above-mentioned problems, DC/DC converters of the invention, it makes out according to the drive signal that control circuit generates
Element conductive cut-off is closed, so that the 1st DC voltage is converted to the 2nd DC voltage, which is characterized in that, control
Circuit processed has：Oscillator, the pulse of frequency as defined in its output；Error amplifier, it is to the 2nd DC voltage and benchmark
Error between voltage is amplified and exports the 1st error amplification signal；Low-pass filter circuit, it, which has, is used for adjustment time
The adjustment element of constant, inputs the 1st error amplification signal and generates the 2nd error amplification signal；Current detection circuit, it is to flowing through
The electric current of switch element is detected and output current signal；Current comparator, it is to the 2nd error amplification signal and current signal
It is compared, the reset signal for being used for ending switch element is exported according to output is compared；Zero cross detection circuit, in inductor
Regeneration during at the end of, zero cross detection circuit output zero cross signal, wherein, the inductor and switch element and the 2nd direct current
The lead-out terminal connection of voltage；Underloading detection circuit, it exports the 2nd error amplification signal in underloading letter compared with threshold value
Number；Timer circuit, when output underloading signal and zero cross signal, after the time as defined in the 1st, the timer is electric
Road exports intermitten enabling signal, in the case of during continue for as defined in the 2nd during not exporting zero cross signal, the meter
When device circuit output intermitten disable signal；ON-OFF control portion, intermitten license letter is outputed in timer circuit
In a period of number, when the 2nd error amplification signal is less than threshold value, which end switch element, in timing
In a period of device circuit output intermitten enabling signal, when the 2nd error amplification signal is more than threshold value, the turn-on deadline
Control unit makes switching elements conductive；Voltage superposing circuit, it is connected with the input terminal of error amplifier, defeated in timer circuit
In a period of having gone out intermitten enabling signal, when outputing reset signal from current comparator, the input to error amplifier
The voltage signal of time as defined in terminal is overlapping；And voltage detecting circuit, it declines the 2nd DC voltage must be than defined electricity
Situation about forcing down is detected, the 2nd DC voltage decline must be lower than defined voltage when, low-pass filter circuit adjustment member
Part receives the signal from voltage detecting circuit, is adjusted in a manner of the time constant of low-pass filter diminishes.
Moreover, in defined voltage reduction described in the 2nd DirectCurrent Voltage Ratio, voltage superposing circuit is received from described
The signal of voltage detecting circuit, forbids the input terminal overlapping voltage signal to the error amplifier.
According to the present invention, timer circuit is according to the underloading signal from underloading detection circuit and from zero cross detection circuit
Zero cross signal, by after the defined time, exporting intermitten enabling signal, being held during zero cross signal is not exported
In the case of having continued defined period, intermitten disable signal is exported.Moreover, when voltage as defined in the 2nd DirectCurrent Voltage Ratio is low
When lower, adjustment element is adjusted in a manner of the time constant of low-pass filter diminishes, therefore the state in load from underloading
Sharp increase and the 2nd DC voltage can export intermitten disable signal immediately and suppress the 2nd DC voltage when declining
Decline.
Brief description of the drawings
Fig. 1 is the circuit structure diagram of the DC/DC converters of the embodiment of the present invention 1.
Fig. 2 is the detailed circuit structure diagram of the zero cross detection circuit of the DC/DC converters of the embodiment of the present invention 1.
Fig. 3 is the detailed circuit structure diagram of the timer circuit of the DC/DC converters of the embodiment 1 of invention.
Fig. 4 is the sequence diagram for illustrating the action of each several part of the DC/DC converters of the embodiment of the present invention 1.
Fig. 5 is to be shown in existing DC/DC converters for output voltage only by error amplification signal detection come really
The figure of fixed underloading detection threshold value.
Fig. 6 is to show to take out for output voltage in the DC/DC converters of the embodiment of the present invention 1 to amplify by error
Signal detection carrys out definite threshold value and by zero passage detection come the figure of the underloading detection threshold value of the logical AND between definite threshold value.
Fig. 7 is the sequence diagram for illustrating the action of each several part of the DC/DC converters of the embodiment of the present invention 1.
Fig. 8 is the sequence diagram for illustrating the action of each several part of the DC/DC converters of the embodiment of the present invention 1.
Fig. 9 is the circuit structure diagram of the DC/DC converters of the embodiment of the present invention 2.
Figure 10 is the sequence diagram for illustrating the action of each several part of the DC/DC converters of the embodiment of the present invention 2.
Figure 11 is the circuit structure diagram of existing DC/DC converters.
Figure 12 is the sequence diagram for illustrating the action of each several part of existing DC/DC converters.
Figure 13 a and Figure 13 b are the voltage differences illustrated in existing DC/DC converters between input voltage and output voltage
The figure for the problem of underloading detection threshold value suddenly rises when big.
Label declaration
1 oscillator
2 set-reset flip-floops
3rd, 273,274 logical AND circuit
4 high-side drivers
5 driving REG circuits
6 anti-backflow diodes
7 boottrap capacitors
8 high-end MOSFET
9 inductors
10 output capacitors
11 output loadings
12nd, 13 feedback resistance
14 error amplifiers
15 phase compensation resistance
16 phase compensation capacitors
17 PWM comparators
18 inverters
19 logic NOR circuits
20 low-end drivers
21 low side MOSFET
22 zero cross detection circuits
23 underloading detection comparators
27 intermittent oscillation control circuits
271 low-pass filter circuits
272 timer circuits
273rd, 274 logical AND circuit
275 single-shot trigger circuits
276th, 2713 switch
2711 filter resistances
2712 filter capacitors
IrippleCurrent source
Ibias1、Ibias2Constant-current source
Embodiment
Hereinafter, several embodiments of the DC/DC converters of the present invention are described in detail referring to the drawings.First, it is right
The summary of the present invention illustrates.
In the prior art, by being compared to have detected underloading to error amplification signal and threshold value, and in contrast,
In the present invention, the detection that error amplification signal carries out and the discontinuous zero cross detection circuit of detection inductor current will be utilized
It is combined to detection underloading.
I.e., in the present invention, error amplification signal is passed through low-pass filter to generate the 2nd error signal, pass through combination
Underloading detection comparator and zero cross detection circuit, in output voltage VoutBe worth it is smaller under conditions of carry out using zero passage detection
Underloading detects, in output voltage VoutBe worth it is bigger under conditions of, underloading detection is carried out by underloading detection comparator, wherein,
The underloading detection comparator is by carrying out the comparison of underloading detection compared with underloading detection threshold value to the 2nd error signal
Device, the zero cross detection circuit are the circuits that situation about terminating during the regeneration to inductor is detected.When detecting at light load,
At the end of during the conducting of intermittent oscillation, ripple is temporarily overlapped on FB voltages so that error amplification signal instantaneously under
Drop.Moreover, low-pass filter has the adjustment element being adjusted to time constant, when load sharp increases from the state of underloading
Add and the 2nd DC voltage decline when, reduce time constant and suppress the decline of the 2nd DC voltage.
Therefore, in the present invention, it can prevent high-end MOSFET from continuously carrying out switch motion and by an intermittent oscillation
On-off times in during action are suppressed to once, also, are worked as from voltage detecting circuit and detected output voltage VoutThe feelings of decline
Intermittent oscillation action is instantaneously stopped during condition, therefore can suppress to decline to voltage during load offer.
In addition, in the present invention, be configured to, by underloading detection threshold value with the 1st threshold value, the 2nd threshold value and the 3rd threshold value this three rank
Section switches over, when being transferred to intermitten from stable oscillation stationary vibration action, the underloading detection threshold value selection of underloading detection comparator
1st threshold value produces magnetic hysteresis, when being transferred to stable oscillation stationary vibration action from intermittent oscillation action, the underloading inspection of underloading detection comparator
Threshold value selection voltage level 2nd threshold value bigger than the 1st threshold value or the 3rd threshold value are surveyed to produce magnetic hysteresis, so as to release underloading inspection
Survey the unstable action of Near Threshold.
Then, illustrated using the specific embodiment of DC/DC converters as characterized above as illustration.
【Embodiment 1】
Fig. 1 is the circuit structure diagram of the DC/DC converters of the embodiment of the present invention 1.Fig. 2 is the embodiment of the present invention 1
The detailed circuit structure diagram of the zero cross detection circuit of DC/DC converters.Fig. 3 is the DC/DC converters of the embodiment 1 of invention
The detailed circuit structure diagram of timer circuit.
The DC/DC converters of embodiment 1 are following DC/DC converters：According to control circuit generate drive signal come
End switching elements conductive, so that the 1st DC voltage is converted to the 2nd DC voltage.
Oscillator 1 exports the pulse of defined frequency.Error amplifier 14 is to output voltage VoutWith reference voltage V ref it
Between error be amplified and output error amplified signal COMP1.Inductor 9 and be made of switch element MOSFET8,9 and
Output voltage VoutLead-out terminal connection.Zero cross detection circuit 22 during the regeneration of inductor 9 at the end of export zero passage letter
Number.Error amplification signal COMP1 is converted to the 2nd error signal COMP2 by low-pass filter circuit 271.Underloading detection comparator
23 export underloading signal according to the error amplification signal from error amplifier 14.
The DC/DC converters of embodiment 1 are characterized in that, relative to the knot of the existing DC/DC converters shown in Figure 11
Structure is further provided with the intermittent oscillation control circuit 27 for controlling interval oscillation action.
Intermittent oscillation control circuit 27 is configured to, and has：By filter resistance 2711, filter capacitor 2712, switch
2713 and the low-pass filter circuit 271 that forms of logic or circuit 2714；Timer 272；Logical AND circuit 273；Logical AND electricity
Road 274；Single-shot trigger circuit 275；Switch 276；And current source Iripple。
Timer circuit 272 is according to the underloading signal from underloading detection comparator 23 and from zero cross detection circuit 22
Zero cross signal, after by the defined time, exports intermitten enabling signal, continues during zero cross signal is not exported
In the case of defined period, intermitten disable signal is exported.Moreover, to output voltage VoutThe situation of decline is examined
Survey and stop intermitten disable signal.
Logical AND circuit 273, inverter 18 and logical AND circuit 3（ON-OFF control portion）, in timer circuit 272
In a period of outputing intermitten enabling signal, end MOSFET8 when error amplification signal is less than threshold value, in timer
In a period of circuit 272 outputs intermitten enabling signal, when error amplification signal at least becomes more than threshold value, make
MOSFET8 is turned on.
Low-pass filter circuit 271 has the adjustment element for adjustment time constant, by adjustment element according to the 1st error
Amplified signal COMP1 generates the 2nd error amplification signal COMP2.Filter resistance 2711, filter capacitor 2712 and switch 2713
Form adjustment element.
PWM comparators 17（Current comparator）To the 2nd error amplification signal COMP2 and the high-side current for flowing through MOSFET8
Detect signal VtripIt is compared, and will be tactile for being output to the reset signal RESET that MOSFET8 ends according to output is compared
Send out the reseting terminal R of device 2.Logical AND circuit 274 takes out the reset signal RESET from PWM comparators 17 and comes from timer
Logical AND between the signal of circuit 272, is output to single-shot trigger circuit 275.Single-shot trigger circuit 275 is according to from logical AND circuit
274 output and generate ono shot pulse, and be output to switch 276, logic or circuit 2714.
Current source Iripple（Voltage superposing circuit）Reversed input terminal via switch 276 with error amplifier 14 connects
Connect.In a period of timer circuit 272 outputs intermitten enabling signal, reset letter is being outputed from PWM comparators 17
Number when, current source IrippleTo the reversed input terminal overlapping defined time of error amplifier 14（During ono shot pulse）'s
Voltage signal.
It is multiple being outputed from PWM comparators 17 in a period of timer circuit 272 outputs intermitten enabling signal
During the signal of position, or when timer circuit 272 detects the situation that the 2nd DC voltage declines, low-pass filter circuit 271 makes
The conducting of switch 2713, so that time constant is smaller than defined time constant.
On current source Iripple, end switch 276 after by the defined time, so as to forbid voltage signal
It is overlapping.On low-pass filter circuit 271, end switch 2713 after by the defined time, so that time constant
It is bigger than defined time constant.
Then, with reference to the sequence diagram of Fig. 4, during to steady load（Iout>Iskip_in）Region action illustrate.
By feedback resistance 12 and feedback resistance 13 to output voltage VoutCarry out partial pressure, generation feedback voltage FB.Feedback electricity
Pressure FB is input into the reversed input terminal of error amplifier 14, the input reference voltage Vref in non-inverting input terminal.By mistake
Poor amplifier 14 produces the 1st error amplification signal COMP1 between feedback voltage FB and reference voltage V ref and is output to low pass
Wave filter 271.
In the state of steady load, due to the 1st threshold value Vtm_Lo be set to it is lower than the 2nd error amplification signal COMP2,
Therefore SKIP_OK signals, the closure of switch 2713 are not exported from timer circuit.Therefore, the attenuation characteristic of low-pass filter 271 becomes
Weak, the 2nd error amplification signal COMP2 becomes the voltage roughly equal with the 1st error amplification signal COMP1 signals, is input to PWM
The reversed input terminal of comparator 17 and the reversed input terminal of underloading detection comparator 23.In the non-of underloading detection comparator 23
Underloading detection threshold value Vsk_Lo is inputted in anti-phase input, in the case where output current Iout is fully big, becomes COMP2>Vsk_
Lo, therefore the output signal SKIP1 of underloading detection comparator 23 becomes low level.Therefore, by logical AND circuit 273 to inversion
The input of device circuit 18 and export low level SKIP2 signals.Therefore, the output of PWM latch 2 is delivered to high-end drive circuit
4, intermittent oscillation action becomes illegal state.
Constant-current source I is connected with oscillator 1bias2, according to constant-current source Ibias2And set pulse is generated, it is output to PWM locks
The set terminal of storage 2.
Constant-current source I is connected with driving REG circuits 5bias1, driving REG circuits 5 are via low-side driver circuitry 20 and prevent
Counter-current diode 6 supplies driving voltage to high-end drive circuit 4.
When PWM latch 2 becomes SM set mode, high-side driver 4 is driven by logical AND circuit 3, so that high-end
MOSFET8 is turned on.At this time, SW terminal voltages rise to input voltage VinNeighbouring voltage, corresponding to SW terminals and Vout terminals
The electric current IDH of voltage difference flow through inductor 9, so as to carry out energy supply to output capacitor 10 and output loading 11.
On the other hand, the drain current having with high-end MOSFET8 is inputted in the non-inverting input terminal of PWM comparators 17
IDHIn the superior MCU signal V of ratiotrip, during the conducting of high-end MOSFET8, as superior MCU signal Vtrip
During as more than the 2nd error amplification signal COMP2, reset signal RESET is exported to PWM latch 2.When PWM latch 2 becomes
During reset state, end high-side driver 4 by logical AND circuit 3, and low side is driven by logic NOR circuit 19
Device 20 turns on.Thus, high-end MOSFET8 is switched to cut-off from conducting, and low side MOSFET21 is switched to conducting from cut-off, so that
The regenerative current IDL produced in inductor 9 is flowed through from the source electrode of low side MOS21 by drain electrode.
In a period of the cycle of oscillation determined by oscillator 1, connect in the electric current that the regeneration for carrying out inductor 9 is not over
In the case of continuous action, PWM latch 2 becomes SM set mode, low side MOSFET21 cut-offs again by the signal of oscillator 1
And high-end MOSFET8 conductings.
The action of above series of is repeated, so as to carry out buck chopper action.
Then, with reference to Fig. 4 to being transferred to underloading from steady load（Iout=Iskip_in）When action illustrate.
When Iout declines, the 1st error amplification signal COMP1 and the 2nd error amplification COMP2 decline, therefore with high-end
The mode that the peak value of the drain current IDH of MOSFET diminishes is controlled.Underloading detection comparator 23 is to the 2nd error amplification signal
COMP2 is compared with the 1st underloading detection threshold value Vsk_Lo, and in moment t1, as the 2nd error amplification signal COMP2, to be less than the 1st light
When carrying detection threshold value Vsk_Lo, the 1st underloading detection signal SKIP1 changes to height from undercut, to logical AND circuit 273 and timer electricity
The supply of road 272 represents the signal of light condition.
Afterwards, Iout further declines, and does not connect when the valley point current of inductor current IL reaches zero ampere-hour progress electric current
Continuous action.At this time, the polarity of SW terminal voltages is switched to just from negative.As shown in Fig. 2, in zero cross detection circuit 22, pass through ratio
Compared with the change in polarity that device 221 detects SW terminal voltages, set-reset flip-floop 222 is set to be in SM set mode.Thus, logic or non-electrical are passed through
Road 19 and low-end driver 20 end low side MOSFET21, while timer circuit 272 is exported and represents zero passage detection state
Signal.
In timer circuit 272, in moment t2, all become when the 1st underloading detects signal SKIP1 and zero cross signal ZERO
Gao Shi, as shown in figure 3, set-reset flip-floop 2722 becomes SM set mode due to logical AND circuit 2721, turns on switch 2723.In
It is to end switch 2725 by inverter 2724, so as to make capacitor 2726 discharge by constant-current source Idis.
Compared with comparator 2727 permits the 1st threshold value Vtm_Lo to the current potential TM of capacitor 2726 with intermittent oscillation,
Moment t3, the current potential TM of capacitor 2726 reach the 1st threshold value Vtm_Lo.Then, believe with intermittent oscillation enabling signal SKIP-OK
Number from undercut change to high while, the 1st threshold value Vtm_Lo is switched to voltage level 2nd threshold value bigger than the 1st threshold value Vtm_Lo
Vtm_Hi.Thus, it is switched to the pattern of license intermittent oscillation action.At this time, by the underloading detection threshold of underloading detection comparator 23
Value is switched to the voltage level 3rd threshold value Vsk_Hi bigger than the 1st threshold value Vsk_Lo.
As described above, the SKIP1 from underloading detection comparator 23 is taken out by logical AND circuit 2721 and comes from zero passage
Logical AND between the zero cross signal ZERO of detection circuit 22, therefore as shown in figure 4, in output voltage VoutIt is worth smaller bar
Under part, compared to underloading detection comparator 23, underloading detection threshold value Iskip-in is preferentially determined by zero cross detection circuit 22.When
If the inductor value of inductor 9 is L, stable oscillation stationary vibration frequency is Fsw, underloading detection threshold value Iskip-in at this time by
Iskip_in=Vout（Vin-Vout）/（2·L·Vin·Fsw）
Represent, in output voltage VoutUnder conditions of smaller, Iskip-in is being set as the longitudinal axis, output voltage VoutFor transverse axis
When, as shown in figure 5, the characteristic as parabolic shape.
On the other hand, in output voltage VoutBigger region, Iskip-in level is by existing underloading detection comparator
23 preferentially determine.It is as shown in Figure 6 when illustrating the state.Therefore, it is possible to solve in the output voltage V shown in Figure 13outIt is small
Region in the existing issues that become larger of Iskip-in.In addition, even in output voltage VoutIn big region, it can also prevent
Iskip-in becomes situation too much, can realize output voltage VoutThe small underloading detection operation of dependence.
Then, with reference to Fig. 4 to during intermittent oscillation at light load（Iout<Iskip_in）Action illustrate.
When SKIP-OK signals become it is high when, being output into for logic or circuit 2714 is low, ends switch 2713.Moreover,
In the state of SKIP-OK signals is high and license intermittent oscillations, in logical AND circuit 273, signal is detected in the 1st underloading
SKIP1 for it is high when, it is high to the detection signal SKIP2 output of the 2nd underloading, so as to by inverter 18, logical AND circuit 3 and
End to high-side driver semi-finals high-end MOSFET8.Afterwards, in moment t3, when zero cross detection circuit 22 detects inductor
Terminate during 9 regeneration, zero cross signal ZERO from undercut change to high when, made by logic NOR circuit 19 and low-end driver 20
Low side MOSFET21 ends.
Afterwards, when in during the switch motion of intermittent oscillation stops, the electric charge of output capacitor 10 passes through output current
Iout and when discharging, output voltage VoutSomewhat decline, when the potential difference between FB terminals and Vref becomes larger, due to the 1st error
Amplify voltage signal COMP1 to rise, therefore the 2nd error amplification signal COMP2 also rises.
In moment t4, when the 2nd error amplification signal COMP2 becomes more than the 3rd underloading threshold value Vsk_Hi, underloading detection ratio
The 1st underloading detection signal SKIP1 switched from high to compared with device 23 it is low, so that the 2nd underloading detection signal SKIP2 also be switched from height
To low, the voltage level of underloading detection threshold value is smaller than Vsk_Hi, is switched to the 2nd underloading threshold value Vsk_Md bigger than Vsk_Lo.This
When, the output of inverter 18 is changed into height from undercut, so as to start the switch of MOSFET8 by signal that oscillator 1 exports
Action.
Afterwards, when the drain current IDH risings of high-end MOSFET8, in moment t5, superior MCU signal VtripReach
During the 2nd error amplification signal COMP2, PWM comparators 17 export reset signal to PWM latch 2, so that high-end MOSFET8
Cut-off.At this time, reset signal RESET2 is also supplied with to single-shot trigger circuit 275 by logical AND circuit 274.
In single-shot trigger circuit 275, receive reset signal RESET2 and in defined period（Moment t6~t7）It is interior to incite somebody to action
Ripple_ON signals change to height from undercut.Thus, due to the conducting of switch 276, constant current IrippleIt is fed into FB terminals, FB
Terminal voltage instantaneously rises.Moreover, on the opportunity, the output of logic or circuit 2714 is become by Ripple_ON signals
Height simultaneously turns on switch 2713, so that the time constant of low-pass filter 271 diminishes and weakens attenuating.
When FB terminal voltages rapidly rise, since the voltage difference between Vref becomes larger, error amplifier 14 makes
1st error amplification signal COMP1 instantaneously declines, and the 2nd error amplification signal COMP2 also declines therewith（Moment t6~t7）.
When the 2nd error amplification signal COMP2 declines and reaches underloading detection threshold value Vsk_Md, underloading detection circuit 23 is again
It is secondary that 1st underloading detection signal SKIP1 is changed into height from undercut, will be light while the switch motion of high-end MOSFET8 is stopped
Carry detection threshold value and be switched to Vsk_Hi.
During as defined in process（Moment t6~t7）Afterwards, single-shot trigger circuit 275 switches Ripple_ON signals from height
To low, end switch 276.At this time, in moment t8~t9, overshoot, underloading inspection are produced in the 1st error amplification signal COMP1
Slowdown monitoring circuit 23 is possible to cause error detection.Therefore, end switch 2713 by logic or circuit 2714, so that low-pass filtering
The time constant of device 271 increases and improves attenuation characteristic, can prevent from producing overshoot in the 2nd error amplification signal COMP2.
Afterwards, after terminating during the regeneration of inductor 9, switch motion and the oscillator 1 of low side MOSFET21 are made
Stop with the circuit operation of driving REG circuits 5.
Intermittent oscillation action is carried out by the way that a series of action of the above is repeated, becomes to get over output current Iout
Longer mode of small intermittent oscillation cycle is controlled, so that what is produced in high-end MOSFET8 and low side MOSFET21 opens
Loss is closed to decline and improve light-load efficiency.Moreover, at the end of during the conducting of intermittent oscillation, it is temporarily overlapping on FB voltages
Ripple, so that the 2nd error amplification signal instantaneously declines, prevents high-end MOSFET8 from continuously carrying out switch motion, so that will
The on-off times of each resting period are suppressed to once.Thereby, it is possible to by output voltage VoutRipple suppress low, and
The intermittent oscillation cycle will not fall to the degree more than necessary, therefore can suppress the sound from output capacitor 10.
With reference to Fig. 4 to returning to steady load from underloading（Iout≧Iskip_out）When action illustrate.With
Iout rise, intermittent oscillation end during in output voltage VoutFall time shorten, therefore the intermittent oscillation cycle shortens.
So as to, when be transferred to inductor current IL valley current value be more than 0A continuous mode when, due to zero cross signal ZERO into
For low steady state value, therefore set-reset flip-floop 2722 becomes reset state.Therefore, the conducting of switch 2725 and the cut-off of switch 2723, start
The charging of capacitor 2726.When the current potential TM of capacitor 2726, which reaches intermittent oscillation, permits the 2nd threshold value Vtm_Hi, comparator
2727 reversions and SKIP-OK signals are switched from high to low, while underloading detection threshold value is switched to the 1st threshold value Vsk_Lo.
When output load current Iout is rapidly changed into from underloading when overloaded, it is necessary to by output voltage VoutIt is permanent to revert to holding
It is fixed, therefore the 1st error amplification signal COMP1 sharp rises.At this time, when switch 2713 is in cut-off state, low-pass filtering
The time constant of device 271 becomes higher, therefore the 2nd error amplification signal COMP2 can not follow the 1st error amplification signal COMP1.Cause
This, in output voltage VoutIt is middle to produce very big decline.Moreover, receiving reset signal RESET, switch 276 periodically turns on,
Therefore the overlapping ripple on feedback voltage FB, hinders on the 1st error amplification signal COMP1 and the 2nd error amplification signal COMP2
Rise.Therefore, as shown in fig. 7, output voltage V sometimesoutDecline become larger.
In the present invention, rapidly it is changed into from underloading output voltage V when overloaded due to improving output load current Ioutout
Decline, therefore also there is circuits below in timer circuit 272 as shown in Figure 3.
That is, by feedback resistance 12 and feedback resistance 13 to output voltage VoutPartial pressure is carried out, by comparator 2729 to anti-
Feedthrough voltage FB is compared with reference voltage V fb_Lo, the output voltage dropping signal when FB voltages are lower than reference voltage V fb_Lo
FB-LOW.As output voltage dropping signal FB-LOW, set-reset flip-floop 2722 is resetted by logic or circuit 2730, together
When switch 2731 is turned on and is drawn high the anti-phase input current potential of comparator 2727 immediately.Therefore, SKIP-OK signals switch from high to
It is low.Thus, operating stably is transferred to from SKIP actions immediately, forbids the ripple overlap action of switch 276, while pass through FB-LOW
Signal and turn on switch 2713, so that the time constant of low-pass filter 271 to be switched to low grade.Therefore, load is anxious
As shown in the sequence diagram of Fig. 8, the reaction of the 2nd error amplification signal COMP2 accelerates, can be by output voltage for action when speed becomes
VoutDecline suppress low.
As described above, it is configured to, by underloading detection threshold value with the 1st threshold value Vsk_Lo, the 2nd threshold value Vsk_Md and the 3rd threshold value
This three stage of Vsk_Hi switches over, from stable oscillation stationary vibration action be transferred to intermitten when, underloading detection comparator 23 it is light
Carry detection threshold value and select the 1st threshold value Vsk_Lo, when being transferred to stable oscillation stationary vibration action from intermittent oscillation action, underloading detection is compared
2nd threshold value Vsk_Md or 3rd threshold value Vsk_ of the underloading detection threshold value selection voltage level of device 23 than the 1st threshold value Vsk_Lo greatly
Hi, produces magnetic hysteresis, so as to release the unstable action near underloading detection threshold value.
As described above, according to the DC/DC converters of embodiment 1, timer circuit 272 is according to from underloading detection circuit 23
Underloading signal and zero cross signal from zero cross detection circuit 22, intermitten license is inputted after by the defined time
Signal, in the case where continue for defined period during not exporting zero cross signal, exports intermitten disable signal.That is,
Due to exporting zero cross signal when output voltage is big, intermitten enabling signal is exported, is not exported when output voltage is small
Zero cross signal, therefore under conditions of output voltage is small, can be in the region of heavy duty without increase underloading detection threshold value
Intermittent oscillation is forbidden to act.
In addition, on current source Iripple, in a period of timer circuit 272 outputs intermitten enabling signal,
When outputing reset signal from PWM comparators 17, the overlapping defined time on the reversed input terminal of error amplifier 14
Ripple, therefore error amplification signal is instantaneously declined, prevent high-end MOSFET8 from continuously carrying out switch motion, so that will be every
The on-off times of one resting period are suppressed to once.
Thereby, it is possible to by output voltage VoutRipple suppress low, and the intermittent oscillation cycle will not fall to it is necessary with
On, therefore the sound from output capacitor can be suppressed.
In addition, when being acted from stable oscillation stationary vibration action transfer for intermittent oscillation, timer circuit 272 selects the 1st threshold value,
From intermittent oscillation action transfer for stable oscillation stationary vibration action when, timer circuit 272 selects the 2nd threshold value or the 3rd threshold value, thus into
Enter to the load current of intermittent oscillation action and there is no difference between current between the load current that intermittent oscillation action departs from, so as to
Enough release the unstable action near underloading detection threshold value.
Moreover, it can improve due to being sported low-pass filter circuit when overloaded from underloading in output load current Iout
Time constant be switched to output voltage V caused by low gradeoutDecline.
【Embodiment 2】
Fig. 9 is the circuit structure diagram of the DC/DC converters of the embodiment of the present invention 2.Figure 10 is for illustrating the present invention
The sequence diagram of the action of each several part of the DC/DC converters of embodiment 2.Relative to the embodiment 1 shown in Fig. 1, it is characterised in that
Add logical AND circuit 24, switch 25 and switch 26.For the structure identical with the structure shown in Fig. 1, the description thereof will be omitted.
In a period of intermittent oscillation acts, BIAS_OFF signals are changed to height by logical AND circuit 24 from undercut, so that
Switch 25 and the cut-off of switch 26, stop oscillator 1 and driving REG circuits 5.During the vibration conducting of intermittent oscillation action,
Logical AND circuit 24 BIAS_OFF signals are switched from high to it is low so that switch 25 and switch 26 conducting, start again at vibration
The action of device 1 and driving REG circuits 5, so as to start again at the switch motion of high-end MOSFET8 and low side MOSFET21.Pass through
The processing is repeated, the average value for the electric current for making to consume in circuit declines, can compared to the 1st embodiment shown in Fig. 1
Further improve light-load efficiency.
Fig. 9 is the circuit structure diagram of the DC/DC converters of the embodiment of the present invention 2.Figure 10 is for illustrating the present invention
The sequence diagram of the action of each several part of the DC/DC converters of embodiment 2.
The DC/DC converters of embodiment 2 shown in Fig. 9, relative to the DC/DC converters of the embodiment 1 shown in Fig. 1, its
It is characterized in that, is also provided with logical AND circuit 24, switch 25 and switch 26.In addition, for the knot identical with the structure shown in Fig. 1
Structure, the description thereof will be omitted.
One end of switch 25 and driving REG circuits 5 and bias source Ibias1One end connection.Switch 26 and the one of oscillator 1
End and bias source Ibias2One end connection.Logical AND circuit 24 takes out the zero cross signal from zero cross detection circuit 22 and is patrolled with coming from
The logical AND between the SKIP2 of circuit 273 is collected, by BIAS_OFF signal outputs to switch 25, switch 26.
Then, the sequence diagram with reference to shown in Figure 10 illustrates action.First, during the cut-off of intermittent oscillation action
（For example, moment t3~t4）, BIAS_OFF signals are changed into height from undercut, so that switch 25 and the cut-off of switch 26, make vibration
Device 1 and driving REG circuits 5 stop.
Intermittent oscillation action conducting during in, logical AND circuit 24 BIAS_OFF signals are switched from high to it is low, from
And make switch 25 and the conducting of switch 26, start again at oscillator 1 and drive the action of REG circuits 5, and start again at high-end
The switch motion of MOSFET8 and low side MOSFET21.
By the way that the processing is repeated, the average value for the electric current that can make to consume in DC/DC converters declines.Therefore,
Compared to the DC/DC converters of the embodiment 1 shown in Fig. 1, light-load efficiency can be further improved.
The present invention can be used in switching power unit.
Claims (6)
1. a kind of DC/DC converters, it ends switching elements conductive according to the drive signal that control circuit generates, so that by the
1 DC voltage is converted to the 2nd DC voltage, which is characterized in that,
Control circuit has：
Oscillator, the pulse of frequency as defined in its output；
Error amplifier, it is amplified the error between the 2nd DC voltage and reference voltage and exports the 1st error and put
Big signal；
Low-pass filter circuit, it has the adjustment element for adjustment time constant, input the 1st error amplification signal and
Generate the 2nd error amplification signal；
Current detection circuit, electric current for flowing through the switch element is detected for it and output current signal；
Current comparator, it compared with the current signal, exports the 2nd error amplification signal according to comparing, defeated
Go out the reset signal for making the switch element cut-off；
Inductor, it is connected with the lead-out terminal of the switch element and the 2nd DC voltage；
Zero cross detection circuit, during the regeneration of the inductor at the end of, the zero cross detection circuit output zero cross signal, its
In, the lead-out terminal of the inductor, the switch element and the 2nd DC voltage is connection；
Underloading detection circuit, it exports underloading signal to the 2nd error amplification signal compared with threshold value；
Timer circuit, when outputing the underloading signal and the zero cross signal, after the time as defined in the 1st is passed through,
The timer circuit exports intermitten enabling signal, and the phase is continue for as defined in the 2nd during the zero cross signal is not exported
Between in the case of, the timer circuit output intermitten disable signal；
ON-OFF control portion, in a period of the timer circuit outputs the intermitten enabling signal, described
When 2nd error amplification signal is less than threshold value, which end the switch element, in the timer circuit
, should when the 2nd error amplification signal becomes more than the threshold value in a period of outputing the intermitten enabling signal
ON-OFF control portion makes the switching elements conductive；
Voltage superposing circuit, it is connected with the input terminal of the error amplifier, is outputed in the timer circuit described
In a period of intermitten enabling signal, when outputing the reset signal from the current comparator, in the defined time
The interior input terminal overlapping voltage signal to the error amplifier；And
Voltage detecting circuit, its situation to voltage reduction as defined in the 2nd DirectCurrent Voltage Ratio are detected,
In voltage reduction as defined in the 2nd DirectCurrent Voltage Ratio, the adjustment element of the low-pass filter circuit, which receives, to be come from
The signal of the voltage detecting circuit, is adjusted in a manner of the time constant for making the low-pass filter diminishes.
2. DC/DC converters according to claim 1, it is characterised in that
In a period of the timer circuit outputs the intermitten enabling signal, exported from the current comparator
During reset signal, the low-pass filter circuit makes the time constant more normal than the defined time by the adjustment element
Number is small.
3. DC/DC converters according to claim 2, it is characterised in that
The voltage superposing circuit is forbidding the overlapping of the voltage signal after the defined time,
The low-pass filter circuit makes the time normal after the defined time by the adjustment element
Number is bigger than the defined time constant.
4. the DC/DC converters described in any one in claims 1 to 3, it is characterised in that
The threshold value has：1st threshold value, the 3rd threshold value of 2nd threshold value bigger than the 1st threshold value and 2 threshold values of Bi greatly,
When being transferred to intermittent oscillation action from stable oscillation stationary vibration action, the timer circuit selects the 1st threshold value, from institute
When stating intermittent oscillation action and being transferred to stable oscillation stationary vibration action, the timer circuit selects the 2nd threshold value or the described 3rd
Threshold value.
5. DC/DC converters according to claim 4, it is characterised in that
When the error amplification signal is less than 1 threshold value, the 1st threshold value is switched in institute by the timer circuit
The 2nd threshold value or the 3rd threshold value are stated,
When the error amplification signal is less than 2 threshold value, the ON-OFF control portion ends the switch element,
When the error amplification signal becomes more than the 3rd threshold value, the ON-OFF control portion makes the switching elements conductive.
6. the DC/DC converters described in any one in claims 1 to 3, it is characterised in that
The DC/DC converters have the regulator circuit for being used for driving the switch element,
The DC/DC converters have driving stop, and the intermitten enabling signal is outputed in the timer circuit
In a period of, which makes the oscillator and described steady according to the zero cross signal from the zero cross detection circuit
Volt circuit stops.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410114285.1A CN104953824B (en) | 2014-03-25 | 2014-03-25 | DC/DC converters |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410114285.1A CN104953824B (en) | 2014-03-25 | 2014-03-25 | DC/DC converters |
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| CN106712501B (en) * | 2015-07-17 | 2019-06-04 | 三垦电气株式会社 | The control circuit and electric pressure converter of electric pressure converter |
| DE102018110696B3 (en) * | 2018-05-04 | 2019-09-12 | Vossloh-Schwabe Deutschland Gmbh | Operating device and method for operating a lamp arrangement |
| CN113346753B (en) * | 2021-04-30 | 2023-01-17 | 广州金升阳科技有限公司 | Light and no-load control method and circuit of clamp asymmetric half-bridge flyback converter |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1365181A (en) * | 2000-12-04 | 2002-08-21 | 三垦电气株式会社 | DC-DC converter |
| CN1411130A (en) * | 2001-09-28 | 2003-04-16 | 三垦电气株式会社 | Switch power supply unit |
| JP2007020352A (en) * | 2005-07-11 | 2007-01-25 | Rohm Co Ltd | Voltage-fall type switching regulator, and its control circuit, and electronic equipment using the same |
| CN102377337A (en) * | 2010-08-19 | 2012-03-14 | 三垦电气株式会社 | Switching power source apparatus |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5481178A (en) * | 1993-03-23 | 1996-01-02 | Linear Technology Corporation | Control circuit and method for maintaining high efficiency over broad current ranges in a switching regulator circuit |
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2014
- 2014-03-25 CN CN201410114285.1A patent/CN104953824B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1365181A (en) * | 2000-12-04 | 2002-08-21 | 三垦电气株式会社 | DC-DC converter |
| CN1411130A (en) * | 2001-09-28 | 2003-04-16 | 三垦电气株式会社 | Switch power supply unit |
| JP2007020352A (en) * | 2005-07-11 | 2007-01-25 | Rohm Co Ltd | Voltage-fall type switching regulator, and its control circuit, and electronic equipment using the same |
| CN102377337A (en) * | 2010-08-19 | 2012-03-14 | 三垦电气株式会社 | Switching power source apparatus |
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