JP6341423B2 - DC / DC converter - Google Patents

Description

  The present invention relates to a DC / DC converter.

  As a method for generating a stable voltage lower than the input voltage, a non-insulated step-down chopper circuit is widely used. However, since the switching operation is continued even when the load is light, such as during standby, the power conversion efficiency decreases as the load becomes light.

  In order to solve this problem, a light load is detected by comparing the error signal generated by comparing the output voltage and the reference voltage with a predetermined threshold value. Thus, a method has been proposed in which the intermittent operation is repeated by controlling on / off of the switching transistor.

  This control method can reduce the switching loss by reducing the frequency of the switching operation as the load becomes lighter, and can also reduce the gate drive current of the switching transistor, thereby improving the efficiency (Patent Document 1). ). FIG. 10 shows a DC / DC converter described in Patent Document 1. In FIG.

  The DC / DC converter shown in FIG. 10 includes an oscillator 1, an SR flip-flop 2, an AND circuit 3, a high side driver 4, a drive REG circuit 5, a backflow prevention diode 6, a bootstrap capacitor 7, a high side MOSFET 8, an inductor 9, and an output. Capacitor 10, output load 11, feedback resistor 12, feedback resistor 13, error amplifier 14, phase compensation resistor 15, phase compensation capacitor 16, PWM comparator 17, inverter 18, NOR circuit 19, low side driver 20, low side MOSFET 21, zero cross detection circuit 22, a light load detection comparator 23, a constant current source Ibias1, and a constant current source Ibias2.

  Next, referring to the timing chart shown in FIG. 11, first, the operation in the region at the time of steady load (Iout> Iskip) will be described.

  The output voltage Vout is divided by the feedback resistor 12 and the feedback resistor 13 to generate the feedback voltage FB. The feedback voltage FB is input to the inverting input terminal of the error amplifier 14, and the reference voltage Vref is input to the non-inverting input terminal. The error amplifier 14 generates an error amplification signal COMP between the feedback voltage FB and the reference voltage Vref, and the error amplification signal COMP is output to the inverting input terminal of the PWM comparator 17 and the inverting input terminal of the light load detection comparator 23. The light load detection first threshold value Vsk_Lo is input to the non-inverting input terminal of the light load detection comparator 23. When the output load current Iout is sufficiently large, COMP> Vsk_Lo. For this reason, the output signal SKIP2 of the light load detection comparator 23 becomes low level, and a low level signal is output to the input of the inverter circuit 18. For this reason, the intermittent oscillation operation is prohibited.

  A constant current source Ibias 2 is connected to the oscillator 1, and the oscillator 1 generates a set pulse based on the constant current source Ibias 2 and outputs the set pulse to the set terminal S of the PWM latch 2.

  A constant current source Ibias 1 is connected to the drive REG circuit 5, and the drive REG (regulator) circuit 5 supplies a drive voltage to the high side drive circuit 4 via the low side drive circuit 20 and the backflow prevention diode 6.

  When the PWM latch 2 is set, the high side MOSFET 8 is turned on by driving the high side driver 4 via the AND circuit 3. At this time, the SW terminal voltage rises to a voltage near the DC power supply Vin, and a current IDH corresponding to the voltage difference between the SW terminal and the Vout terminal flows through the inductor 9, thereby supplying energy to the output capacitor 10 and the output load 11. Do.

  On the other hand, the high-side current detection signal Vtrip proportional to the drain current IDH of the high-side MOSFET 8 is input to the non-inverting input of the PWM comparator 17. When the high side current detection signal Vtrip becomes equal to or higher than the error amplification signal COMP during the ON period of the high side MOSFET 8, the reset signal RESET is output to the PWM latch 2. When the PWM latch 2 is in the reset state, the high side driver 4 is turned off via the AND circuit 3 and the low side driver 20 is turned on via the NOR circuit 19. As a result, the high-side MOSFET 8 is switched from on to off, and the low-side MOSFET 21 is switched from off to on, whereby the regenerative current IDL is supplied from the source of the low-side MOS 21 to the inductor 9 through the drain.

  In the case of the current continuous operation in which the regeneration of the inductor 9 is not completed during the oscillation period determined by the oscillator 1, the PWM latch 2 is set again, the low-side MOSFET 21 is turned off, and the high-side MOSFET 8 is turned on.

  The step-down chopper operation is performed by repeating the above operation. Next, referring to FIG. 11, the operation when shifting from a steady load to a light load and returning to the steady load again will be described. When Iout decreases, the error amplification signal COMP decreases, so that the peak value of the drain current IDH of the high-side MOSFET 8 is controlled to be small. The light load detection comparator 23 compares the error amplification signal COMP with the first light load detection threshold value Vsk_Lo, and when the error amplification signal COMP becomes less than the first threshold value Vsk_Lo, the first threshold value Vsk_Lo is switched to the second threshold value Vsk_Hi, and at the same time, the light load The detection signal SKIP switches from low to high. Then, the high-side MOSFET 8 is forcibly turned off via the inverter 18, the AND circuit 3, and the high-side driver 4. Thereafter, when the zero-cross detection circuit 22 detects that the regeneration period of the inductor 9 is completed and the zero-cross signal ZERO switches from low to high, the low-side MOSFET 21 is turned off via the NOR circuit 19 and the low-side driver 20.

  Thereafter, when the charge of the output capacitor 10 is discharged by the output current Iout during the intermittent oscillation switch operation stop period, the output voltage Vout decreases slightly, and when the potential difference between the voltage at the FB terminal and the voltage Vref widens, error amplification occurs. The voltage signal COMP rises.

  When the error amplification signal COMP becomes equal to or higher than the second light load threshold Vsk_Hi, the light load detection comparator 23 switches the light load detection signal SKIP from high to low, so that the light load detection threshold is changed from the second threshold Vsk_Hi to the first threshold Vsk_Lo. Switch to At this time, the switching operation is started when the output of the inverter 18 is switched from low to high.

  An intermittent oscillation operation is performed by repeating the above series of operations, and the switching loss generated in the high-side MOSFET 8 and the low-side MOSFET 21 is reduced by controlling the intermittent oscillation period to be longer as the output current Iout decreases. Improve light load efficiency.

  Thereafter, when Iout rises, the drop time of Vout during the intermittent oscillation off period is shortened as Iout rises, so that the intermittent oscillation period is shortened. Eventually, when the error amplification signal COMP rises and does not become less than the light load detection first threshold value Vsk_Lo, the operation shifts to a steady oscillation operation.

  In Patent Document 2, as a proposal to reduce the number of times of switching at a light load, the output voltage is detected by a hysteresis comparator, and when the detected voltage reaches the first threshold, the switching element is turned off, and the second smaller than the first threshold. In a step-down chopper that turns on a switching element when the threshold value is reached, it has been proposed to shift the second threshold value to the high potential side by a predetermined voltage width at light load.

US Pat. No. 5,481,178 JP 2007-020352 A

  However, in Patent Document 1, as a first problem, since there is a propagation delay in the PWM comparator 17, even if the current detection signal Vtrip reaches the error amplification signal COMP, a reset signal is quickly output to the PWM latch 2, The high side MOSFET 8 cannot be turned off. For this reason, the error amplification signal COMP is controlled in advance at a voltage lower than the target level. Since this propagation delay is constant, as shown in FIG. 12A, under the condition where Vout is relatively large (the voltage difference between Vin and Vout is small), the ON period of the high-side MOSFET 8 (FIG. 12A). (Corresponding to the ON period of Vtrip) is sufficiently long with respect to the propagation delay ΔT, so that there is no particular problem.

  However, under the condition where the setting of Vout is relatively small (the voltage difference between Vin and Vout is large), the ON period of the high-side MOSFET 8 (corresponding to the ON period of Vtrip in FIG. 12B) is shortened, and the propagation delay Thus, the error amplification signal COMP is controlled with a voltage much smaller than the target level. Since the light load detection comparator 23 performs light load detection by comparing the error amplification signal COMP and the light load detection first threshold value Vsk_Lo, as shown in FIG. (Light load detection threshold) becomes large, and there is a problem that intermittent oscillation operation is performed even in a heavy load region where steady oscillation operation is desired.

As a second problem, when the high-side MOSFET 8 is turned on during the intermittent oscillation period, Vout rises and the voltage difference between the FB terminal voltage and the voltage Vref increases, so that the error amplification signal COMP is lowered and lightened again. The load detection signal SKIP is switched from low to high, and the operations of the high side MOSFET 8 and the low side MOSFET 21 are stopped. However, since there is actually a response delay in the error amplification signal COMP and the error amplification signal COMP cannot quickly become less than the light load detection first threshold value (Vsk_Lo), as shown in FIG. Switching operation is performed several times during. For this reason, the ripple voltage superimposed on Vout increases, and accordingly, the intermittent oscillation off period becomes longer than necessary. For this reason, the intermittent oscillation frequency becomes lower than the human audible range (20 kHz or less), and when a ceramic capacitor is used as the output capacitor 10, there is a problem that sound is generated due to the piezoelectric effect.

  As a third problem, there is no current difference between the load current that enters the intermittent oscillation operation and the load current that exits the intermittent oscillation operation, and thus the operation becomes unstable in the load region near the threshold. there were. For Patent Document 2, the second problem can be reduced, but the first and third problems are not solved.

  The present invention provides a DC / DC converter capable of prohibiting intermittent oscillation operation in a heavy load region without causing the oscillation frequency to be lower than the audible range even when the output voltage is small, without increasing the light load detection threshold. It is to provide.

In order to solve the above-described problem, the DC / DC converter according to claim 1 is a DC / DC converter that converts a first DC voltage into a second DC voltage by turning on and off a switching element in accordance with a drive signal generated by a control circuit. A converter that outputs a pulse of a predetermined frequency; an error amplifier that amplifies an error between the second DC voltage and a reference voltage and outputs an error amplification signal; and the switching element; An inductor connected to the output terminal of the second DC voltage, a zero-cross detection circuit that outputs a zero-cross signal when the regeneration period of the inductor is completed, and an error amplification signal from the error amplifier are compared with a threshold value to reduce the threshold. a light-load detection circuit for outputting a load signal, the zero cross signal from the light load signal and the zero-cross detection circuit from the light load detection latch circuit and A timer circuit that outputs an intermittent operation permission signal after a predetermined period of time and outputs an intermittent operation prohibition signal when a period in which the zero cross signal is not output continues for a predetermined period, and the timer circuit outputs the intermittent operation permission signal. The switching element is turned off when the error amplification signal becomes less than the threshold during a period, and the error amplification signal becomes at least the threshold during the period when the timer circuit outputs the intermittent operation permission signal. An on / off control unit that turns on the switching element at times, detects an off period of the switching element during a period in which the timer circuit outputs the intermittent operation permission signal, and changes the threshold according to the detected off period And an oscillation pause period limiting circuit for controlling the intermittent oscillation period within a predetermined time. .

According to the present invention, the timer circuit output is not a period of light load detection light load signal and the zero-crossing signal and outputs zero-crossing signal the intermittent operation permission signal after a predetermined time has elapsed based on the zero-crossing detection circuit from the latch circuit is predetermined When the period continues, an intermittent operation inhibition signal is output. That is, when the output voltage is larger than the light load threshold level determined by the zero cross detection circuit, for better light load threshold level determined by the light load detection known circuit is low, the light load <br/> test is priority known circuit outputs an intermittent operation permission signal, while the output when the voltage is low, than the light load threshold level determined by the zero crossing detecting circuit, a light load threshold determined by the light load detection known circuits Since the level is higher, the zero cross detection circuit is prioritized and the intermittent operation permission signal is output. For this reason, even if the output voltage is low, the light load detection threshold value is not increased, and the intermittent oscillation operation can be prohibited in the heavy load region. Furthermore, by monitoring the oscillation suspension period during intermittent oscillation operation and changing the reference value of the light load detection threshold according to the oscillation suspension period, the intermittent oscillation period is controlled so that the intermittent oscillation period does not enter the audible range. It becomes possible to control stably.

It is a circuit block diagram of the DC / DC converter of the Example of this invention. It is a detailed circuit block diagram of the zero cross detection circuit of the DC / DC converter of the Example of this invention. It is a detailed circuit block diagram of the timer circuit of the DC / DC converter of the Example of invention. It is a timing chart for demonstrating operation | movement of each part of the DC / DC converter of the Example of this invention. It is a timing chart of each part for demonstrating the operation | movement which superimposes a ripple voltage at the time of the intermittent oscillation operation | movement of the DC / DC converter of the Example of this invention. It is a figure which shows the light load detection threshold value determined only by an error amplification signal detection with respect to an output voltage in the conventional DC / DC converter. It is a figure which shows the light load detection threshold value which took the AND of the threshold value determined by error amplification signal detection with respect to an output voltage, and the threshold value determined by zero cross detection with respect to the output voltage in the Example of this invention. FIG. 4 is a circuit configuration diagram of a DC / DC converter according to an embodiment of the present invention with details of an oscillation pause period limiting circuit 30 added. 9 is a timing chart for explaining the operation of each part of the DC / DC converter according to the embodiment of the present invention shown in FIG. It is a circuit block diagram of the conventional DC / DC converter. It is a timing chart for demonstrating operation | movement of each part of the conventional DC / DC converter. It is a figure explaining the problem that a light load detection threshold rises rapidly when the voltage difference of an input voltage and an output voltage is large in the conventional DC / DC converter.

  Hereinafter, embodiments of the DC / DC converter of the present invention will be described in detail with reference to the drawings. First, an outline of the present invention will be described.

  Whereas the prior art detects a light load by comparing the error amplification signal with a threshold value, the present invention combines detection with the error amplification signal and a zero-cross detection circuit that detects discontinuity in the inductor current. It is characterized by detecting a light load.

  That is, the present invention combines a light load detection comparator that performs light load detection by comparing an error amplification signal and a light load detection threshold with a zero cross detection circuit that detects that the regeneration period of the inductor has ended, When the value is relatively small, light load detection by zero cross detection is performed, and when the Vout value is relatively large, a light load detection comparator performs light load detection. As a result, the problem that the light load detection threshold rapidly increases when Vout is small can be solved, and light load detection with less Vout dependency can be realized.

  In contrast, the conventional technique stops the switching operation when the error amplification signal becomes less than the light load detection threshold, and restarts the switching operation when the error amplification signal exceeds the light load detection threshold. The invention is characterized in that an intermittent oscillation operation control circuit is added and the number of switches during one intermittent oscillation operation period is suppressed to one.

  That is, the present invention reduces the error amplification signal instantaneously by temporarily superimposing a ripple on the FB voltage at the end of the intermittent oscillation on-period, thereby preventing the high-side MOSFET from continuously switching. Limit the number of switches per intermittent cycle to one. Thereby, the ripple of the output voltage Vout can be suppressed low, and since the intermittent oscillation period does not become lower than necessary, the noise from the output capacitor can be suppressed.

  The prior art provides hysteresis with a first threshold and a second threshold larger than the first threshold in order to detect a light load, whereas the present invention provides the first threshold and the first threshold. The hysteresis is provided with a second threshold value greater than the second threshold value and a third threshold value greater than the second threshold value.

  That is, the present invention has a configuration in which the light load detection threshold is switched in three stages, the first threshold, the second threshold, and the third threshold, and the light load detection comparator has a light load when transitioning from the steady oscillation operation to the intermittent operation. As the load detection threshold, the first threshold is selected, and when shifting from the intermittent oscillation operation to the steady oscillation operation, the light load detection threshold of the light load detection comparator is the second threshold having a voltage level higher than the first threshold, or The unstable operation near the light load detection threshold can be eliminated by selecting three thresholds and generating hysteresis.

Further, the present invention is characterized in that the oscillation oscillation period of the intermittent oscillation period is monitored, and the intermittent oscillation period is controlled by changing the reference value of the light load detection threshold according to the oscillation suspension period.

That is, the present invention monitors the oscillation suspension period of the intermittent oscillation cycle, and when the oscillation suspension period is longer than the predetermined period, the light load detection threshold of the light load detection comparator is lowered to shorten the intermittent oscillation cycle. When the oscillation pause period is corrected to be shorter than the predetermined period, the intermittent oscillation period is lengthened by raising the light load detection threshold of the light load detection comparator and making the intermittent oscillation period longer. It becomes possible to control.

  Next, a specific example of the DC / DC converter having the above-described features will be described as an example.

  FIG. 1 is a circuit configuration diagram of a DC / DC converter according to an embodiment of the present invention. FIG. 2 is a detailed circuit configuration diagram of the zero-cross detection circuit of the DC / DC converter according to the embodiment of the present invention. FIG. 3 is a detailed circuit diagram of the timer circuit of the DC / DC converter of the embodiment of the invention.

  The DC / DC converter according to the embodiment is a DC / DC converter that converts a first DC voltage into a second DC voltage by turning on and off a switching element in accordance with a drive signal generated by a control circuit.

  The oscillator 1 outputs a pulse having a predetermined frequency. The error amplifier 14 amplifies the error between the second DC voltage and the reference voltage and outputs an error amplification signal. The inductor 9 is connected to MOSFETs 8 and 21 made of switching elements and an output terminal of the second DC voltage Vout. The zero-cross detection circuit 22 outputs a zero-cross signal when the regeneration period of the inductor 9 is completed. The light load detection comparator 23 compares the error amplification signal from the error amplifier 14 with a threshold value and outputs a light load signal.

  The DC / DC converter according to the embodiment has an intermittent oscillation operation control circuit 27 for controlling the intermittent oscillation operation and an oscillation pause period during the intermittent oscillation operation, in addition to the configuration of the conventional DC / DC converter shown in FIG. A limiting circuit 30 is provided.

  First, the intermittent oscillation operation control circuit 27 includes a low-pass filter circuit 271 including a filter resistor 2711, a filter capacitor 2712, a switch 2713, and an OR circuit 2715, a timer 272, an AND circuit 273, an AND circuit 274, a one-shot circuit 275, A switch 276 and a current source Iripple are included.

The timer circuit 272 is outputted without periods of light load signal and the zero-crossing signal and outputs zero-crossing signal the intermittent operation permission signal after a predetermined time has elapsed based on the zero-crossing detection circuit 22 from the light-load detection knowledge comparator 23 continues for a predetermined time period In this case, an intermittent operation prohibition signal is output.

The AND circuit 273, the inverter 18, and the AND circuit 3 (on / off control unit) turn off the MOSFET 8 when the error amplification signal becomes less than the threshold during the period in which the timer circuit 272 outputs the intermittent operation permission signal, and the timer circuit The MOSFET 8 is turned on when the error amplification signal becomes at least a threshold value or more during the period in which the 272 outputs the intermittent operation permission signal.

  The low-pass filter circuit 271 includes an adjustment element for adjusting the time constant, and generates the second error amplification signal COMP2 by the adjustment element based on the first error amplification signal COMP1. The filter resistor 2711, the filter capacitor 2712, the switch 2713, and the OR circuit 2715 constitute an adjustment element.

  The PWM comparator 17 (current comparator) compares the second error amplification signal COMP2 with the current signal flowing through the MOSFET 8, and outputs a reset signal for turning off the MOSFET 8 to the AND circuit 274 based on the comparison output. The AND circuit 274 takes an AND of the reset signal from the PWM comparator 17 and the signal from the timer circuit 272 and outputs the result to the one-shot circuit 275. The one-shot circuit 275 generates a one-shot pulse based on the output from the AND circuit 274 and outputs the one-shot pulse to the switch 2713 via the switch 276 and the OR circuit 2715.

  The current source Iripple (voltage superposition circuit) is connected to the inverting input terminal of the error amplifier 14 via the switch 276. When the reset signal is output from the PWM comparator 17 while the timer circuit 272 is outputting the intermittent operation permission signal, the current source Iripple is supplied to the inverting input terminal of the error amplifier 14 for a predetermined time (one shot pulse period). Superimpose the signal.

  When the intermittent operation permission signal SKIP-OK is output from the timer circuit 272, the low-pass filter circuit 271 makes the time constant larger than a predetermined time constant by turning off the switch 2713. Further, when the reset signal is output from the PWM comparator 17 while the timer circuit 272 is outputting the intermittent operation permission signal, the switch 2713 is turned on only during the period of one shot pulse output by the one-shot circuit 275. The constant is set to a predetermined time constant.

  The current source Iripple prohibits the superposition of the voltage signal after a predetermined time has elapsed. The low-pass filter circuit 271 sets the time constant to be larger than the predetermined time constant by turning off the switch 2713 after a predetermined time has elapsed.

  Next, the region operation at the time of steady load (Iout> Iskip_in) will be described with reference to the timing chart of FIG.

  The output voltage Vout is divided by the feedback resistor 12 and the feedback resistor 13 to generate the feedback voltage FB. The feedback voltage FB is input to the inverting input terminal of the error amplifier 14, and the reference voltage Vref is input to the non-inverting input terminal. The error amplifier 14 generates a first error amplification signal COMP1 of the feedback voltage FB and the reference voltage Vref and outputs it to the low-pass filter 271.

  In a steady load state, the output of the timer circuit 272 is at a low level, so the switch 2713 is closed via the OR circuit 2715, the attenuation characteristic of the low-pass filter 271 is weak, and the second error amplification signal COMP2 is The voltage is substantially equal to the error amplification signal COMP1 and is input to the inverting input terminal of the PWM comparator 17 and the inverting input terminal of the light load detection comparator 23. When the light load detection threshold value Vsk_Lo is input to the non-inverting input of the light load detection comparator 23 and the output current Iout is sufficiently large, COMP2> Vsk_Lo is satisfied, so that the output signal SKIP1 of the light load detection comparator 23 is low level. Become. Therefore, a low-level SKIP2 signal is output to the input of the inverter circuit 18 via the AND circuit 273. For this reason, the intermittent oscillation operation is prohibited.

  A constant current source Ibias 2 is connected to the oscillator 1, a set pulse is generated based on the constant current source Ibias 2, and is output to the set terminal of the PWM latch 2.

  A constant current source Ibias 1 is connected to the drive REG circuit 5 and supplies a drive voltage to the high side drive circuit 4 via the low side drive circuit 20 and the backflow prevention diode 6.

  When the PWM latch 2 is set, the high side MOSFET 8 is turned on by driving the high side driver 4 via the AND circuit 3. At this time, the SW terminal voltage rises to a voltage close to Vin, and a current IDH corresponding to the voltage difference between the SW terminal and the Vout terminal flows through the inductor 9 to supply energy to the output capacitor 10 and the output load 11.

  On the other hand, a high-side current detection signal Vtrip that is proportional to the drain current IDH of the high-side MOSFET 8 is input to the non-inverting input terminal of the PWM comparator 17, and the high-side current detection signal Vtrip is supplied during the ON period of the high-side MOSFET 8. When the error amplification signal COMP2 is equal to or higher than 2, the reset signal RESET is output to the PWM latch 2. When the PWM latch 2 is in a reset state, the high side driver 4 is turned off via the AND circuit 3 and the low side driver 20 is turned on via the NOR circuit 19. As a result, the high-side MOSFET 8 is switched from on to off, and the low-side MOSFET 21 is switched from off to on, whereby the regenerative current IDL is supplied from the source of the low-side MOS 21 to the inductor 9 through the drain.

  In the case of a continuous current operation in which regeneration of the inductor 9 is not completed during the oscillation period determined by the oscillator 1, the PWM latch 2 is set again, the low-side MOSFET 21 is turned off, and the high-side MOSFET 8 is turned on.

  The step-down chopper operation is performed by repeating the above series of operations.

  Next, the operation when shifting from a steady load to a light load (Iout = Iskip_in) will be described with reference to FIGS.

  When Iout decreases, the first error amplification signal COMP1 and the second error amplification COMP2 decrease, so that the peak value of the drain current IDH of the high-side MOSFET is controlled to be small. The light load detection comparator 23 compares the second error amplification signal COMP2 with the first light load detection threshold value Vsk_Lo, and when the second error amplification signal COMP2 becomes less than the first light load detection threshold value Vsk_Lo at time t1, the first light load detection threshold value Vsk_Lo. The load detection signal SKIP1 is switched from low to high, and a signal indicating a light load state is supplied to the AND circuit 273 and the timer circuit 272.

  Thereafter, when Iout further decreases and the valley current of the inductor current IL reaches zero ampere, the current discontinuous operation is performed. At this time, the polarity of the SW terminal voltage is switched from minus to plus. As shown in FIG. 2, the zero-cross detection circuit 22 detects a change in polarity of the SW terminal voltage by the comparator 221 and sets the SR flip-flop 222 in the set state. As a result, the low-side MOSFET 21 is turned off via the NOR circuit 19 and the low-side driver 20, and at the same time, a signal indicating a zero-cross detection state is output to the timer circuit 272.

  When the first light load detection signal SKIP1 and the zero-cross signal ZERO are both high at the time t2, the timer circuit 272 sets the SR flip-flop 2722 via the AND circuit 2721 as shown in FIG. The capacitor 2726 is discharged by the constant current source Idis by turning on the switch 2723 and turning off the switch 2725 through the inverter 2724.

  The comparator 2727 compares the potential TM of the capacitor 2726 with the intermittent oscillation permission first threshold value Vtm_Lo, and at time t3, the potential TM of the capacitor 2726 reaches the first threshold value Vtm_Lo. Then, the intermittent oscillation permission signal SKIP-OK signal switches from low to high, and at the same time, the first threshold value Vtm_Lo is switched to the second threshold value Vtm_Hi having a voltage level higher than the first threshold value Vtm_Lo. As a result, the mode is switched to allow the intermittent oscillation operation. At this time, the light load detection threshold value of the light load detection comparator 23 is switched to the third threshold value Vsk_Hi having a voltage level larger than the first threshold value Vsk_Lo.

  When the SKIP-OK signal is switched from low to high, one input of the OR circuit 2715 becomes low level, so that the switch 2713 is opened and the switch 2713 is opened and closed by the other input Ripple_on signal.

In this way, the AND circuit 2721 ANDs the SKIP1 from the light load detection comparator 23 and the zero cross signal ZERO from the zero cross detection circuit 22 to perform light load detection. Under the condition that the Vout value is relatively small, the light load threshold level determined by the zero-cross detection circuit 22 is lower than the light load threshold level determined by the light-load detection comparator 23. The detection threshold value Iskip-in is determined. In this case, the light load detection threshold value Iskip-in is expressed as follows, assuming that the inductor value of the inductor 9 is L and the steady oscillation frequency is Fsw.
Iskip_in = Vout (Vin−Vout) / (2 · L · Vin · Fsw)
In the condition where Vout is relatively small, when Iskip-in is the vertical axis and Vout is the horizontal axis, a parabolic characteristic is obtained as shown in FIG.

  On the other hand, in a region where Vout is relatively large, the Iskip-in level is determined with priority by the conventional light load detection comparator 23. This situation is illustrated in FIG. Therefore, the conventional problem that Iskip-in becomes large in the region where Vout is small shown in FIG. 6 can be solved. Even in a region where Vout is large, it is possible to prevent Iskip-in from becoming too large, and it is possible to realize a light load detection operation with little Vout dependency.

  Next, the operation in the intermittent oscillation period (Iout <Iskip_in) at light load will be described with reference to FIGS.

  In a state where the SKIP-OK signal is high and intermittent oscillation is permitted, the AND circuit 273 outputs a high to the second light load detection signal SKIP2 when the first light load detection signal SKIP1 is high, The high side MOSFET 8 is forcibly turned off via the AND circuit 3 and the high side driver 4. Thereafter, at time t3, when the zero cross detection circuit 22 detects that the regeneration period of the inductor 9 is completed and the zero cross signal ZERO switches from low to high, the low side MOSFET 21 is turned off via the NOR circuit 19 and the low side driver 20. .

  Thereafter, when the electric charge of the output capacitor 10 is discharged by the output current Iout during the intermittent oscillation switch operation stop period, the Vout slightly decreases, and when the potential difference between the FB terminal and Vref widens, the first error amplified voltage signal COMP1. Therefore, the second error amplification signal COMP2 also rises.

  When the second error amplification signal COMP2 becomes equal to or higher than the third light load threshold Vsk_Hi at time t4 in FIG. 5, the light load detection comparator 23 switches the first light load detection signal SKIP1 from high to low, thereby The load detection signal SKIP2 is also switched from high to low, and the light load detection threshold is switched to the second light load threshold Vsk_Md having a voltage level smaller than Vsk_Hi and larger than Vsk_Lo. At this time, when the output of the inverter 18 is switched from low to high, the switching operation of the MOSFET 8 is started.

  Thereafter, when the drain current IDH of the high-side MOSFET 8 rises and the current detection signal Vtrip reaches the second error amplification signal COMP2 at time t5, the PWM comparator 17 outputs a reset signal to the PWM latch 2 so that the high-side MOSFET The MOSFET 8 is turned off. At this time, the reset signal RESET2 is also supplied to the one-shot circuit 275 via the AND circuit 274.

  In response to the reset signal RESET2, the one-shot circuit 275 switches the Ripple_ON signal from low to high only for a predetermined period (time t6 to t7). Thereby, since the switch 276 is turned on, the constant current Iripple is supplied to the FB terminal, and the FB terminal voltage rises instantaneously. Further, by turning on the switch 2713 via the OR circuit 2715 with the Ripple_on signal at this timing, the time constant of the low puff filter 271 is reduced and the attenuation effect is weakened.

  When the FB terminal voltage rises rapidly, the voltage difference from Vref widens, so that the error amplifier 14 instantaneously reduces the first error amplification signal COMP1, and the second error amplification signal COMP2 also decreases following that (time t6). ~ T7).

  When the second error amplification signal COMP2 decreases and reaches the light load detection threshold Vsk_Md, the light load detection circuit 23 switches the first light load detection signal SKIP1 from low to high again to stop the switching operation of the high side MOSFET 8. At the same time, the light load detection threshold is switched to Vsk_Hi.

  The one-shot circuit 275 switches the Ripple_ON signal from high to low after a predetermined period (time t6 to t7) has elapsed, and turns off the switch 276. At this time, at time t8 to t9, the first error amplification signal COMP1 may overshoot and the light load detection circuit 23 may cause erroneous detection. For this reason, by turning off the switch 2713, the time constant of the low-pass filter 271 can be increased to improve the attenuation characteristic, and the occurrence of overshoot in the second error amplification signal COMP2 can be prevented.

  Thereafter, after the regeneration period of the inductor 9 is completed, the switching operation of the low-side MOSFET 21 is stopped.

  An intermittent oscillation operation is performed by repeating the above series of operations, and the switching loss generated in the high-side MOSFET 8 and the low-side MOSFET 21 is reduced by controlling the intermittent oscillation period to be longer as the output current Iout decreases. Improve light load efficiency. Further, by temporarily superimposing a ripple on the FB voltage at the end of the on-period of intermittent oscillation, the second error amplification signal is instantaneously reduced, and the high-side MOSFET 8 is prevented from continuously switching, thereby preventing one intermittent operation. Limit the number of switches per cycle to one. Thereby, the ripple of the output voltage Vout can be suppressed low, and since the intermittent oscillation period does not become lower than necessary, it is possible to suppress the sound from the output capacitor 10.

  Next, an operation when returning from a light load to a steady load (Iout ≧ Iskip_out) will be described with reference to FIG. As Iout increases, the decrease time of Vout during the intermittent oscillation off period is shortened, so that the intermittent oscillation period is shortened. Eventually, when the valley current value of the inductor current IL shifts to a continuous mode of 0 A or more, the zero-cross signal ZERO is fixed to low, so that the SR flip-flop 2722 is reset. Accordingly, the switch 2725 is turned on, the switch 2723 is turned off, and charging of the capacitor 2726 is started. When the potential TM of the capacitor 2726 reaches the intermittent oscillation permission second threshold value Vtm_Hi, the comparator 2727 is inverted to switch the SKIP-OK signal from high to low and at the same time switch the light load detection threshold value to the first threshold value Vsk_Lo.

  As described above, the light load detection threshold is configured to switch between the first threshold value Vsk_Lo, the second threshold value Vsk_Md, and the third threshold value Vsk_Hi in three stages, and when shifting from the steady oscillation operation to the intermittent operation, the light load detection comparator 23 As the light load detection threshold value, the first threshold value Vsk_Lo is selected, and when shifting from the intermittent oscillation operation to the steady oscillation operation, the light load detection threshold value of the light load detection comparator 23 is the first voltage level that is larger than the first threshold value Vsk_Lo. By selecting the second threshold value Vsk_Md or the third threshold value Vsk_Hi and generating hysteresis, the unstable operation near the light load detection threshold value can be eliminated.

Thus, the timer circuit 272, the output is not a period of zero cross signal and outputs the zero-crossing signal the intermittent operation permission signal after a predetermined time has elapsed based on from the light load signal and the zero-cross detection circuit 22 from the light-load detection knowledge comparator 23 When the operation continues for a predetermined period, an intermittent operation inhibition signal is output. That is, when the output voltage is large, is preferentially light-load detection knowledge comparator 23 outputs an intermittent operation permission signal when the output voltage is small, the zero-crossing detection circuit is preferentially outputs the intermittent operation permission signal. For this reason, even if the output voltage is low, the light load detection threshold value is not increased, and the intermittent oscillation operation can be prohibited in the heavy load region.

  Further, the current source Iripple superimposes a ripple on the inverting input terminal of the error amplifier 14 for a predetermined time when the reset signal is output from the PWM comparator 17 while the timer circuit 272 outputs the intermittent operation permission signal. The error amplification signal is reduced instantaneously to prevent the high-side MOSFET 8 from continuously switching, thereby reducing the number of switches per intermittent cycle to one. Thereby, the ripple of the output voltage Vout can be suppressed low.

  The timer circuit 272 selects the first threshold when shifting from the steady oscillation operation to the intermittent oscillation operation, and selects the second threshold or the third threshold when shifting from the intermittent oscillation operation to the steady oscillation operation. A current difference is intentionally provided between the load current that enters the intermittent oscillation operation and the load current that exits the intermittent oscillation operation, and the unstable operation near the light load detection threshold can be eliminated.

Here, the operation of the oscillation pause period limiting circuit 30 for limiting the intermittent oscillation period in the intermittent oscillation operation so as not to enter the audible range will be described.
FIG. 8 is a circuit configuration diagram of the DC / DC converter according to the embodiment of the present invention. FIG. 9 is a timing chart for explaining the operation of each part of the DC / DC converter of the embodiment of the present invention.

  The DC / DC converter of the embodiment shown in FIG. 8 shows the details of the oscillation pause period limiting circuit 30 in addition to the DC / DC converter of the embodiment shown in FIG. The description of the same configuration as that shown in FIG. 1 is omitted.

The oscillation pause period limiting circuit 30 includes a DA converter circuit 308, an up / down counter circuit 307 that outputs a voltage change signal to the DA converter circuit 308, and a latch circuit 306 that generates a signal to be input to the up / down counter circuit 307. , The current source Iclamp, the reference voltage clampREF, the capacitor 304 for monitoring the oscillation suspension period of the intermittent oscillation period, the switch 302 for controlling the charging current of the capacitor 304, the switch 303 for controlling the discharge of the capacitor 304, and the inverter 301, intermittently It comprises a comparator 305 that monitors the oscillation pause period of the oscillation period and compares the generated voltage clamp with the reference voltage clampREF.
Note that the reference voltage Skip_REF of the light load detection comparator 23 described above is an output voltage generated by the DA converter circuit 308.

  Next, the operation of the oscillation pause period limiting circuit 30 will be described with reference to the timing chart shown in FIG. The load current Iout decreases and becomes the third light load threshold Vsk_Hi after time t0. When the load current further decreases and the intermittent oscillation operation starts after time t1, the light load detection comparator 23 switches the first light load detection signal SKIP1 to high, and the second light load detection signal SKIP2 also switches to high. Here, the up / down counter circuit 307 outputs a count at the time of a steady load and inputs it to the DA converter 308. The DA converter 308 outputs the light load detection threshold Vsk_Hi based on the reference voltage during steady operation to the non-inverting terminal of the light load detection comparator 23.

Next, when the second light load detection signal SKIP2 switches to high at time t2, the switch 30
2 is turned on and a charging current flows from the current source Iclamp to the capacitor 304. At the same time, the switch 303 is turned off via the inverter 301, so that the discharge path of the capacitor 304 is eliminated, and the capacitor 304 is charged with the constant current Iclamp. Here, when the state in which the load current decreases continues and the oscillation suspension period of the intermittent oscillation operation becomes longer, the capacitor 30
The charging time to 4 also becomes longer. At time t3, the clamp voltage of the capacitor 304 becomes cla.
When the voltage exceeds the mpREF voltage, the output of the comparator 305 is inverted, a low to high signal is output, and a reset signal is input to the reset terminal of the latch circuit 306. As a result, the output voltage cin of the latch circuit 306 is inverted from the high level to the low level, and the low level signal is held even at time t4. At time t4, since the inverting terminal voltage COMP2 exceeds the non-inverting terminal voltage Vsk_Hi of the light load detection comparator 23, the high side MOSFET 8 is turned on. At the same time, from time t4 to time t5, the light load detection threshold value of the light load detection comparator 23 is selected from the third threshold value Vsk_Hi having the largest voltage level to the second threshold value Vsk_Md.

Next, the output time cout of the up / down counter circuit 307 constituted by a circuit that counts up when the cin voltage is high level and counts down when the cin voltage is low level is the timing when the RESET signal that becomes the clock signal becomes high level At t5, the countdown is performed. Thereby, skipREF which is the output voltage of the DA converter 308 is reduced by 1 bit from time t5 to t7 which is the next cycle. The light load detection threshold of the light load detection comparator 23 between time t5 and time t6 is selected from the second threshold value Vsk_Md to the third threshold value Vsk_Hi. In skipREF shown in FIG. 9, the third threshold value Vsk_Hi at times t5 to t6 is set slightly higher than the second threshold value Vsk_Md at times t4 to t5.

Thus, since the absolute value of the light load detection threshold skipREF is lowered, the upper limit value of the COMP2 signal is narrowed and the turn-on timing of the high-side MOSFET 8 is advanced, so that the oscillation suspension period of the intermittent oscillation period can be limited. it can.
Further, by reducing the absolute value of the light load detection threshold skipREF, the ON period of the high side MOSFET 8 is shortened, and the energy supply capability to the output voltage Vout is reduced. As a result, there is an advantage that the control system is likely to be stable because it is not limited only to the off period.

Next, since the cin voltage is also output at the timing of time t8, the output cout of the up / down counter circuit 307 further reduces the light load detection threshold skipREF by one bit from time t8 to t10. .

Next, at the timing of time t10, since the cin voltage is output at a high level, the output cout of the up / down counter circuit 307 increases the light load detection threshold skipREF by one bit.

Thereafter, each time the next second light load detection signal SKIP2 switches from low to high, the above-described operation is repeated, and the absolute value of the light load detection threshold is converged while limiting the upper limit of the oscillation suspension period of the intermittent oscillation period. I can do it.

According to DC / DC converter of this embodiment as described above, to monitor the oscillation stop period of the intermittent oscillation period, it controls the intermittent oscillation cycle by changing the reference value of the light load detection knowledge threshold according to the oscillation stop period Thus, the intermittent oscillation period can be stably controlled without entering the audible range.

The embodiment of the present invention has been described above. However, the above embodiment is an example for embodying the technical idea of the present invention, and does not specify individual configurations, combinations, and the like as described above. Absent. The present invention can be implemented with various modifications without departing from the scope of the invention.

  The present invention is applicable to a switching power supply device.

DESCRIPTION OF SYMBOLS 1 Oscillator 2 SR flip-flop 3,24,273,274 AND circuit 4 High side driver 5 Drive REG circuit 6 Backflow prevention diode 7 Bootstrap capacitor 8 High side MOSFET
9 Inductor 10 Output capacitor 11 Output load 12, 13 Feedback resistor 14 Error amplifier 15 Phase compensation resistor 16 Phase compensation capacitor 17 PWM comparator 18 Inverter 19 NOR circuit 20 Low side driver 21 Low side MOSFET
22 Zero cross detection circuit 23 Light load detection comparator 25, 26, 302, 303 Switch 27 Intermittent oscillation operation control circuit 271 Low-pass filter circuit 272 Timer circuit 275 One shot circuit 276, 277, 2713 Switch 2711 Filter resistance 2712 Filter capacity 2715 OR circuit 30 Oscillation pause period limiting circuit 301 Inverter 304 Capacitor 305 Comparator 306 Latch circuit 307 Up / down counter circuit 308 DA converter circuit Iripple, Iclamp Current source Ibias1, Ibias2 Constant current source

Claims (6)

The switching element is turned on / off according to the drive signal generated by the control circuit, so that the first
A DC / DC converter for converting a DC voltage into a second DC voltage,
The control circuit includes:
An oscillator that outputs a pulse of a predetermined frequency;
An error amplifier that amplifies an error between the second DC voltage and a reference voltage and outputs an error amplification signal;
An inductor connected to the switching element and an output terminal of the second DC voltage;
A zero-cross detection circuit that outputs a zero-cross signal when the regeneration period of the inductor is completed;
A light load detection circuit that compares the error amplification signal from the error amplifier with a threshold value and outputs a light load signal;
Wherein by intermittently operating the switching element based on the zero cross signal from the light load signal and the zero-cross detection circuit from the light load detection known circuit, the error amplified signal during a period in which intermittent operation is less than the threshold value An on / off controller that turns off the switching element when the error amplification signal is at least equal to or greater than the threshold value during the intermittent operation period.
An oscillation pause period limiting circuit that detects an off period of the switching element during the intermittent operation and controls the intermittent oscillation period within a predetermined time by changing the threshold according to the detected off period. DC / DC converter. The switching element is turned on / off according to the drive signal generated by the control circuit, so that the first
A DC / DC converter for converting a DC voltage into a second DC voltage,
The control circuit includes:
An oscillator that outputs a pulse of a predetermined frequency;
An error amplifier that amplifies an error between the second DC voltage and a reference voltage and outputs an error amplification signal;
An inductor connected to the switching element and an output terminal of the second DC voltage;
A zero-cross detection circuit that outputs a zero-cross signal when the regeneration period of the inductor is completed;
A light load detection circuit that compares the error amplification signal from the error amplifier with a threshold value and outputs a light load signal;
Intermittent if Nonprinting period of the zero-cross signal and outputs an intermittent operation permission signal after a predetermined time has elapsed based on the zero cross signal from the light load signal the zero-cross detection circuit from the light load detection known circuits continues for a predetermined time period A timer circuit for outputting an operation prohibition signal;
A period during which the timer circuit outputs the intermittent operation permission signal when the error amplification signal becomes less than the threshold value during a period when the timer circuit outputs the intermittent operation permission signal. An on / off controller that turns on the switching element when the error amplification signal is at least equal to or greater than the threshold;
The timer circuit detects an off period of the switching element during which the intermittent operation permission signal is output, and controls the intermittent oscillation period within a predetermined time by changing the threshold value according to the detected off period. A DC / DC converter comprising an oscillation pause period limiting circuit. The threshold comprises a first threshold, a second threshold greater than the first threshold, and a third threshold greater than the second threshold;
The timer circuit selects the first threshold value when shifting from the steady oscillation operation to the intermittent oscillation operation, and the second threshold value or the third threshold value when shifting from the intermittent oscillation operation to the steady oscillation operation.
The DC / DC converter according to claim 2, wherein a threshold value is selected. The timer circuit switches the first threshold to the second threshold or the third threshold when the error amplification signal becomes less than the first threshold,
The on / off control unit turns off the switching element when the error amplification signal becomes less than the second threshold value, and turns on the switching element when the error amplification signal becomes equal to or more than the third threshold value. The DC / DC converter according to claim 3. The oscillation pause period limiting circuit lowers the threshold when the off-period of the switching element is longer than a predetermined time, and increases the threshold when the off-period of the switching element is shorter than the predetermined time. The DC / DC converter according to claim 2, wherein: The oscillation pause period limiting circuit includes an up / down counter circuit and a DA converter circuit for inputting a count output of the up / down counter circuit,
The DA converter circuit generates the threshold;
6. The DC / DC converter according to claim 5, wherein a count value of the up / down counter circuit is changed in accordance with an off period of the switching element.