JP5034750B2 - Power control circuit - Google Patents

Description

  The present invention relates to a power supply control circuit that controls the voltage of an output power supply by changing the energization time of an inductor by PWM control of a switching element.

  In the case of a step-down type power supply circuit such as a DC / DC converter, a series circuit of a switching element such as a power MOSFET, a coil and a capacitor is arranged between the power supply and the ground, and the output power supply voltage and the reference voltage The FET is switched by a PWM signal generated according to the difference between the two. In the power supply circuit having such a configuration, the difference between the output voltage and the reference voltage is very large immediately after the power is turned on and the operation is started, and thus a large inrush current may flow through the coil. Therefore, it is necessary to perform so-called soft start control so as to gradually increase the current flowing when the power is turned on.

For example, Patent Document 1 discloses the following configuration as a power supply control circuit that performs soft start control. The output voltage of the power supply control circuit and the output detection voltage Vfb of the D / A converter are compared by a comparator, the counter is counted up by the output signal of the comparator, and the count data is D / A converted by the D / A converter. To do. The error amplifier generates a PWM signal using a result obtained by comparing the lower one of the output voltage Vdac of the D / A converter and the reference voltage Vref with the detection voltage Vfb, and outputs the PWM signal to the gate of the FET. When the power is turned on, the output voltage Vdac of the D / A converter is sequentially increased by the counter based on the result of comparison with the detection voltage Vfb until the reference voltage Vref is reached, and soft start control is performed. It has become.
JP 2006-325339 A

However, the configuration disclosed in Patent Document 1 requires a counter and a D / A converter, which increases the circuit scale.
The present invention has been made in view of the above circumstances, and an object thereof is to provide a power supply control circuit capable of performing soft start control with a simpler configuration.

According to the power supply control circuit of the first aspect, since the output voltage is low immediately after the input power supply is turned on and the operation is started, the difference from the reference voltage set in the PWM command generation circuit is large, and the generated PWM The level of the control command becomes high, and the duty of the PWM signal output from the PWM signal output circuit becomes 100%. Since the current detected by the overcurrent detection circuit does not reach the overcurrent level, a continuous energization signal with a duty of 100% is output to the switching element via the logic circuit. As a result, the voltage of the power supply that is output when the inductor is continuously energized rises.
When the above state continues, the energization current of the inductor increases, and the overcurrent detection signal is output by the overcurrent detection circuit. Therefore, after the first delay time given by the delay circuit has elapsed, the switching element is cut off and the inductor is supplied to the inductor. Is stopped and the detection current of the overcurrent detection circuit becomes zero. Then, after the second delay time elapses, the switching element is turned on again, energization of the inductor is resumed, and the detection current of the overcurrent detection circuit starts to increase.

Therefore, during the period when the output power supply voltage is low and the PWM signal output circuit does not substantially output the PWM signal (less than 100% duty), the switching element is intermittently energized by the action of the overcurrent detection circuit and the logic circuit. Slow start control is performed. When the PWM control command decreases as the output voltage increases, the PWM signal output circuit outputs a PWM signal with a duty less than 100%, and the power supply control circuit shifts to a steady operation state.
At that time, since the overcurrent detection circuit does not detect the overcurrent, the logic circuit outputs the PWM signal as it is to the switching element as an energization signal. That is, by the action of the delay circuit and the logic circuit, it is possible to realize the slow start control when the power is turned on with a simpler configuration than the conventional one.

  According to the power supply control circuit of the second aspect, the reference voltage output circuit outputs a voltage signal serving as a reference value to the overcurrent detection circuit, and the PWM signal monitoring means outputs the PWM signal in a normal state. If it is determined that the voltage signal is not, the level of the voltage signal is set low, and if it is determined that the PWM signal is output in a normal state, the level of the voltage signal is set high. That is, immediately after the power is turned on, a PWM signal with a duty less than 100% is not output as described above. Therefore, the reference value in the overcurrent detection circuit is set to a low level, the overcurrent is detected, and the slow start control during the initial operation is performed. Is executed. On the other hand, during steady operation, a PWM signal with a duty less than 100% is output, so the reference value in the overcurrent detection circuit is set to a high level, and no overcurrent is detected and the PWM signal is output as it is. . Therefore, the overcurrent detection level during slow start control can be set lower than during steady operation.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows an overall configuration of a power supply control circuit which is a step-down DC / DC converter. A series circuit of a P-channel MOSFET (semiconductor switching element) 1, a coil (inductor) 2 and a capacitor 3 is connected between the power source + B and the ground, and a free wheel is connected between the drain of the FET 1 and the ground. A diode 4 is connected.

The common connection point of the coil 2 and the capacitor 3 is connected to the inverting input terminal of the error amplifier 6 through the gain resistor 5, and the non-inverting input terminal of the error amplifier 6 which is a differential amplifier circuit has a band gap reference. A reference voltage VBG of 1.22 V is applied from the voltage circuit (BG) 7. The output terminal of the error amplifier 6 is connected to the inverting input terminal of the comparator 8 for generating the PWM signal, and the non-inverting input terminal of the comparator 8 is given a triangular wave signal from the carrier wave output circuit 9 as a carrier wave. Yes.
On the source side of the FET 1, a resistance element 10 is disposed as a current detection unit. As shown in FIG. 2, the current detection unit may be configured by connecting a current detection FET 11 in parallel to the FET 1 and inserting a resistance element 10 into the source of the FET 11.

  The source of the FET 1 is connected to a non-inverting input terminal of a comparator 13 for current comparison, and a reference voltage VLIM for comparison (a voltage corresponding to an overcurrent ILIM) is applied to the inverting input terminal. The output terminal of the comparator 13 is connected to one input terminal of an AND gate (logic circuit) 15 via an analog filter (delay circuit) 14, and the output terminal of the comparator 8 is connected to the other input terminal. It is connected. The output terminal of the AND gate 15 is connected to the gate of the FET 1 through the pre-driver 16. The pre-driver 16 inverts the output level of the AND gate 15 and gives a drive signal to the gate of the FET 1.

FIG. 3 shows a specific configuration example of the analog filter 14. The analog filter 14 includes a Schmitt trigger buffer 17, a series circuit of a charging current source 18 and a capacitor 19 connected between the power source + B and the ground, and a switch connected between a common connection point between the two and the ground. A circuit 20 and a discharge current source 21 are included. The common connection point is connected to the input terminal of the buffer 17, and the switch circuit 20 is turned on / off by the output signal Vcomp of the comparator 13.
The relationship between the constant current Ic flowing through the charging current source 18 and the constant current Id flowing through the discharging current source 21 is set so that Ic <Id, and when the switch circuit 20 is OFF, the capacitor 19 is When charged by the current source 18 and the switch circuit 20 is ON, the capacitor 19 is discharged by the current source 21.

  In the above configuration, the power supply control circuit 22 is configured except for the coil 2, the capacitor 3, and the diode 4. In addition, the resistor element 10 and the comparator 13 constitute an overcurrent detection circuit 23, the error amplifier 6 and the band gap reference voltage circuit 7 constitute a PWM command generation circuit 24, and the comparator 8 and the carrier wave output circuit 9 include a PWM signal. An output circuit 25 is configured.

Next, the operation of this embodiment will be described with reference to FIGS. FIG. 5 is a timing chart showing an operation state when the power supply + B is turned on to the power supply control circuit 22, and FIG. 4 is an enlarged view of a part of the waveform of FIG. 5B (initial change portion). FIG. Since the level of the output voltage Vout is low immediately after the power supply + B is turned on, the level of the output signal Verr of the error amplifier 6 is high, and the PWM control command is equal to or higher than the maximum level of the PWM carrier wave. Therefore, the output of the comparator 8 becomes a low level. At this time, since the current value detected by the current detector 10 is also small, the output signal Vcomp of the comparator 13 for current comparison is at a high level.

  When the current value detected in this state rises and exceeds the reference voltage VLIM in the comparator 13, the output signal Vcomp of the comparator 13 changes to a low level [see FIGS. 4 (a), (b), (1)]. Then, the switch circuit 20 of the analog filter 14 is switched from OFF to ON, and the capacitor 19 starts discharging. When the terminal voltage falls below the input threshold value of the buffer 17, the output signal Vfilt of the analog filter 14 becomes low level. That is, the output signal Vfilt becomes low level when the delay time tdoff elapses from the time when the input signal of the analog filter 14 is switched from high to low by the above-described operation [see FIGS. 4 (c) and (2)]. As a result, the output level of the AND gate 15 changes from low to high, and the FET 1 is turned off.

  When the FET 1 is turned off, the voltage drop in the resistance element 10 disappears, and the level of the non-inverting input terminal of the comparator 13 rises to the power supply + B level, so that the output signal Vcomp immediately becomes high level. Then, the switch circuit 20 of the analog filter 14 is turned off and charging of the capacitor 19 is started. When the terminal voltage exceeds the input threshold value of the buffer 17, the output signal of the analog filter 14 becomes high level. In other words, the output signal Vfilt becomes high level when the delay time tdon elapses from the time when the input signal of the analog filter 14 is switched from low to high by the above-described operation [see FIGS. 4 (c) and 4 (3)].

  When the FET 1 is turned OFF, a delayed current flows through the coil 2, so that the current IL starts to decrease at the point (2) as a peak. When the output signal Vfilt of the analog filter 14 becomes high level as described above, the output level of the AND gate 15 changes from high to low, and the FET 1 is turned on again. Then, the coil current IL starts to rise [see FIGS. 4 (a) and 4 (4)]. When the reference voltage VLIM in the comparator 13 is exceeded, the output signal Vcomp of the comparator 13 changes to a low level [FIG. 4 (a), (Refer to (5)], the state becomes the same as (1).

  Reference is now made to FIG. FIG. 5A shows the ON / OFF state of the FET 1, and FIG. 5C shows the change of the PWM carrier wave and the output voltage Vout. As shown in FIG. 5C, the PWM signal with a duty less than 100% is not output during the period from when the power source + B is turned on until the output voltage Vout rises to some extent, but the comparator 13 and the analog filter described in FIG. By the action of 14, the FET 1 is intermittently turned ON / OFF, and the slow start control is performed. As a result, the increase in the output voltage Vout shown in FIG. 5C is moderate.

  When the output voltage Vout level rises and the detection voltage in the error amplifier 6 becomes near the reference voltage VBG, the PWM signal output circuit 24 outputs a PWM signal with a duty less than 100%, and the FET 1 is turned on / off, and the output voltage Vout becomes a steady operation state controlled near the target power supply voltage. In this case, if normal operation continues, the current detected by the comparator 13 does not exceed the reference value ILIM, so that the output signal Vfilt of the analog filter 14 continues to maintain a high level.

  As described above, according to this embodiment, immediately after the power supply + B is turned on to the power supply control circuit 22, the period during which the output voltage Vout is low and the PWM signal output circuit 25 does not output a PWM signal with a duty less than 100% is The slow start control is performed by intermittently energizing the FET 1 by the action of the overcurrent detection circuit 23 and the AND gate 15, the PWM control command decreases as the output voltage Vout increases, and the PWM signal output circuit 24 is less than 100% duty When the PWM signal is output, a steady operation state is entered. Therefore, it is possible to realize the slow start control when the power is turned on with a simpler configuration than the conventional one.

  In Japanese Patent Application Laid-Open No. 2004-228688, the configuration for realizing the conventional slow start control adopts a configuration using a counter and a D / A converter because it is a problem to use a capacitor. Is a capacitor having a large time constant in the order of ms. In this embodiment, the analog filter 14 is provided with a capacitor 19. However, the capacitor 19 has a time constant that has a capacity as small as μs at most. For example, even when the power control circuit 22 is assumed to be integrated into an IC. It is a capacitor of a size that can be easily formed inside the IC. Therefore, the function is different from the capacitor in question in Patent Document 1.

(Second embodiment)
6 and 7 show a second embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals and the description thereof will be omitted. Hereinafter, different parts will be described. The power supply control circuit 31 of the second embodiment is configured by adding a counter (PWM signal monitoring means) 32 and a variable reference voltage circuit (reference voltage output circuit) 33 to the power supply control circuit 22 of the first embodiment. The

The counter 32 counts the number of carrier waves output from the carrier wave output circuit 9 and is reset by the output signal of the comparator 8. The output signal Q of the counter 32 is sent to the variable reference voltage circuit 33. Is given. The variable reference voltage circuit 33 changes the level of the reference voltage applied to the inverting input terminal of the comparator 13 in two steps according to the state of the output signal Q.
For example, the counter 32 changes the output signal Q to a high level when the number of carrier wave outputs is counted 10 from the reset state, and the variable reference voltage circuit 33 is a reference when the output signal Q is at a high level. The voltage VLIM is set to a low level, and when the output signal Q is at a low level, the reference voltage VLIM is set to a high level.

  Next, the operation of the second embodiment will be described with reference to FIG. Immediately after the power supply + B is turned on to the power supply control circuit 31, the counter 32 is reset. In this case, since the comparator 13 does not output a PWM signal with a duty less than 100%, when the carrier wave output circuit 9 outputs the carrier wave for 10 cycles, the output signal Q becomes high level, and the variable reference voltage circuit 33 reduces the reference voltage VLIM. The level is set [see FIGS. 7 (b) and (1)]. In this state, the slow start control is executed as in the first embodiment.

  When the output voltage Vout rises and the PWM signal circuit 24 outputs a PWM signal with a duty less than 100%, the counter 32 is reset by the output signal of the comparator 8, the output signal Q becomes low level, and the variable reference voltage The circuit 33 sets the reference voltage VLIM to a higher level [see FIGS. 7B and 7].

  As described above, according to the second embodiment, the variable reference voltage circuit 33 sets the reference voltage VLIM applied to the comparator 13 to be low during the slow start control according to the state of the output signal Q of the counter 32, and during the steady operation. I set it higher. Therefore, since the level of the reference voltage VLIM can be changed according to whether the PWM signal is constantly output, the overcurrent detection level during the slow start control can be set lower than during the steady operation.

(Third embodiment)
FIG. 8 shows a third embodiment of the present invention. The third embodiment shows another configuration example of an analog filter as a delay circuit. An analog filter 34 shown in FIG. 8A is a very general CR filter including a resistor element 35, a capacitor 19 and a buffer 17, and an analog filter 36 shown in FIG. 8B is a resistor of FIG. 8A. A series circuit of a diode 37 and a resistance element 38 is connected in parallel to the element 35. That is, in the analog filter 36, the time constant is small because the resistance element 38 is in parallel with the resistance element 35 during charging, and the time constant is large because only the resistance element 35 contributes during discharging. Therefore, a time difference can be provided between the delay times tdon and tdoff as in the first embodiment.

The present invention is not limited to the embodiments described above and shown in the drawings, and the following modifications or expansions are possible.
In addition, the delay circuit may be configured by connecting a plurality of (in the case of inversion, even number) stages of logic gates (forward and inversion buffers) in series.
The current detection unit may use a current transformer, for example, to supply the detection output to the inverting input terminal of the comparator 13 and supply the reference voltage for comparison to the non-inverting input terminal.
The Schmitt trigger buffer 17 constituting the analog filter may be replaced with a buffer having no hysteresis characteristic.

  In the second embodiment, a flip-flop is arranged in place of the counter 32. For example, the variable reference voltage circuit 33 sets the reference voltage VLIM to a low level corresponding to the initial output state of the flip-flop after power-on, and the comparator 8 When the first PWM signal with a duty less than 100% is output first, the initial output state may be cleared and the variable reference voltage circuit 33 may set the reference voltage VLIM to a high level.

1 is a diagram illustrating an overall configuration of a power supply control circuit according to a first embodiment of the present invention. The figure which shows the other structural example of an electric current detection part. The figure which shows the specific structural example of an analog filter Timing chart showing a part of FIG. Timing chart showing the operating state when power supply + B is turned on to the power supply control circuit FIG. 1 equivalent view showing a second embodiment of the present invention. Figure equivalent to FIG. FIG. 2 equivalent view showing a third embodiment of the present invention.

Explanation of symbols

  In the drawing, 1 is a P-channel MOSFET (semiconductor switching element), 2 is a coil (inductor), 6 is an error amplifier, 14 is an analog filter (delay circuit), 15 is an AND gate (logic circuit), 22 is a power supply control circuit, 23 is an overcurrent detection circuit, 24 is a PWM command generation circuit, 25 is a PWM signal output circuit, 31 is a power supply control circuit, 32 is a counter (PWM signal monitoring means), 33 is a variable reference voltage circuit (reference voltage output circuit), Reference numerals 34 and 36 denote analog filters (delay circuits).

Claims (2)

In the power supply control circuit that controls the voltage of the output power by changing the energization time to the inductor by PWM controlling the switching element,
A PWM command generation circuit that generates a PWM control command in accordance with a potential difference between the power supply voltage and a reference voltage;
A PWM signal output circuit that compares the PWM control command with an amplitude level of a carrier wave and outputs a PWM signal;
An overcurrent detection circuit that detects the current flowing through the switching element and outputs an overcurrent detection signal when an overcurrent is detected in comparison with a reference value;
The overcurrent detection signal is provided with a first delay time that is a time from when the signal is output to when the switching element is shut off, and when the switching element is shut off and then turned on again. A delay circuit for providing a second delay time;
A logic circuit that synthesizes the PWM signal and a signal output from the delay circuit to output the PWM signal as a conduction control signal for the switching element when the overcurrent detection signal is not output; A power supply control circuit comprising: A reference voltage output circuit that outputs a voltage signal serving as the reference value to the overcurrent detection circuit;
PWM signal monitoring means for monitoring whether the PWM signal is output in a normal state,
When the PWM signal monitoring means determines that the PWM signal is not output in a normal state, the reference voltage output circuit sets the level of the voltage signal to be low and the PWM signal is output in a normal state. 2. The power supply control circuit according to claim 1, wherein the power supply control circuit is configured to set a level of the voltage signal high when it is determined that the voltage signal is present.

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