CN104952731A - Field effect transistor with accumulation effect and production method thereof - Google Patents
Field effect transistor with accumulation effect and production method thereof Download PDFInfo
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- CN104952731A CN104952731A CN201410127294.4A CN201410127294A CN104952731A CN 104952731 A CN104952731 A CN 104952731A CN 201410127294 A CN201410127294 A CN 201410127294A CN 104952731 A CN104952731 A CN 104952731A
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- 230000005669 field effect Effects 0.000 title claims abstract description 30
- 230000000694 effects Effects 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000009825 accumulation Methods 0.000 title abstract 2
- -1 Boron ions Chemical class 0.000 claims abstract description 26
- 229910052796 boron Inorganic materials 0.000 claims abstract description 20
- 239000013078 crystal Substances 0.000 claims description 51
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- 239000004020 conductor Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 239000011521 glass Substances 0.000 claims description 12
- 238000009792 diffusion process Methods 0.000 claims description 6
- 238000001465 metallisation Methods 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 238000001459 lithography Methods 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 abstract description 2
- 230000001186 cumulative effect Effects 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003292 diminished effect Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000002353 field-effect transistor method Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention discloses a field effect transistor with an accumulation effect and a production method thereof. A space charge region which bears counter voltage is changed to a vertical direction and a horizontal direction from a single vertical direction, when the counter voltage is borne, all depletion areas are formed by using an effective distance between trenches, and a structure capable of bearing high counter voltage is realized. The thickness of an epitaxial layer is reduced, at the same time the epitaxial concentration can be increased, the epitaxial resistivity is reduced, high counter voltage can be born in the condition of ensuring a thin epitaxial layer, and low internal resistance in conduction is realized. Boron ions are implanted at a trench bottom to form a P-type region, with the thick oxide layer at the trench bottom, the counter voltage can be born, and the switching speed of a MOS tube can be raised greatly. A barrier cumulative effect is used, free charges get together at the outer walls of the trenches when voltage is added at a gate, a conductive channel with a high concentration is formed, current flows through the channel to realize conduction and does not goes through the epitaxial layer with high resistance, and thus the internal resistance in the conduction is reduced further.
Description
Technical field
The invention belongs to technical field of semiconductors, be specifically related to field-effect transistor and the production method thereof with build-up effect.
Background technology
Power MOS pipe carrys out pressure-bearing when bearing back-pressure primarily of the intrinsic semiconductor of the vague and general rear formation of epitaxial loayer.Because the resistivity of epitaxial loayer is comparatively large, make Ron comparatively large, cause epilayer resistance to account for the ratio of overall conducting resistance bigger than normal.Therefore, by effectively improving epilayer resistance, Ron can be reduced further.At present, popular method is the 3D structure adopting similar super junction Super Junction, as shown in Figure 1.The 3D structure of similar super junction Super Junction reduces epilayer resistance from two aspects.On the one hand, vertical and horizontal both direction is changed into from single vertical direction in the space charge region bearing back-pressure, reduces the thickness of epitaxial loayer; On the other hand, when ensureing that metal-oxide-semiconductor cut-off time space charged region majority carrier can exhaust, improve epitaxial loayer carrier concentration, then during metal-oxide-semiconductor conducting, the resistivity of epitaxial loayer is just as far as possible little as far as possible.Just diminished at withstand voltage constant situation lower epi layer resistance or overall conducting resistance like this, during power MOS pipe work, heating is just few.But current Super Junction and 3D structure all exist certain technical difficulty, its core technology all rests in foreign brand name producer and domestic minority supplier hand.
Summary of the invention
Technical problem to be solved by this invention is to provide the field-effect transistor and production method thereof with build-up effect, and it while reaching Super Junction and 3D structure phase same-action, can reduce technology difficulty.
For solving the problem, the present invention is achieved by the following technical solutions:
There is the production method of the field-effect transistor of build-up effect, comprise the steps:
(1) to crystal prediffusion, the substrate layer that bottom relative concentration is high is spread to the epitaxial loayer that top relative concentration is low, and between substrate layer and epitaxial loayer, forms n+ layer;
(2) on crystal, make groove, and grow silicon dioxide oxide layer in the groove of crystal;
(3) in the groove of crystal plated metal or polysilicon as good conductor;
(4) oxide layer of plane of crystal is etched;
(5) inject boron ion to crystal and carry out diffusion knot, the groove Outboard Sections on epitaxial loayer top forms P-Body region;
(6) phosphonium ion of high dose injected to crystal and carry out diffusion knot, above P-Body region, forming the N+ source region of high concentration;
(7) BPSG boron-phosphorosilicate glass is deposited to protect grid Gate at the upper surface of crystal;
(8) contact hole is made by lithography on the top of crystal;
(9) inject the boron ion of high dose in the bottom of contact hole, form the P+ region of high concentration;
(10) metal closures is filled in the contact hole;
(11) metallization operations is carried out to crystal upper surface, at the metallic film such as upper surface plated aluminum or aluminium copper silicon of crystal;
(12) thinning and back face metalization operation is carried out to the crystal back side, produce drain D rain at the back side of crystal.
Above-mentioned steps (2) is specially:
(2.1) at the upper lithographic trenches figure of gained crystal;
(2.1.1) on crystal, groove is etched according to groove figure;
(2.1.2) inject boron ion at channel bottom, form boron ion district;
(2.2) in channel bottom, trenched side-wall and crystal upper surface growth silicon dioxide oxide layer.
In above-mentioned steps (2.1), negative photolithographicallpatterned or positive photolithographicallpatterned two schemes can be adopted to etch groove.
In above-mentioned steps (2.2), the thickness of the oxide layer of channel bottom growth is thicker than the thickness of the oxide layer of trenched side-wall and the growth of crystal upper surface.
Adopt the field-effect transistor with build-up effect that aforementioned production method obtains, its field effect transistor tube body is primarily of substrate layer, n+ floor, epitaxial loayer, boron ion district, oxide layer, good conductor, P-body region, N+, P+ district, source region, metal closures, boron-phosphorosilicate glass, metallic film and back of the body gold metal layer composition.Wherein n+ layer is positioned at the top of substrate layer, and epitaxial loayer is positioned at the top of n+ layer; Offer the groove extending to epitaxial loayer bottom from epitaxial loayer upper vertical in epitaxial loayer, boron ion district is arranged on the bottom outside of groove, and oxide layer is attached on sidewall inside groove and bottom, and good conductor is filled in the groove with oxide layer; P-body region is placed in above epitaxial loayer, the outside of groove; Source region N+ is placed in the top in P-body region, the outside of groove; Offer the contact hole extending to N+ bottom, source region from source region N+ upper vertical in the N+ of source region, P+ district is arranged on the bottom outside of contact hole, in contact hole, fill metal closures; Boron-phosphorosilicate glass covers directly over source region N+ and good conductor; Metallic film covers directly over metal closures and boron-phosphorosilicate glass; Metal layer on back is overlying on the bottom of substrate layer.Good conductor forms the grid of field effect transistor tube body, and metallic film forms the source electrode of field effect transistor tube body, and metal layer on back forms the drain electrode of field effect transistor tube body.
The thickness of the oxide layer of above-mentioned channel bottom growth is thicker than the thickness of the oxide layer of trenched side-wall growth.
Compared with prior art, the present invention, while reaching Super Junction and 3D structure phase same-action, reduces technology difficulty.Key point forms 3D structure, vertical and horizontal both direction being changed into from single vertical direction in the space charge region bearing back-pressure, when bearing back-pressure, utilizing coverage between groove to form whole exhaustion region, realizes the structure can bearing higher back-pressure.Reduce the thickness of epitaxial loayer, extension concentration can be increased simultaneously, reduce electrical resistivity of epitaxy, ensure can bear higher back-pressure under thinner epitaxial layer case, and internal resistance lower when realizing conducting; Also can at channel bottom by injecting boron ion, a territory, p type island region is formed at channel bottom, add the thick oxide layer of channel bottom, ensure on the one hand to bear back-pressure, significantly can eliminate the electric capacity between Gate and Drain on the other hand, significantly can reduce the charging interval (gate charge density (Qg) can significantly reduce) during Gate switch, thus improve the switching speed of metal-oxide-semiconductor.In addition make use of barrier cumulative effect, when Gate making alive, groove outer wall assembles free charge, and form the conductive channel of one deck high concentration, electric current is through this channel conductive, must through the higher epitaxial loayer of resistance, thus the internal resistance (Ron) when reduce further conducting.
Accompanying drawing explanation
Fig. 1 is the cutaway view of existing three-dimensional structure field-effect transistor.
The cutaway view with the field-effect transistor of build-up effect that Fig. 2 is the present invention.
Fig. 3-16 is the process drawing with the field-effect transistor of build-up effect shown in Fig. 2.
embodiment
There is a production method for the field-effect transistor of build-up effect, comprise the steps:
(1) to crystal prediffusion, the substrate layer that bottom relative concentration is high is spread to the epitaxial loayer that top relative concentration is low, and between substrate layer and epitaxial loayer, forms n+ layer.As Fig. 3.
(2) on crystal, make groove, and grow silicon dioxide oxide layer in the groove of crystal.
(2.1) at the upper lithographic trenches figure of gained crystal.As Fig. 4.Wherein photoetching can adopt negative photolithographicallpatterned or positive photolithographicallpatterned.
(2.1.1) on crystal, groove is etched according to groove figure.As Fig. 5.
(2.1.2) inject boron ion at channel bottom, form boron ion district, as Fig. 6.Wherein photoetching can adopt negative photolithographicallpatterned or positive photolithographicallpatterned two schemes optional.
(2.2) in channel bottom, trenched side-wall and crystal upper surface growth silicon dioxide oxide layer.As Fig. 7.In the present embodiment, the thickness of the oxide layer of channel bottom growth is thicker than the thickness of the oxide layer of trenched side-wall and the growth of crystal upper surface.
(3) in the groove of crystal plated metal or polysilicon as good conductor.As Fig. 8.
(4) oxide layer of plane of crystal is etched.As Fig. 9.
(5) inject boron ion to crystal and carry out diffusion knot, the groove Outboard Sections on epitaxial loayer top forms P-Body region.As Figure 10.
(6) phosphonium ion of high dose injected to crystal and carry out diffusion knot, above P-Body region, forming the N+ source region of high concentration.As Figure 11.
(7) BPSG boron-phosphorosilicate glass is deposited to protect grid Gate at the upper surface of crystal.As Figure 12.
(8) contact hole is made by lithography on the top of crystal.As Figure 13.
(9) inject the boron ion of high dose in the bottom of contact hole, form the P+ region of high concentration.As Figure 14.
(10) metal closures is filled in the contact hole.As Figure 15.
(11) metallization operations is carried out to crystal upper surface, at the metallic film such as upper surface plated aluminum or aluminium copper silicon of crystal.As Figure 16.
(12) thinning and back face metalization operation is carried out to the crystal back side, produce drain D rain at the back side of crystal.As Fig. 2.
Adopt the field-effect transistor with build-up effect that aforementioned production method obtains, as shown in Figure 2, its field effect transistor tube body is primarily of substrate layer, n+ floor, epitaxial loayer, boron ion district, oxide layer, good conductor, P-body region, N+, P+ district, source region, metal closures, boron-phosphorosilicate glass, metallic film and back of the body gold metal layer composition.Wherein n+ layer is positioned at the top of substrate layer, and epitaxial loayer is positioned at the top of n+ layer.Offer the groove extending to epitaxial loayer bottom from epitaxial loayer upper vertical in epitaxial loayer, boron ion district is arranged on the bottom outside of groove, and oxide layer is attached on sidewall inside groove and bottom, and good conductor is filled in the groove with oxide layer.P-body region is placed in above epitaxial loayer, the outside of groove.Source region N+ is placed in the top in P-body region, the outside of groove.Offer the contact hole extending to N+ bottom, source region from source region N+ upper vertical in the N+ of source region, P+ district is arranged on the bottom outside of contact hole, in contact hole, fill metal closures.Boron-phosphorosilicate glass covers directly over source region N+ and good conductor.Metallic film covers directly over metal closures and boron-phosphorosilicate glass.Metal layer on back is overlying on the bottom of substrate layer.Good conductor forms the grid of field effect transistor tube body, and metallic film forms the source electrode of field effect transistor tube body, and metal layer on back forms the drain electrode of field effect transistor tube body.In the present embodiment, metal closures is tungsten plug, and the thickness of the oxide layer of channel bottom growth is thicker than the thickness of the oxide layer of trenched side-wall growth.
Claims (6)
1. there is the production method of the field-effect transistor of build-up effect, it is characterized in that comprising the steps:
(1) to crystal prediffusion, the substrate layer that bottom relative concentration is high is spread to the epitaxial loayer that top relative concentration is low, and between substrate layer and epitaxial loayer, forms n+ layer;
(2) on crystal, make groove, and grow silicon dioxide oxide layer in the groove of crystal;
(3) in the groove of crystal plated metal or polysilicon as good conductor;
(4) oxide layer of plane of crystal is etched;
(5) inject boron ion to crystal and carry out diffusion knot, the groove Outboard Sections on epitaxial loayer top forms P-Body region;
(6) phosphonium ion injected to crystal and carry out diffusion knot, above P-Body region, forming N+ source region;
(7) BPSG boron-phosphorosilicate glass is deposited to protect grid at the upper surface of crystal;
(8) contact hole is made by lithography on the top of crystal;
(9) inject boron ion in the bottom of contact hole, form P+ region;
(10) metal closures is filled in the contact hole;
(11) metallization operations is carried out to crystal upper surface, at the metallic film such as upper surface plated aluminum or aluminium copper silicon of crystal;
(12) thinning and back face metalization operation is carried out to the crystal back side, produce drain electrode at the back side of crystal.
2. have the production method of the field-effect transistor of build-up effect according to claim 1, it is characterized in that, above-mentioned steps (2) is specially:
(2.1) at the upper lithographic trenches figure of gained crystal;
(2.1.1) on crystal, groove is etched according to groove figure;
(2.1.2) inject boron ion at channel bottom, form boron ion district;
(2.2) in channel bottom, trenched side-wall and crystal upper surface growth silicon dioxide oxide layer.
3. there is the production method of the field-effect transistor of build-up effect according to claim 2, it is characterized in that, in above-mentioned steps (2.1), adopt negative photolithographicallpatterned or positive photolithographicallpatterned to etch groove.
4. have the production method of the field-effect transistor of build-up effect according to claim 2, it is characterized in that, in above-mentioned steps (2.2), the thickness of the oxide layer of channel bottom growth is thicker than the thickness of the oxide layer of trenched side-wall and the growth of crystal upper surface.
5. adopt the field-effect transistor with build-up effect that described in claim 1, production method obtains, comprise field effect transistor tube body, it is characterized in that, described field effect transistor tube body is primarily of substrate layer, n+ floor, epitaxial loayer, boron ion district, oxide layer, good conductor, P-body region, N+, P+ district, source region, metal closures, boron-phosphorosilicate glass, metallic film and back of the body gold metal layer composition; Wherein n+ layer is positioned at the top of substrate layer, and epitaxial loayer is positioned at the top of n+ layer; Offer the groove extending to epitaxial loayer bottom from epitaxial loayer upper vertical in epitaxial loayer, boron ion district is arranged on the bottom outside of groove, and oxide layer is attached on sidewall inside groove and bottom, and good conductor is filled in the groove with oxide layer; P-body region is placed in above epitaxial loayer, the outside of groove; Source region N+ is placed in the top in P-body region, the outside of groove; Offer the contact hole extending to N+ bottom, source region from source region N+ upper vertical in the N+ of source region, P+ district is arranged on the bottom outside of contact hole, in contact hole, fill metal closures; Boron-phosphorosilicate glass covers directly over source region N+ and good conductor; Metallic film covers directly over metal closures and boron-phosphorosilicate glass; Metal layer on back is overlying on the bottom of substrate layer; Good conductor forms the grid of field effect transistor tube body, and metallic film forms the source electrode of field effect transistor tube body, and metal layer on back forms the drain electrode of field effect transistor tube body.
6. have the field-effect transistor of build-up effect according to claim 5, it is characterized in that, the thickness of the oxide layer of channel bottom growth is thicker than the thickness of the oxide layer of trenched side-wall growth.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201410127294.4A CN104952731A (en) | 2014-03-31 | 2014-03-31 | Field effect transistor with accumulation effect and production method thereof |
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| CN201410127294.4A CN104952731A (en) | 2014-03-31 | 2014-03-31 | Field effect transistor with accumulation effect and production method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112490283A (en) * | 2019-09-11 | 2021-03-12 | 珠海格力电器股份有限公司 | Insulated gate structure, manufacturing method thereof and power device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5929481A (en) * | 1996-07-19 | 1999-07-27 | Siliconix Incorporated | High density trench DMOS transistor with trench bottom implant |
| CN1864270A (en) * | 2003-10-08 | 2006-11-15 | 丰田自动车株式会社 | Insulated-gate semiconductor device and its manufacturing method |
| CN102184960A (en) * | 2011-04-22 | 2011-09-14 | 上海宏力半导体制造有限公司 | Power metal oxide semiconductor field-effect tube and forming method thereof |
| CN103515245A (en) * | 2013-09-30 | 2014-01-15 | 桂林斯壮微电子有限责任公司 | Channel voltage dividing field effect tube and production method based on high-energy ion implantation mode |
-
2014
- 2014-03-31 CN CN201410127294.4A patent/CN104952731A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5929481A (en) * | 1996-07-19 | 1999-07-27 | Siliconix Incorporated | High density trench DMOS transistor with trench bottom implant |
| CN1864270A (en) * | 2003-10-08 | 2006-11-15 | 丰田自动车株式会社 | Insulated-gate semiconductor device and its manufacturing method |
| CN102184960A (en) * | 2011-04-22 | 2011-09-14 | 上海宏力半导体制造有限公司 | Power metal oxide semiconductor field-effect tube and forming method thereof |
| CN103515245A (en) * | 2013-09-30 | 2014-01-15 | 桂林斯壮微电子有限责任公司 | Channel voltage dividing field effect tube and production method based on high-energy ion implantation mode |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112490283A (en) * | 2019-09-11 | 2021-03-12 | 珠海格力电器股份有限公司 | Insulated gate structure, manufacturing method thereof and power device |
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