CN104916597A - Wafer-level fan-out chip packaging method and packaging structure - Google Patents
Wafer-level fan-out chip packaging method and packaging structure Download PDFInfo
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- CN104916597A CN104916597A CN201410097812.2A CN201410097812A CN104916597A CN 104916597 A CN104916597 A CN 104916597A CN 201410097812 A CN201410097812 A CN 201410097812A CN 104916597 A CN104916597 A CN 104916597A
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- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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Abstract
The invention provides a wafer-level fan-out chip packaging method and a packaging structure. The wafer-level fan-out chip packaging method comprises the following steps: providing a carrier and equipping a plurality of chips on the carrier; forming a plurality of adhesion layers on active surfaces of the corresponding chips respectively; covering a conductive cover body to enable the conductive cover body to be bonded with the chips through the adhesion layers, the conductive cover body separating the chips into a plurality of packaging spaces respectively; filling insulating materials into the packaging spaces via a plurality of through holes in the conductive cover body to form a first insulation structure; and removing the carrier.
Description
Technical field
The invention relates to a kind of method for packing and structure of chip, and relate to a kind of method for packing and encapsulating structure of wafer scale fan-out chip especially.
Background technology
Along with the universalness of electronic product, the electronic product of portable and Wearable become people live in indispensable instrument.And exploitation has high-effect, small size, high arithmetic speed, high-quality and multi-functional electronic product and element, the trend necessitated.With regard to outward appearance, light, thin, short, little electronic product becomes inevitable trend, and in order to coordinate the requirement of trend, one of selection that the packaging technology of wafer scale (Wafer Level Chip Scale Package is called for short WLCSP) necessitates.
Wafer-level packaging and the main difference of traditional encapsulation technology are: the concept of wafer-level packaging is the encapsulation directly completing integrated circuit on wafer, but not carries out encapsulation procedure for other chip after cutting.By the encapsulation of wafer scale, the size of the chip after encapsulation and crystal grain original measure-alike.And the size of such wafer-level packaging can limit the scope of layout fan-out (Fan-Out).
Summary of the invention
The invention provides a kind of method for packing and encapsulating structure of wafer scale fan-out chip, object is to provide that a kind of packaging cost is low, product packaging body thickness is thin, mechanical support ability enhancement, there is great heat radiation effect, improve wafer level fan-out chip package structure and the method for packing in product useful life.
The method for packing of wafer scale fan-out chip of the present invention comprises: provide a carrier, and configure multiple chip on this carrier; Form multiple adhesion layer on an active surface of those chips corresponding; Cover a conductive cover, conductive cover is binded by those adhesion layers and those chips, and this conductive cover separates those chips respectively in multiple encapsulated space; Make insulating material by the multiple perforations in this conductive cover, insert those encapsulated spaces and form the first insulation system; And remove this carrier.
The present invention separately proposes a kind of encapsulating structure of wafer scale fan-out chip, comprises conductive plate, a chip, the first insulation system, the second insulation system and multiple weld pad.This conductive plate has supporting part and at least one jut, and chip is sticked together on this supporting part by an adhesion layer.This first insulation system is centered around the surrounding of this chip with on supporting part.This second insulation system isolates multiple electrode window respectively.Those weld pads are configured in those electrode windows respectively to form multiple electrode.
Based on above-mentioned, method for packing of the present invention, by the mode sucking (or inserting), around coating chip complete for insulating material, can reduce the thickness of product packaging body, improves the reliability of the chip after encapsulation.Further, by the method for packing of wafer scale of the present invention, the chip after encapsulation can be tested by the tester table of wafer scale, significantly reduces complexity and the packaging cost of production procedure
Should be understood that above general description and following detailed description are all exemplary, and desirable to provide to as the of the present invention further explanation of advocating.
Accompanying drawing explanation
Comprise accompanying drawing to provide a further understanding of the present invention, and accompanying drawing to be incorporated in this specification and to form the part of this specification.Accompanying drawing illustrates embodiments of the invention, and together with the description in order to explain principle of the present invention.
Fig. 1 is the flow chart of the method for packing of the wafer scale fan-out chip of one embodiment of the invention;
Fig. 2 A ~ Fig. 2 K is the implementation detail schematic diagram of the method for packing of the wafer scale fan-out chip of the embodiment of the present invention.
Fig. 3 A is encapsulating structure 300 stereogram of the wafer scale fan-out chip of one embodiment of the invention;
Fig. 3 B is the profile of encapsulating structure 300 line segment B-B ';
Fig. 3 C is the profile of the wafer scale fan-out chip packaging structure of another embodiment of the present invention;
Fig. 4 A ~ Fig. 4 C is the schematic diagram of the application of the encapsulating structure of the embodiment of the present invention.
Description of reference numerals:
S110 ~ S160: the step of method for packing;
210: carrier;
211: stripping film adhesive tape;
221 ~ 222,321: chip;
231,232: adhesion layer;
240: conductive cover;
241: dividing plate;
300,410,420: encapsulating structure;
340: conductive plate;
370: adhesion coating;
400: power-switching circuit;
T1, T2: side;
H1, H2: perforation;
Z1, Z2: encapsulated space;
PM: the first insulation system;
GP: glass substrate;
PL: the second insulation system;
W1 ~ WN: electrode window;
PAD1 ~ PADN: weld pad;
BA1 ~ BAN: soldered ball;
A-A ', B-B ': line segment;
3401: supporting part;
3402: jut;
M1 ~ M5: transistor;
DC: drain electrode;
S1, S2: source electrode;
G1, G2: grid;
D1: diode;
L1, L2: inductance;
GND: earth terminal;
C1: electric capacity.
Embodiment
With detailed reference to the preferred embodiments of the present invention, the example is illustrated in the accompanying drawings.Same reference numbers is in the accompanying drawings and the description in order to refer to same or similar part.
One embodiment of its manufacturing process and method refers to Fig. 1, and Fig. 1 is the flow chart of the method for packing of the wafer scale fan-out chip of one embodiment of the invention.It is the implementation detail schematic diagram of the method for packing of the wafer scale fan-out chip of the embodiment of the present invention referring to Fig. 2 A ~ Fig. 2 K.In Fig. 1 and Fig. 2 A, in step S110, provide a carrier 210, carrier 210 surface coverage stripping film adhesive tape 211.In the present embodiment, carrier 210 can be a round carrier consistent with wafer size, such as 6 inches, 8 inches or the disk of 12 inches.And in material, 210, carrier can by such as made by the material such as metal, metal alloy, plastics or quartz glass.Carrier 210 can be that the material of conduction or insulation formed.211, stripping film adhesive tape can be the adhesive tape of biadhesive.
Then, in the step s 120, then by multiple chip configuration that wafer cuts down on carrier 210.At this chip with the metal oxide semiconductor field effect transistor of vertical-type (Metal-Oxide-Semiconductor Field-Effect Transistor, be called for short MOSFET) be example, certainly other are as igbt (Insulated Gate Bipolar Transistor, be called for short IGBT), bipolar junction transistor (Bipolar Junction Transistor, be called for short BJT), diode (Diode) etc. is all possible apply, and its chips first active surface can design and comprise source electrode, grid two electrodes.Chip back, namely the second active surface design is as drain electrode.Wherein, in fig. 2b, chip 221 ~ 222 is configured in carrier 210, and the first active surface of chip 221 ~ 222 contacts to bind with stripping film adhesive tape 211.In step s 130, which, formed on the second active surface of 221 ~ 222 of multiple chips of multiple adhesion layer on corresponding carrier 210.Adhesion layer 231 and 232 such as shown in Fig. 2 C.
About the formation method of adhesion layer 231 and 232, can utilize a glue or half tone coating method, will have the adhesion layer 231 and 232 of conductivity, appropriate is placed on the second active surface of chip 221 ~ 222 respectively.Adhesion layer 231 and 232 can be the conduction materials such as elargol, tin cream or copper cream.
In step S140, then cover conductive cover 240 above chip 221 ~ 222 and carrier 210, chip 221 ~ 222, by dividing plate 241, separates in multiple encapsulated space Z1 and Z2 by conductive cover 240 respectively.Conductive cover 240 produces with chip 221 ~ 222 respectively by adhesion layer 231 and 232 and is electrically connected.Further, the first side T1 of conductive cover 240 has multiple dividing plate 241.Above-mentioned conductive cover 240 can be circular metal frame, and can be formed by the material of the tool electrical conductivity characteristics such as copper, iron nickel.Conductive cover 240 can according to Customer Requirement Design shape and size, and use the mode of etching or punch die to manufacture.Conductive cover 240 can coordinate the wafer of the chip 221 ~ 222 that will encapsulate and be made as the disk of 6 inches, 8 inches or 12 inches, maybe can be made as tabular.For example, conductive cover 240 can made by the thick alcu alloy film of 25um to 100um.
In addition, dividing plate 241 can lead to overetched mode to be formed, the plane that dividing plate 241 contacts with stripping film adhesive tape 211, then can with the second active surface copline of chip 221 ~ 222.Corresponding adjustment is carried out in the position that the position that dividing plate 241 is formed and thickness then can be configured on stripping film adhesive tape 211 according to chip 221 ~ 222.In conductive cover 240, multiple dividing plate 241 can the webbed structure of shape be separated out multiple array arrangement encapsulated space.
In step S150, by insulating material by the multiple hole for injecting glue in conductive cover or perforation, insert empty Z1, the Z2 left by encapsulated space, form the first insulation system.Please jointly with reference to Fig. 1 and Fig. 2 E, perforation H1 and H2 can be formed respectively in the position of corresponding encapsulated space Z1 and Z2 in conductive cover 240, please refer to Fig. 2 F again, by providing the insulating material of liquid, be received in or be sucked in encapsulated space Z1 and Z2 to make insulating material PM by perforation H1 and H2, the insulating material be inhaled in one embodiment will fill up encapsulated space Z1 and Z2, to form the first insulation system PM.In addition, after insulating material fills up encapsulated space Z1 and Z2, and action is cured to the first insulation system PM.
Insulating material can be insulator die moulding material, and can be any suitable thermoplastic or thermosets, the such as resin of epoxy-based material, silica gel or photoresist etc.Insulating material after solidification forms multiple moulding bodies, and for providing the rigid structure of protect IC 221 ~ 222.Encapsulated space Z1 and Z2 is filled up completely for making insulating material, the embodiment of the present invention carries out the action vacuumized by perforation H1 and H2, and make encapsulated space Z1 and Z2 form vacuum state, apply liquid insulating material again above perforation H1 and H2, liquid insulating material effectively can be sucked in encapsulated space Z1 and Z2, and fill up encapsulated space Z1 and Z2.Thus, the moulding bodies that the insulating material after solidification produces will cause structure not firm because including multiple hole, and promote the reliability of encapsulation.
Then, in step S160, then carrier 210(is removed as shown in Figure 2 G).Wherein, removing of carrier 210 is reached by removing stripping film adhesive tape 211.It should be noted that shown in Fig. 2 G, the structure of the plastic packaging disk completed by above-mentioned technique is smooth, does not have warpage or blocked up and excessive glue problem, need not carry out thinning and cleaning, effectively reduces the complexity of method for packing.
Then, in the part of the electrode generation type about the rear chip of encapsulation, please refer to Fig. 2 H ~ Fig. 2 J.In Fig. 2 H, the conductive cover 240 of the plastic packaging disk completed is combined with glass substrate GP, makes glass substrate GP directly contact the second side T2 of conductive cover 240.
And be coated with one deck polymer dielectric material to form an insulating barrier at chip 221 ~ 222 first active surface, this insulating barrier object is the intensity increasing passivation layer (passivation), to chip formation insulation insulation blocking to a certain extent.Then multiple electrode window W1 ~ WN is formed on the insulating layer by part etching mode, wherein electrode window W1 ~ WN as follow-up drain electrode, source electrode with gate contact window, and remain insulating barrier part and be formed at surface except electrode window W1 ~ WN position, electrode window W1 ~ WN is done by the second insulation system PL respectively and isolates.In the part that electrode window W1 ~ WN is formed at chip 221 ~ 222 first active surface with dividing plate on 241 part on, on the part that the second insulation system PL also covers chip 221 ~ 222 first active surface and dividing plate 241 part.Electrode window W1 ~ WN is used for the expose portion of the first active surface of contact chip 221 ~ 222 part and dividing plate 241 expose portion.On these surfaces of exposing, namely in electrode window W1 ~ WN, then can form multiple weld pad PAD1 ~ PADN respectively, this weld pad is called projection underlying metal UBM, uses as follow-up liner ball or the intermetallic connection of projection operation.
In Fig. 2 I, then form multiple soldered ball BA1 ~ BAN respectively on weld pad PAD1 ~ PADN, and form multiple electrode.Wherein, soldered ball BA1 can as the drain electrode of the transistor in chip 221, and soldered ball BA2 and BA3 then respectively can as the grid of transistor and source electrode.Complete and plant ball and be correlated with after operation, remove glass substrate GP, as Fig. 2 J.
Can be learnt by Fig. 2 J, multiple chip 221 ~ 222 completes encapsulation in the mode of wafer scale, and when testing chip 221 ~ 222 chip after encapsulation, the packaging body of the wafer scale of Fig. 2 J can be utilized to complete test by the test machine of wafer scale.So naked brilliant pin can be utilized to survey (Chip Probing is called for short CP) by the electrical standard specification of the crystal grain on chip according to design, survey mode with pin and detect to carry out disposable test, significantly reduce testing cost and the time needed for test.Can certainly well cutting, finished product test is carried out to the assembly be separated.
The position of the final line segment A-A ' according to Fig. 2 J is cut, and institute obtains the encapsulating structure after cutting as shown in figure 2k.In Fig. 2 K, first active surface and the conductive cover 240 of chip 221 are electrically connected, and by soldered ball BA1 to form the drain electrode of transistor in chip 221, the second active surface of chip 221 is then electrically connected to soldered ball BA2 and BA3 and forms grid and the source electrode of transistor in chip 221 respectively.
Please be synchronously below the stereogram of the encapsulating structure 300 of the wafer scale fan-out chip of one embodiment of the invention with reference to Fig. 3 A and Fig. 3 B, Fig. 3 A, Fig. 3 B be the profile of encapsulating structure 300 line segment B-B '.Encapsulating structure 300 is the encapsulating structures produced according to the method for packing of Fig. 1 embodiment of the present invention.Wherein, encapsulating structure 300 comprises conductive plate 340, cuts multiple one of them, chip 321, first insulation system PM, the second insulation system PL and multiple soldered ball BA1 ~ BA3 by conductive cover 240.Conductive plate 340 has supporting part 3401 and jut 3402 (corresponding 2H figure dividing plate 241), and supporting part 3401 and jut 3402 contact with each other.Wherein, supporting part 3401 is used for carries chips 321, and jut 3402 is then used for forming soldered ball BA1.
Chip 321 sticks together on supporting part 3401 by adhesion layer 370, and adhesion layer 370 is can the adhesion material of conductive material, and chip 321 is connected with conductive plate 340 electronics by adhesion layer 370.First insulation system PM is then centered around the surrounding of chip 321 and covers supporting part 3401 and do not contact with the upper surface of chip 321.Second insulation system PL isolates multiple electrode window (W1 ~ WN with reference to 2H), and the second insulation system PL cover segment chip 321 active surface on on the jut 3402 of partially conductive plate 340, as for the first insulation system PM because electrodeless window exists, therefore the second insulation system PL can cover the first insulation system PM completely.Multiple electrode window touches chip 321.And jut 3402 has multiple electrode window equally.Above-mentioned electrode window is used for forming soldered ball BA1 ~ BA3, and wherein, soldered ball BA1 is configured in the electrode window on jut 3402, and soldered ball BA2, BA3 are then configured in the electrode window on chip 321.In the present embodiment, soldered ball BA1 can be used as the drain electrode of transistor in chip 321, and soldered ball BA2 can be used as the grid of transistor in chip 321, and soldered ball BA3 then can be used as the source electrode of transistor in chip 321.
The the first insulation system PM that it should be noted that in the embodiment of the present invention is by originally for liquid kenel injects the space existing for it, and the insulating material of liquid towards kenel performs the action of solidification.The upper surface of the first insulation system PM after solidification can be used for being formed the upper surface of soldered ball BA1 on the same plane with the jut 3402 of conductive plate 340.Thus, the first insulation system PM after solidification can form firm structure at encapsulating structure 300, effectively reaches effect of protect IC 321.
Corresponding aforementioned about in the embodiment of method for packing, the jut 3402 of the present embodiment is the dividing plate in previous embodiment in conductive cover.The conductive plate 340 of the present embodiment is conductive cover in previous embodiment or segmentation rear portion.And the first insulation system PM is the state after solidification.
The present embodiment uses metal to be connected in chip drain metal layer, except strengthening mechanical strength, can also radiating effect be increased, can be connected on printed circuit board (PCB) (Printed Circuit Board is called for short PCB) in addition, utilize the Copper Foil on printed circuit board (PCB), further reduction thermal resistivity, improves product useful life, also because drain electrode connection metal, thinner chip can be applicable to, as the size of 50um or less.Fig. 3 C is the profile of the wafer scale fan-out chip packaging structure of another embodiment of the present invention.Therefore as Fig. 3 C, this application can insert the MOSFET of two identical or different sizes.
About chip 321, can refer to Fig. 4 A ~ Fig. 4 C, Fig. 4 A ~ Fig. 4 C is the schematic diagram of the application of the encapsulating structure of the embodiment of the present invention.Wherein, in Figure 4 A, chip 321 can comprise one or more transistor M1 and M2.Wherein, the drain D C of transistor M1 and M2 is interconnected, and form electrode by soldered ball BA1, and the source S 1 of transistor M1 and M2 and S2 can form two mutually isolated source electrodes respectively by different soldered ball BA3, and the grid G 1 of transistor M1 and M2 and G2 can form two mutually isolated grids respectively by different soldered ball BA1.
In figure 4b, encapsulating structure of the present invention also can be applicable in power-switching circuit.Wherein, the power-switching circuit 400 in Fig. 4 B comprises encapsulating structure 410.Chip in encapsulating structure 410 comprises transistor M3 and diode D1.The drain electrode of transistor M3 and the anode of diode D1 couple mutually by the conductive plate in encapsulating structure 410, and be connected to inductance L 1 by the electrode that corresponding soldered ball is formed, the electrode that the source electrode of transistor M3 can be formed by corresponding soldered ball is coupled to earth terminal GND, and the electrode that the grid of transistor M3 can be formed by the soldered ball of correspondence receives driving voltage, such as, it is the driving voltage of pulse-width modulation signal.In addition, the electrode that the negative electrode of diode D1 is also formed by the soldered ball of correspondence is coupled to electric capacity C1.
Fig. 4 C is the circuit of the encapsulating structure 420 with two transistor M4 ~ M5.In figure 4 c, the drain electrode that transistor M4 ~ M5 couples jointly is connected to inductance L 2 by the electrode on encapsulating structure 420, the grid of transistor M4 ~ M5 and source electrode then can receive required signal or voltage respectively by the electrode of correspondence, meet the demand of circuit running.
In sum, the present invention by by insulating material to suck or the mode inserted, make it be coated on around chip, use the reliability of the chip after improving encapsulation.Further, lower the complexity of production procedure by the method for packing of wafer scale and be packaged into, the competitiveness of effective improving product.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (10)
1. a method for packing for wafer scale fan-out chip, is characterized in that, comprising:
Carrier is provided;
Configure multiple chip on this carrier;
Form multiple adhesion layer on the active surface of those chips corresponding;
Cover conductive cover, this conductive cover is binded by those adhesion layers and those chips, and this conductive cover separates those chips respectively in multiple encapsulated space;
Make insulating material by multiple perforations of this conductive cover, insert those encapsulated spaces and form the first insulation system; And
Remove this carrier.
2. method for packing according to claim 1, is characterized in that, the first side of this conductive cover has multiple dividing plate, in order to separate out those encapsulated spaces.
3. method for packing according to claim 2, is characterized in that, also comprises after removing the step of this carrier:
There is provided glass substrate in the second side of this conductive cover;
Form multiple electrode window, and isolate respectively with the second insulation system; And
Form multiple weld pad in those electrode windows to form multiple electrode.
4. method for packing according to claim 3, is characterized in that, this second insulation system covers on those chips of part with on those dividing plates of part.
5. method for packing according to claim 1, is characterized in that, this insulating material is liquid, and makes this insulating material by those perforations, inserts those encapsulated spaces and forms this first insulation system.
6. method for packing according to claim 1, is characterized in that, forms the step of those adhesion layers on the surface of those chips and comprises:
Utilize the mode of some glue or half tone coating, this active surface of those chips is formed those adhesion layers, and those adhesion layers have conductivity.
7. an encapsulating structure for wafer scale fan-out chip, is characterized in that, comprising:
Conductive plate, has supporting part and at least one jut;
Chip, sticks together on this supporting part by adhesion layer;
First insulation system, is centered around the surrounding of this chip with on this supporting part;
Second insulation system, isolates multiple electrode window respectively; And
Multiple weld pad, is configured in those electrode windows respectively to form multiple electrode.
8. require the encapsulating structure of wafer scale fan-out chip described in 7 according to power, it is characterized in that, this second insulation system covers on those chips of part with on those dividing plates of part.
9. the encapsulating structure of wafer scale fan-out chip according to claim 7, it is characterized in that, the surface of this first insulation system and the surface of this jut are copline.
10. the encapsulating structure of wafer scale fan-out chip according to claim 7, it is characterized in that, those adhesion layers for having conductivity, and those chips be at least one metal oxide semiconductor field effect transistor, igbt, bipolar junction transistor, diode assembly and mutually combine.
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