CN104916548B - The preparation method of semiconductor device - Google Patents

The preparation method of semiconductor device Download PDF

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Publication number
CN104916548B
CN104916548B CN201410092528.6A CN201410092528A CN104916548B CN 104916548 B CN104916548 B CN 104916548B CN 201410092528 A CN201410092528 A CN 201410092528A CN 104916548 B CN104916548 B CN 104916548B
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pin
conducting strip
semiconductor chip
projection
conducting
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CN104916548A (en
Inventor
孙智信
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BAIRONG ELECTRONICS Co Ltd
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BAIRONG ELECTRONICS Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/77—Apparatus for connecting with strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/3701—Shape
    • H01L2224/37011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/8438—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/84385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

A kind of preparation method of semiconductor device, is comprised the steps of：(A) a pin unit by a framework positioning is provided, the pin unit has first pin and second pin separately set, and second pin has the limiting section of neighbouring first pin；(B) semiconductor chip is provided and the semiconductor chip is arranged on first pin and is electrically connected with；(C) conducting strip is provided and is electrically connected with second pin and the semiconductor chip, the conducting strip there is one by the limiting section of second pin can be engaged spacing be limited portion；(D) sealing program；And (E) by the pin unit and the framework apart.Engage the conducting strip by the limiting section of second pin so that predetermined installation site can not be deviateed when the conducting strip is installed because of slip, improve the yield of encapsulation.

Description

The preparation method of semiconductor device
Technical field
The present invention relates to a kind of preparation method of device, more particularly to a kind of preparation method of semiconductor device.
Background technology
The preparation method of existing semiconductor device, it is first two spaced pins of offer, then by a semiconductor Chip is disposed therein on a pin with being electrically connected with, and provides a conducting strip afterwards, and two opposite ends of the conducting strip are distinguished Be bonded and be electrically connected to the semiconductor chip and another pin on, finally carry out sealing program, complete semiconductor dress Put.
However, when the conducting strip carries out above-mentioned electric connection step, it is bad because of aligning accuracy, often make the conducting strip inclined From predetermined electric connection position, and cause faying surface too small, or even slide out the semiconductor chip and be connected to positioned at this partly On pin below conductor chip, short circuit is formed, yield declines.
Furthermore when being electrically connected with the conducting strip, be first the semiconductor chip and this do not place connecing for the semiconductor chip Point covers elargol on pin, after put the conducting strip and be placed into a reflow stove heat, the solid-state elargol thawing for making a little to cover and be covered with and take Junction, and then stick together the conducting strip.However, because the elargol that point covers is that solid-state point-like is presented, so inserting the behaviour of the reflow oven In work, the conducting strip being placed on elargol easily slides because rocking, and deviates predetermined lap position, causes faying surface too small, Even slide out elargol surface and be connected on the pin below the semiconductor chip, form short circuit.
In addition, when carrying out sealing program, a mould is put into after being the semi-finished product cooling that will be treated through reflow oven, then Irrigate sealing.But because the sealing of injection is fluid, there is the characteristic of flowing, may if the faying surface of the conducting strip is too small The sealing being injected into is promoted and separated, and destroys the stacked manner of script.
The preparation method of existing semiconductor device, because aligning accuracy and mode of operation it is therefore, often cause inter-module make a reservation for Stacked manner be destroyed, cause encapsulate yield it is bad the problem of.
The content of the invention
It is an object of the invention to provide a kind of system for the semiconductor device that can be improved the installation degree of accuracy, lift encapsulation yield Make method.
The preparation method of semiconductor device of the present invention, is comprised the steps of：(A) one is provided to be connect by what a framework positioned Pin unit.The pin unit has first pin and second pin separately set.First pin has one The supporting part of individual neighbouring second pin, and first Conducting end portions away from second pin.Second pin has one The connection end of individual neighbouring first pin, a limiting section on the connection end, and remote first pin The second Conducting end portions；(B) semiconductor chip is provided, the semiconductor chip is arranged on the supporting part of first pin And it is electrically connected with；(C) conducting strip is provided, the conducting strip is connected with second pin and the semiconductor chip.This is led Electric piece is located therein one end including one and fastens with the limiting section of second pin and be connected end with this to be electrically connected with Be limited portion, one positioned at the other end and the patch that is arranged on the semiconductor chip and is electrically connected with the semiconductor chip Conjunction portion, and one connect the sticking part and this is limited the connecting portion in portion.This is limited portion can be by the limiting section of second pin Engage it is spacing, without being moved along a first direction and a second direction.The first direction and the second direction are parallel to The upper surface of the connection end of second pin；(D) sealing program is carried out, by the part of the pin unit, the semiconductor chip, And the conducting strip is with a sealant covers, and make the first Conducting end portions of first pin and the second conducting end of second pin Expose outside the sealing in portion；And (E) by the pin unit and the framework apart.
It is preferred that vertical second direction of the first direction.
It is preferred that the portion of being limited of the conducting strip has a basal wall section being connected with the connecting portion, and one from the base Wall section upper surface downward through perforation, the limiting section of second pin is formed at the upper surface of the connection end and worn with this The projection that hole is engaged, the projection, which can be worn in the perforation, is limited the conducting strip, and makes the conducting strip not with this Projection rotates for axle center.
It is preferred that the portion of being limited of the conducting strip has a basal wall section being connected with the connecting portion, and one from the base For wall section in contrast to the projection that a side of the connecting portion extends downwardly, the limiting section of second pin is one from the connection end Upper surface allow the projection to wear into being limited the conducting strip downward through and with the perforation that is engaged of the projection, the perforation Position, and the conducting strip does not rotate by axle center of the projection.
It is preferred that the portion of being limited of the conducting strip has a basal wall section being connected with the connecting portion, two from the basal wall The two-phase of section is tossed about the side wall sections extended downwardly, and two are respectively formed in the side wall sections and are opened on the inverted U-shaped of lower side Neck, the limiting section of second pin be two and be respectively formed in the connection end two-phase and toss about the projection on side, the projection energy Being snapped into the inverted U-shaped neck respectively is limited the conducting strip.
It is preferred that the sticking part of the conducting strip has the fitting section and a warpage section being connected, when completion step When C), the fitting section is disposed on the semiconductor chip and in the range of the upper surface of the semiconductor chip, the warpage section It is the direction warpage from the fitting section toward the remote semiconductor chip, and is connected to the connecting portion of the conducting strip.
It is preferred that the preparation method of the semiconductor device is also contained in the step (F) after step (E), bend this The part that one pin and second pin are exposed to outside the sealing, make first Conducting end portions and second Conducting end portions adjacent respectively The nearly sealing surface.
The beneficial effects of the present invention are：Match by the limiting section of second pin and the portion of being limited of the conducting strip Close, the limiting section is engaged the spacing conducting strip, therefore can be without departing from predetermined installation site when installing the conducting strip, and make The mode of the survivable inter-module storehouse of operating procedure subsequently carried out, improve the yield of encapsulation.
Brief description of the drawings
Fig. 1 is a process block diagram, illustrates a first embodiment of the preparation method of semiconductor device of the present invention；
Fig. 2 is a schematic diagram, illustrates that a semiconductor chip of the first embodiment is arranged at a pin by elargol On one the first pin of unit；
Fig. 3 is a schematic diagram, illustrates that a conducting strip of the first embodiment is arranged on the pin unit；
Fig. 4 is side view diagram, illustrates the conducting strip of the first embodiment and the electric connection mode of the semiconductor chip；
Fig. 5 is a schematic diagram, illustrates the sealant covers mode of the first embodiment and by the pin unit and a framework Separation；
Fig. 6 is side view diagram, illustrates the bending mode of the pin unit of the first embodiment；
Fig. 7 is a three-dimensional exploded view, illustrates another embodiment aspect of the conducting strip；
Fig. 8 is a three-dimensional exploded view, illustrates another embodiment aspect of the conducting strip；
Fig. 9 is a process block diagram, illustrates a second embodiment of the preparation method of semiconductor device of the present invention；
Figure 10 (a) is a schematic diagram, illustrates that multiple pin units are connected with multiple semiconductor chips in the second embodiment；
Figure 10 (b) is a schematic diagram, illustrates that multiple conducting strips are by multiple sucker suctions and displacement in the second embodiment.
Embodiment
Below in conjunction with the accompanying drawings and embodiment the present invention is described in detail.
Before the present invention is described in detail, it shall be noted that in the following description content, similar component is with identical Number to represent.
Refering to Fig. 1, for a first embodiment of the preparation method of semiconductor device of the present invention, step includes：Step (A) 100 provide a pin unit by a framework positioning.Step (B) 200 provides a semiconductor chip, by the semiconductor core Piece is arranged on one of pin of the pin unit and is electrically connected with.Step (C) 300 provides a conducting strip, and this is led It is electrically connected with mutually between another pin and the semiconductor chip of electric piece and the pin unit.Step (D) 400 carries out sealing journey Sequence.Step (E) 500 is by the pin unit and the framework apart.Step (F) 600 bends program.Then, then by above steps After being specified in.
Refering to Fig. 1, Fig. 2 and Fig. 3, the step (A) 100 provides a pin unit 2 positioned by a framework 1.This connects Pin unit 2 has first pin 21 and second pin 22 separately set.First pin 21 has a neighbour The supporting part 211 of nearly second pin 22, and first Conducting end portions 212 away from second pin 22.Second pin 22 have the 221, limiting sections 222 on the connection end 221 in connection end of neighbouring first pin 21, and One the second Conducting end portions 223 away from first pin 21.First Conducting end portions 212 and second Conducting end portions 223 are It is connected with the framework 1 and is fixed and positioned.
It is noted that the present embodiment is that a metal substrate is first defined into the framework 1 after hollow out and compacting And the pin unit 2, or such as existing casting method, the framework 1 can be produced and by the framework in a manner of integrally formed The pin unit 2 of 1 positioning.The framework 1 and the pin unit 2 also must be the component of separation, after it is again that the pin unit 2 is fixed Positioned on the framework 1.The positioning method of the pin unit 2, it ought to not be limited with this preferred embodiment disclosure of that System.
The step (B) 200 is to provide a semiconductor chip 3, and point covers silver on the supporting part 211 of first pin 21 Glue, then the semiconductor chip 3 is positioned on elargol, rear heating and melting elargol forms a first elargol layer 5, makes the semiconductor Chip 3 by the first elargol layer 5 and bind is arranged on the supporting part 211 of first pin 21, and with first pin 21 It is electrically connected with.
Refering to Fig. 1, Fig. 3 and Fig. 4, the step (C) 300 is to provide a conducting strip 4, and in the upper of the semiconductor chip 3 Point covers elargol respectively for surface and the connection end 221 of second pin 22, is adsorbed followed by a sucker 10 and mobile this is led Electric piece 4, and its two opposite ends portion is arranged on the elargol of the connection end 221 and the semiconductor chip 3 respectively.By the conduction Piece 4 is moved on second pin 22 and the semiconductor chip 3, except use above-mentioned sucker 10, also can be used other clamp or Adsorption plant is reached.
After the conducting strip 4 is placed on elargol, the good said modules of storehouse are inserted into a reflow oven (not shown) heating, The solid-state elargol for making a little to cover melts, and in one the second elargol layer 6 of formation on the semiconductor chip 3, and in second pin A the 3rd elargol layer 7 is formed on 22 connection end 221.The second elargol layer 6 and the 3rd elargol layer 7 are by the conducting strip 4 It is electrically connected with second pin 22 and the semiconductor chip 3.
The conducting strip 4 be located therein one end including one and fastened with the limiting section 222 of second pin 22 and with What the connection end 221 was electrically connected be limited 41, one, portion positioned at the other end and be arranged on the semiconductor chip 3 and with The sticking part 42 that the semiconductor chip 3 is electrically connected with, and one connect the sticking part 42 and this is limited the connecting portion 43 in portion 41.
This, which is limited portion 41, has a basal wall section 411 being connected with the connecting portion 43, and one from the basal wall section 411 Surface downward through rectangular through-holes 412.The limiting section 222 of second pin 22 is formed at the upper table of the connection end 221 Face, and a rectangular cam 224 being engaged with the perforation 412.
When the conducting strip 4 is adsorbed by the sucker 10 and is moved to the top of the pin unit 2, make the perforation of the conducting strip 4 412 are directed at the projection 224 of second pin 22, after move sucker 10 again and the projection 224 is worn in the perforation 412, The conducting strip 4 is limited to move without direction of the edge parallel to the upper surface of the connection end 221 of second pin 22, and not Rotated with the projection 224 for axle center.Define a first direction X and a second direction Y is parallel to the connection of second pin 22 The upper surface of end 221, and be mutually perpendicular to.Though it should be noted that in this embodiment perforation 412 with projection 224 using rectangle as Example, but both shapes only need for the non-circular of mutual cooperation, to allow be formed interfering and can not rotate against between the two.
When the conducting strip 4 is spacing by the projection 224, the conducting strip 4 is set not slid because elargol appearance is in curved surface, and together When the conducting strip 4 sticking part 42 be to be limited to the upper surface of the semiconductor chip 3, the sticking part 42 is placed in this Elargol on semiconductor chip 3.Now, the good said modules of storehouse are inserted into the reflow stove heat, makes the solid-state elargol a little covered Melt simultaneously gluing conducting strip 4.
The sticking part 42 has the fitting section 421 and a warpage section 422 being connected, and the fitting section 421 is by this Second elargol layer 6 binds and is arranged on the semiconductor chip 3, and in the range of the upper surface of the semiconductor chip 3.This sticks up Tune 422 is the direction warpage from the fitting section 421 toward the remote semiconductor chip 3, and is connected to the connecting portion of the conducting strip 4 43, the part being at least connected with the fitting section 421 in the warpage section 422 is spaced on the upper surface of the semiconductor chip 3.
When the fitting section 421 is pressed on the point-like elargol on the semiconductor chip 3, the elargol melted by heating is squeezed The periphery flowing of pressure and the past semiconductor chip 3, excessive elargol can be placed in the warpage section 422 and the semiconductor chip 3 It in the accommodation space 40 that upper surface is defined, therefore will not produce because elargol overflow is to first pin 21, and cause this The short circuit problem that conducting strip 4 is electrically connected with first pin 21.
Refering to Fig. 1 and Fig. 5, the step (D) 400 is to insert the component for completing step (C) 300 in one mould (not shown), after pour into sealing 8 again and coat the part of the pin unit 2, the semiconductor chip 3, and the conducting strip 4, make First Conducting end portions 212 of first pin 21 and the second Conducting end portions 223 of second pin 22 expose outside the sealing 8.
After completion pours into the step of sealing 8, the sealing 8 is solidified, then by by the component that the sealing 8 coats from the mould Middle (not shown) is taken out.Any existing mode can be used to complete for this sealing program, ought to not be with disclosed in this preferred embodiment Content for limitation.
The step (E) 500 is cut for the finished product for being completed the step (D) 400, makes the pin unit 2 and the frame Frame 1 separates, and forms a semiconductor device semi-finished product.Any existing mode can be used to complete for this separating step, ought to not be with The present embodiment disclosure of that is limitation.
Refering to Fig. 1 and Fig. 6, the step (F) 600 be by first pin 21 of the semiconductor device semi-finished product and this second The part that pin 22 exposes to the sealing 8 is bent, and distinguishes first Conducting end portions 212 and second Conducting end portions 223 The neighbouring surface of sealing 8, that is, complete a semiconductor device.Any existing mode can be used to complete for this bending program, ought to Not using this preferred embodiment disclosure of that as limitation.
It is noted that there be two kinds of realities in the limiting section 222 of second pin 22 and the portion 41 that is limited of the conducting strip 4 Apply aspect.
Refering to Fig. 7, in another embodiment aspect of the conducting strip 4, the conducting strip 4 is limited portion 41 with one and the company The connected basal wall section 411 of socket part 43, and one from the basal wall section 411 in contrast to the square that a side of the connecting portion 43 extends downwardly Shape projection 413, the projection 413 can also be formed at the lower surface of the basal wall section 411.The limiting section 222 of second pin 22 is one It is individual from the upper surface of the connection end 221 downward through and with the rectangular through-holes 225 that are engaged of the projection 413.The perforation 225 is held Perhaps the projection 413 is worn into being limited the conducting strip 4, and without along first direction X and second direction Y displacements, and this is led Electric piece 4 is not rotated with the projection 413 for axle center.
Refering to Fig. 8, in another embodiment aspect of the conducting strip 4, the conducting strip 4 is limited portion 41 with one and the company The connected basal wall section 411, two of socket part 43 is tossed about the side wall sections 414 extended downwardly, and two points from the two-phase of the basal wall section 411 The side wall sections 414 are not formed at and are opened on the inverted U-shaped neck 415 of lower side.The limiting section 222 of second pin 22 is two The individual projection 226 for being respectively formed in the 221 liang of opposite lateral sides in connection end.The projection 226 can be snapped into described inverted U-shaped respectively Neck 415 is limited the conducting strip 4, without along first direction X and second direction Y displacements.
It is by first embodiment of the invention for the second embodiment of the present invention refering to Fig. 9, Figure 10 (a) and Figure 10 (b) For mass producing.From first embodiment major difference is that the quantity of provided component is different, remaining is grasped the present embodiment It is all identical to make means.
The step of the present embodiment, includes：(A) multiple pin units 2 positioned by a framework 1 are provided.(B) provide multiple Semiconductor chip 3, each semiconductor chip 3 are arranged on one of pin of each pin unit 2 and are electrically connected with. (C) multiple conducting strips 4 are provided, by another pin in each conducting strip 4 and each pin unit 2 and located at the pin It is electrically connected with mutually between semiconductor chip 3 on unit 2.(D) sealing program is carried out.(E) by the pin unit 2 and the framework 1 separation.(F) program is bent.
The pin unit 2, the semiconductor chip 3, and the structure of the conducting strip 4 and the complete phase of the first embodiment Together.
To be adsorbed with multiple suckers 10 and the mobile conducting strip 4 when step (C) is carried out, make each conducting strip 4 with Second pin 22 of each pin unit 2 and the semiconductor chip 3 being arranged on the first pin 21 are aligned and are electrically connected with. The conducting strip 4 is moved on second pin 22 and the semiconductor chip 3, except using above-mentioned sucker 10, it also can be used He clamps or adsorption plant is reached.
The sucker 10 can adsorb the conducting strip 4 in a manner of a row or a row, can also be arranged in an array to adsorb The conducting strip 4, also any of which of conducting strip 4 can sequentially be adsorbed with single individual sucker 10 to carry out step (C).
When adsorbing the conducting strip 4 using row, row or the sucker 10 of array form, the conducting strip 4 is can be with One framework 1 ' positions, and facilitates the sucker to position and adsorb.Wherein, the conducting strip 4 is to be passed through with a metal substrate The framework 1 ' and the conducting strip 4 are defined after hollow out and compacting, or can be poured in a manner of integrally formed Ru existing Casting, produce the framework 1 ' and the conducting strip 4 positioned by the framework 1 '.The framework 1 ' and the conducting strip 4 also must be The component of separation, after the conducting strip 4 be fixedly arranged on the framework 1 ' again and positioned.
Other modes of operation, such as：The mode of electric connection, sealing program, with the side of framework 1 from mode, and bending program, It is all identical with the first embodiment.
The present embodiment is to be used to mass produce by the method shown in the first embodiment.Because the conducting strip 4 can quilt The limiting section 222 of second pin 22 is spacing, so under large production, can also there is accurate positioning, and is not easy because shaking Move and be destroyed the storehouse between said modules, improve the yield of encapsulation.
In summary, it is engaged, makes with the portion 41 that is limited of the conducting strip 4 by the limiting section 222 of second pin 22 The limiting section 222 engages the spacing conducting strip 4, therefore can be without departing from predetermined installation site when installing the conducting strip 4, and makes The mode of the survivable inter-module storehouse of operating procedure subsequently carried out, therefore the purpose of the present invention can be reached really.

Claims (6)

  1. A kind of 1. preparation method of semiconductor device, it is characterised in that：The preparation method of the semiconductor device comprises the steps of： (A) a pin unit by the positioning of framework is provided, the pin unit have first pin separately setting and One the second pin, first pin have a supporting part of neighbouring second pin, and one away from second pin There is one to be located at adjacent to the connection end of first pin, one on the connection end for first Conducting end portions, second pin Limiting section, and second Conducting end portions away from first pin；(B) a semiconductor chip is provided, by the semiconductor Chip is arranged on the supporting part of first pin and is electrically connected with；(C) provide a conducting strip, by the conducting strip and this second Pin and the semiconductor chip are connected, the conducting strip including one be located therein one end and with the limiting section of second pin Fasten and with this be connected end electric connection be limited portion, one positioned at the other end and being arranged on the semiconductor chip And the sticking part being electrically connected with the semiconductor chip, and one connect the sticking part and this is limited the connecting portion in portion, the quilt Limiting section can be spacing by the limiting section engaging of second pin, without the upper surface along the connection end parallel to second pin Direction movement；(D) sealing program is carried out, by the part of the pin unit, the semiconductor chip, and the conducting strip with an envelope Glue coats, and the first Conducting end portions of first pin and the second Conducting end portions of second pin is exposed outside the sealing；And (E) by the pin unit and the framework apart.
  2. 2. the preparation method of semiconductor device according to claim 1, it is characterised in that：The portion's of being limited tool of the conducting strip Have a basal wall section being connected with the connecting portion, and one from the basal wall section upper surface downward through perforation, second pin A limiting section projection being formed at the upper surface of the connection end and be engaged with the perforation, the projection can be worn into should It is limited the conducting strip in perforation, and the conducting strip is not rotated by axle center of the projection.
  3. 3. the preparation method of semiconductor device according to claim 1, it is characterised in that：The portion's of being limited tool of the conducting strip There is a basal wall section being connected with the connecting portion, and one extends downwardly from the basal wall section in contrast to a side of the connecting portion Projection, the limiting section of second pin be one from the upper surface of the connection end downward through and with wearing of being engaged of the projection Hole, the perforation allow the projection to wear into being limited the conducting strip, and the conducting strip does not rotate by axle center of the projection.
  4. 4. the preparation method of semiconductor device according to claim 1, it is characterised in that：The portion's of being limited tool of the conducting strip There are the basal wall section being connected with the connecting portion, two two-phases from the basal wall section to toss about the side wall sections extended downwardly, and two It is respectively formed in the side wall sections and is opened on the inverted U-shaped neck of lower side, the limiting section of second pin is two difference shapes Into the projection on side of being tossed about in the connection end two-phase, the projection, which can be snapped into the inverted U-shaped neck respectively, makes the conducting strip quilt It is spacing.
  5. 5. the preparation method of semiconductor device according to claim 1, it is characterised in that：The sticking part of the conducting strip has A fitting section being connected and a warpage section, when completing step (C), the fitting section is disposed on the semiconductor chip And in the range of the upper surface of the semiconductor chip, the warpage section is from the fitting section toward the direction away from the semiconductor chip Warpage, and it is connected to the connecting portion of the conducting strip.
  6. 6. the preparation method of semiconductor device according to claim 1, it is characterised in that：The making side of the semiconductor device Method is also contained in the step (F) after step (E), bends the portion that first pin and second pin are exposed to outside the sealing Point, make first Conducting end portions and second Conducting end portions respectively adjacent to the sealing surface.
CN201410092528.6A 2014-03-13 2014-03-13 The preparation method of semiconductor device Active CN104916548B (en)

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EP3503178A1 (en) * 2017-12-20 2019-06-26 Nexperia B.V. Semiconductor package and method of manufacture
EP3761358A1 (en) * 2019-07-02 2021-01-06 Nexperia B.V. A lead frame assembly for a semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1708206A (en) * 2004-06-09 2005-12-14 Nec化合物半导体器件株式会社 Chip-component-mounted device and semiconductor device
TWM399518U (en) * 2010-10-01 2011-03-01 Ceramate Technical Co Ltd Electric connector with semiconductor type anti-surge and -electrostatic functions

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JP2003273311A (en) * 2002-03-19 2003-09-26 Seiko Epson Corp Semiconductor device and manufacturing method therefor, circuit substrate, and electronic apparatus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1708206A (en) * 2004-06-09 2005-12-14 Nec化合物半导体器件株式会社 Chip-component-mounted device and semiconductor device
TWM399518U (en) * 2010-10-01 2011-03-01 Ceramate Technical Co Ltd Electric connector with semiconductor type anti-surge and -electrostatic functions

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