CN104916548A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- CN104916548A CN104916548A CN201410092528.6A CN201410092528A CN104916548A CN 104916548 A CN104916548 A CN 104916548A CN 201410092528 A CN201410092528 A CN 201410092528A CN 104916548 A CN104916548 A CN 104916548A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/77—Apparatus for connecting with strap connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/3701—Shape
- H01L2224/37011—Shape comprising apertures or cavities
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/4005—Shape
- H01L2224/4009—Loop shape
- H01L2224/40095—Kinked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/8438—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/84385—Shape, e.g. interlocking features
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention discloses a semiconductor device manufacturing method, which comprises the following steps: (A) a pin unit positioned by a frame is provided, wherein the pin unit comprises a first pin and a second pin arranged at an interval, and the second pin is provided with a limiting part near the first pin; (B) a semiconductor chip is provided, and the semiconductor chip is arranged on the first pin and is electrically connected; (C) a conductive sheet is provided and electrically connected with the second pin and the semiconductor chip, and the conductive sheet is provided with a limited part which can be clamped and limited by the limiting part of the second pin; (D) a glue sealing processing is carried out; and (E) the pin unit and the frame are separated. The conductive sheet is clamped by the limiting part of the second pin, the conductive sheet can be prevented from sliding and deviating from the preset mounting position when the conductive sheet is mounted, and the packaging yield is improved.
Description
Technical field
The present invention relates to a kind of manufacture method of device, particularly relate to a kind of manufacture method of semiconductor device.
Background technology
The manufacture method of existing semiconductor device, that two spaced pins are first provided, again a semiconductor chip is electrically connected on a pin disposed therein, after a conducting strip is provided, two end opposite of this conducting strip are fitted respectively and is electrically connected on this semiconductor chip and another pin, finally carry out sealing program, complete a semiconductor device.
But, when this conducting strip carries out above-mentioned electric connection step, not good because of aligning accuracy, this conducting strip is often made to depart from predetermined electric connection position, and cause faying surface too small, even landing goes out this semiconductor chip and is connected on the pin that is positioned at below this semiconductor chip, forms short circuit, and yield declines.
Moreover, when being electrically connected this conducting strip, be that first on the pin that this semiconductor chip and this do not place this semiconductor chip, point covers elargol, after put this conducting strip and insert a reflow oven heating, make the solid-state elargol a little covered melt and be covered with faying surface, and then stick together this conducting strip.But, the elargol covered because of point presents solid-state point-like, so in the operation of inserting this reflow oven, be placed in this conducting strip easily slippage because rocking on elargol, and depart from predetermined lap position, cause faying surface too small, even landing goes out elargol surface and is connected on the pin that is positioned at below this semiconductor chip, forms short circuit.
In addition, when carrying out sealing program, be put into a mould, Reperfu-sion sealing by after the semi-finished product cooling of reflow oven process.But because the sealing of injecting is fluid, have the characteristic of flowing, if the faying surface of this conducting strip is too small, then the sealing that may be injected into promotes and is separated, and destroys stacked manner originally.
The manufacture method of existing semiconductor device, because of aligning accuracy and mode of operation therefore, often make the predetermined stacked manner of inter-module be destroyed, cause the not good problem of encapsulation yield.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method that can improve installation accuracy, promote the semiconductor device of encapsulation yield.
The manufacture method of semiconductor device of the present invention, comprises following steps: (A) provides one by the pin unit of a framework location.This pin unit has first pin and second pin that arrange separately.This first pin has the supporting part of this second pin of vicinity, and first Conducting end portions away from this second pin.This second pin has connecting end portion, the limiting section be located in this connecting end portion of this first pin of vicinity, and second Conducting end portions away from this first pin; (B) semiconductor chip is provided, the supporting part this semiconductor chip being arranged at this first pin is electrically connected; (C) conducting strip is provided, this conducting strip is connected with this second pin and this semiconductor chip.This conducting strip comprise one be positioned at a wherein end and fasten with the limiting section of this second pin and the limited portion be electrically connected with this connecting end portion, one be positioned at the other end and be arranged on this semiconductor chip and the sticking part be electrically connected with this semiconductor chip, an and connecting portion connecting this sticking part and this limited portion.This limited portion can be spacing by the engaging of the limiting section of this second pin, and do not move along a first direction and a second direction.This first direction and this second direction are the upper surfaces of the connecting end portion being parallel to this second pin; (D) carry out sealing program, by the part of this pin unit, this semiconductor chip, and this conducting strip is with a sealant covers, and makes the first Conducting end portions of this first pin and the second Conducting end portions of this second pin expose outside this sealing; And (E) is by this pin unit and this framework apart.
Preferably, this first direction this second direction vertical.
Preferably, the limited portion of this conducting strip has a basal wall section be connected with this connecting portion, and a perforation run through downwards from this basal wall section upper surface, the limiting section of this second pin is formed at the upper surface of this connecting end portion and the projection matched with this perforation, this projection can wear in this perforation and make this conducting strip limited, and make this conducting strip not with this projection for axle center rotates.
Preferably, the limited portion of this conducting strip has a basal wall section be connected with this connecting portion, and one from this basal wall section in contrast to the projection that a side of this connecting portion extends downwards, the limiting section of this second pin is that a upper surface from this connecting end portion runs through downwards and the perforation matched with this projection, this perforation allows that this projection wears into making this conducting strip limited, and this conducting strip not with this projection for axle center rotates.
Preferably, the limited portion of this conducting strip has a basal wall section be connected with this connecting portion, two side wall sections extended from two opposition sides of this basal wall section downwards, and two are formed at described side wall sections respectively and are opened on the inverted U-shaped draw-in groove of lower side, the limiting section of this second pin is two projections being formed at this limit, connecting end portion two opposition side respectively, and described projection can be snapped into described inverted U-shaped draw-in groove respectively makes this conducting strip limited.
Preferably, the sticking part of this conducting strip has the laminating section and a warpage section that are connected, as completing steps C) time, this laminating section is arranged on this semiconductor chip and is positioned at the upper surface scope of this semiconductor chip, this warpage section is from this laminating section toward the direction warpage away from this semiconductor chip, and is connected to the connecting portion of this conducting strip.
Preferably, the manufacture method of this semiconductor device is also contained in the step (F) after step (E), bend this first pin and this second pin and expose to part outside this sealing, make this first Conducting end portions and this second Conducting end portions this sealing surface contiguous respectively.
Beneficial effect of the present invention is: match with the limited portion of this conducting strip by the limiting section of this second pin, this limiting section is made to engage this conducting strip spacing, therefore predetermined installation site can not be departed from when installing this conducting strip, and make the mode of the survivable inter-module storehouse of follow-up operating procedure of carrying out, improve the yield of encapsulation.
Accompanying drawing explanation
Fig. 1 is a process block diagram, and first embodiment of the manufacture method of semiconductor device of the present invention is described;
Fig. 2 is a schematic diagram, illustrates that a semiconductor chip of this first embodiment is arranged on first pin of a pin unit by elargol;
Fig. 3 is a schematic diagram, illustrates that a conducting strip of this first embodiment is arranged on this pin unit;
Fig. 4 is an end view, and this conducting strip of this first embodiment and the electric connection mode of this semiconductor chip are described;
Fig. 5 is a schematic diagram, illustrate this first embodiment sealant covers mode and by this pin unit and a framework apart;
Fig. 6 is an end view, and the bending mode of this pin unit of this first embodiment is described;
Fig. 7 is a three-dimensional exploded view, and another enforcement aspect of this conducting strip is described;
Fig. 8 is a three-dimensional exploded view, and what this conducting strip was described one implements aspect again;
Fig. 9 is a process block diagram, and one second embodiment of the manufacture method of semiconductor device of the present invention is described;
Figure 10 (a) is a schematic diagram, illustrates that in this second embodiment, multiple pin unit is connected with multiple semiconductor chip;
Figure 10 (b) is a schematic diagram, to illustrate in this second embodiment that multiple conducting strip is by multiple sucker suction and displacement.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in detail.
Before the present invention is described in detail, should be noted that in the following description content, similar assembly represents with identical numbering.
Consult Fig. 1, be first embodiment of the manufacture method of semiconductor device of the present invention, step comprises: step (A) 100 provides one by the pin unit of a framework location.Step (B) 200 provides a semiconductor chip, and one of them pin this semiconductor chip being arranged at this pin unit is electrically connected.Step (C) 300 provides a conducting strip, is electrically connected between another pin of this conducting strip and this pin unit and this semiconductor chip mutually.Step (D) 400 carries out sealing program.Step (E) 500 is by this pin unit and this framework apart.Step (F) 600 bends program.Then, then after above steps is specified in.
Consult Fig. 1, Fig. 2 and Fig. 3, this step (A) 100 provides a pin unit 2 of being located by a framework 1.This pin unit 2 has first pin 21 and second pin 22 that arrange separately.This first pin 21 has the supporting part 211 of this second pin 22 of vicinity, and first Conducting end portions 212 away from this second pin 22.This second pin 22 has connecting end portion 221, limiting section 222 be located in this connecting end portion 221 of this first pin 21 of vicinity, and second Conducting end portions 223 away from this first pin 21.This first Conducting end portions 212 and this second Conducting end portions 223 are connected with this framework 1 and are fixed and locate.
It is worth mentioning that, the present embodiment first a metal substrate is defined this framework 1 and this pin unit 2 after hollow out also compacting, or can in integrated mode, as existing casting method, this pin unit 2 produced this framework 1 and located by this framework 1.This framework 1 and this pin unit 2 also must for the assemblies be separated, after again this pin unit 2 is fixedly arranged on this framework 1 and locates.The locate mode of this pin unit 2, ought to not with the content disclosed in this preferred embodiment for restriction.
This step (B) 200 is to provide a semiconductor chip 3, and point covers elargol on the supporting part 211 of this first pin 21, again this semiconductor chip 3 is positioned on elargol, rear heating and melting elargol forms a first elargol layer 5, this semiconductor chip 3 is binded by this first elargol layer 5 to be arranged on the supporting part 211 of this first pin 21, and is electrically connected with this first pin 21.
Consult Fig. 1, Fig. 3 and Fig. 4, this step (C) 300 is to provide a conducting strip 4, and cover elargol respectively at the upper surface of this semiconductor chip 3 and the connecting end portion 221 of this second pin 22, then utilize a sucker 10 to adsorb and move this conducting strip 4, and its two end opposite portion is arranged on the elargol of this connecting end portion 221 and this semiconductor chip 3 respectively.This conducting strip 4 being moved on this second pin 22 and this semiconductor chip 3, except using above-mentioned sucker 10, other clampings or adsorption plant also can be used to reach.
When this conducting strip 4 is placed in after on elargol, the said modules that storehouse is good is inserted a reflow oven (not shown) heating, the solid-state elargol a little covered is melted, and form a second elargol layer 6 on this semiconductor chip 3, and form a 3rd elargol layer 7 in the connecting end portion 221 of this second pin 22.This conducting strip 4 is electrically connected with this second pin 22 and this semiconductor chip 3 by this second elargol layer 6 and the 3rd elargol layer 7.
This conducting strip 4 comprises one and is positioned at a wherein end and fastens with the limiting section 222 of this second pin 22 and be positioned at the other end with 41, one, the limited portion that this connecting end portion 221 is electrically connected and be arranged on this semiconductor chip 3 and the sticking part 42 be electrically connected with this semiconductor chip 3, and a connecting portion 43 connecting this sticking part 42 and this limited portion 41.
This limited portion 41 has a basal wall section 411 be connected with this connecting portion 43, and a rectangular through-holes 412 run through downwards from this basal wall section 411 upper surface.The limiting section 222 of this second pin 22 is the upper surfaces being formed at this connecting end portion 221, and the rectangular cam 224 matched with this perforation 412.
To be adsorbed by this sucker 10 when this conducting strip 4 and move to the top of this pin unit 2, the perforation 412 of this conducting strip 4 is made to aim at the projection 224 of this second pin 22, after again move sucker 10 and make this projection 224 can wear in this perforation 412, make this conducting strip 4 limited and do not move along a first direction X and second direction Y, and not with this projection 224 for axle center rotate.This first direction X and this second direction Y is the upper surface of the connecting end portion 221 being parallel to this second pin 22, and mutually vertical.It should be noted, though bore a hole 412 in this embodiment with projection 224 for rectangle, both shapes are only required to be cooperatively interact non-circular, allow be formed between the two and mutually interfere and cannot relatively rotate.
When this conducting strip 4 is spacing by this projection 224, make this conducting strip 4 can not be curved surface and slippage because of elargol appearance, and the sticking part 42 of this conducting strip 4 is limited within the scope of the upper surface of this semiconductor chip 3 simultaneously, this sticking part 42 is made to be placed in elargol on this semiconductor chip 3.Now, the said modules that storehouse is good is inserted the heating of this reflow oven, make to select the solid-state elargol covered and melt and this conducting strip 4 of gluing.
This sticking part 42 has the laminating section 421 and a warpage section 422 that are connected, and this laminating section 421 is binded by this second elargol layer 6 and is arranged on this semiconductor chip 3, and is positioned at the upper surface scope of this semiconductor chip 3.This warpage section 422 is from this laminating section 421 toward the direction warpage away from this semiconductor chip 3, and is connected to the connecting portion 43 of this conducting strip 4, and the part compartment of terrain be at least connected with this laminating section 421 in this warpage section 422 is positioned at the upper surface of this semiconductor chip 3.
When this laminating section 421 is pressed on the point-like elargol on this semiconductor chip 3, the elargol melted because of heating is extruded and periphery toward this semiconductor chip 3 flows, in the accommodation space 40 that the upper surface that too much elargol can be placed in this warpage section 422 and this semiconductor chip 3 defines, therefore can not produce because elargol overflow is to this first pin 21, and cause the short circuit problem that this conducting strip 4 is electrically connected with this first pin 21.
Consult Fig. 1 and Fig. 5, this step (D) 400 is that the described assembly of completing steps (C) 300 is inserted (not shown) in a mould, after pour into part, this semiconductor chip 3 of sealing 8 this pin unit 2 coated again, and this conducting strip 4, the first Conducting end portions 212 of this first pin 21 and the second Conducting end portions 223 of this second pin 22 are exposed outside this sealing 8.
After completing the step pouring into this sealing 8, this sealing 8 is solidified, then assembly from this mould in the (not shown) coated by this sealing 8 is taken out.This sealing program can use any existing mode to complete, ought to not with the content disclosed in this preferred embodiment for restriction.
This step (E) 500 cuts for the finished product this step (D) 400 completed, and this pin unit 2 is separated with this framework 1, forms semiconductor device semi-finished product.This separating step can use any existing mode to complete, ought to not with the content disclosed in the present embodiment for restriction.
Consult Fig. 1 and Fig. 6, this step (F) 600 is bent the part that this first pin 21 half-finished for this semiconductor device and this second pin 22 expose to this sealing 8, make this first Conducting end portions 212 and this second Conducting end portions 223 be respectively adjacent to this sealing 8 surface, namely complete a semiconductor device.This bending program can use any existing mode to complete, ought to not with the content disclosed in this preferred embodiment for restriction.
It is worth mentioning that, the limiting section 222 of this second pin 22 and the limited portion 41 of this conducting strip 4 also have two kinds to implement aspect.
Consult Fig. 7, another of this conducting strip 4 is implemented in aspect, the limited portion 41 of this conducting strip 4 has a basal wall section 411 be connected with this connecting portion 43, and one from this basal wall section 411 in contrast to the rectangular cam 413 that a side of this connecting portion 43 extends downwards, this projection 413 also can be formed at the lower surface of this basal wall section 411.The limiting section 222 of this second pin 22 is that a upper surface from this connecting end portion 221 runs through downwards and the rectangular through-holes 225 matched with this projection 413.This perforation 225 allows that this projection 413 wears into making this conducting strip 4 limited, and not along this first direction X and this second direction Y displacement, and this conducting strip 4 not with this projection 413 for axle center rotates.
Consult Fig. 8, in an enforcement aspect again of this conducting strip 4, the limited portion 41 of this conducting strip 4 has a basal wall section be connected with this connecting portion 43 411, two side wall sections 414 extended from two opposition sides of this basal wall section 411 downwards, and two are formed at described side wall sections 414 respectively and are opened on the inverted U-shaped draw-in groove 415 of lower side.The limiting section 222 of this second pin 22 is two projections 226 being formed at this limit, connecting end portion 221 liang of opposition sides respectively.Described projection 226 can be snapped into described inverted U-shaped draw-in groove 415 respectively makes this conducting strip 4 limited, and not along this first direction X and this second direction Y displacement.
Consult Fig. 9, Figure 10 (a) and Figure 10 (b), being one second embodiment of the present invention, is that first embodiment of the invention is used for large-scale production.The present embodiment difference main from the first embodiment is that the quantity of provided assembly is different, and all the other operational means are all identical.
The step of the present embodiment comprises: (A) provides multiple pin unit 2 of being located by a framework 1.(B) provide multiple semiconductor chip 3, one of them pin that each semiconductor chip 3 is arranged at each pin unit 2 is electrically connected.(C) multiple conducting strip 4 is provided, by another pin in each conducting strip 4 and each pin unit 2 and be located on this pin unit 2 between semiconductor chip 3 to be electrically connected mutually.(D) sealing program is carried out.(E) described pin unit 2 is separated with this framework 1.(F) program is bent.
Described pin unit 2, described semiconductor chip 3, and the structure of described conducting strip 4 is identical with this first embodiment.
In time carrying out step (C), be adsorb with multiple sucker 10 and move described conducting strip 4, make the second pin 22 of each conducting strip 4 and each pin unit 2 and the semiconductor chip 3 be arranged on the first pin 21 align and be electrically connected.This conducting strip 4 being moved on this second pin 22 and this semiconductor chip 3, except using above-mentioned sucker 10, other clampings or adsorption plant also can be used to reach.
Described sucker 10 can with one row or one row mode adsorb described conducting strip 4, also can be arranged in an array to adsorb described conducting strip 4, also can with single sucker 10 sequentially adsorb described conducting strip 4 wherein any one to carry out step (C).
When the row of use, row or the described sucker 10 of array form adsorb described conducting strip 4, described conducting strip 4 can be located with a framework 1 ', and facilitate described sucker locate and adsorb.Wherein, described conducting strip 4 can define this framework 1 ' and described conducting strip 4 with a metal substrate after hollow out also compacting, or can in integrated mode, as existing casting method, the described conducting strip 4 produced this framework 1 ' and located by this framework 1 '.This framework 1 ' and described conducting strip 4 also must for the assemblies be separated, after more described conducting strip 4 to be fixedly arranged on this framework 1 ' upper and locate.
Other modes of operation, as the mode of: electric connection, sealing program, with framework 1 side from mode, and bending program, all identical with this first embodiment.
The present embodiment is that the method shown in this first embodiment is used for large-scale production.Because described conducting strip 4 can be spacing by the limiting section 222 of described second pin 22, so under large production, also can there is accurate location, and not easily make because rocking the storehouse between said modules be destroyed, improve the yield of encapsulation.
In sum, match with the limited portion 41 of this conducting strip 4 by the limiting section 222 of this second pin 22, this limiting section 222 is made to engage this conducting strip 4 spacing, therefore predetermined installation site can not be departed from when installing this conducting strip 4, and make the mode of the survivable inter-module storehouse of follow-up operating procedure of carrying out, therefore really can reach object of the present invention.
Claims (7)
1. the manufacture method of a semiconductor device, it is characterized in that: the manufacture method of this semiconductor device comprises following steps: (A) provides one by the pin unit of a framework location, this pin unit has first pin and second pin that arrange separately, this first pin has the supporting part of this second pin of vicinity, and first Conducting end portions away from this second pin, this second pin has the connecting end portion of this first pin of vicinity, a limiting section be located in this connecting end portion, and second Conducting end portions away from this first pin, (B) semiconductor chip is provided, the supporting part this semiconductor chip being arranged at this first pin is electrically connected, (C) conducting strip is provided, this conducting strip is connected with this second pin and this semiconductor chip, this conducting strip comprises one and is positioned at a wherein end and fastens with the limiting section of this second pin and the limited portion be electrically connected with this connecting end portion, one is positioned at the other end and is arranged on this semiconductor chip and the sticking part be electrically connected with this semiconductor chip, and the connecting portion in this sticking part of connection and this limited portion, this limited portion can be spacing by the engaging of the limiting section of this second pin, and do not move along a first direction and a second direction, this first direction and this second direction are the upper surfaces of the connecting end portion being parallel to this second pin, (D) carry out sealing program, by the part of this pin unit, this semiconductor chip, and this conducting strip is with a sealant covers, and makes the first Conducting end portions of this first pin and the second Conducting end portions of this second pin expose outside this sealing, and (E) is by this pin unit and this framework apart.
2. the manufacture method of semiconductor device according to claim 1, is characterized in that: this first direction this second direction vertical.
3. the manufacture method of semiconductor device according to claim 2, it is characterized in that: the limited portion of this conducting strip has a basal wall section be connected with this connecting portion, and a perforation run through downwards from this basal wall section upper surface, the limiting section of this second pin is formed at the upper surface of this connecting end portion and the projection matched with this perforation, this projection can wear in this perforation and make this conducting strip limited, and make this conducting strip not with this projection for axle center rotates.
4. the manufacture method of semiconductor device according to claim 2, it is characterized in that: the limited portion of this conducting strip has a basal wall section be connected with this connecting portion, and one from this basal wall section in contrast to the projection that a side of this connecting portion extends downwards, the limiting section of this second pin is that a upper surface from this connecting end portion runs through downwards and the perforation matched with this projection, this perforation allows that this projection wears into making this conducting strip limited, and this conducting strip not with this projection for axle center rotates.
5. the manufacture method of semiconductor device according to claim 2, it is characterized in that: the limited portion of this conducting strip has a basal wall section be connected with this connecting portion, two side wall sections extended from two opposition sides of this basal wall section downwards, and two are formed at described side wall sections respectively and are opened on the inverted U-shaped draw-in groove of lower side, the limiting section of this second pin is two projections being formed at this limit, connecting end portion two opposition side respectively, and described projection can be snapped into described inverted U-shaped draw-in groove respectively makes this conducting strip limited.
6. the manufacture method of semiconductor device according to claim 1, it is characterized in that: the sticking part of this conducting strip has the laminating section and a warpage section that are connected, as completing steps C) time, this laminating section is arranged on this semiconductor chip and is positioned at the upper surface scope of this semiconductor chip, this warpage section is from this laminating section toward the direction warpage away from this semiconductor chip, and is connected to the connecting portion of this conducting strip.
7. the manufacture method of semiconductor device according to claim 1, it is characterized in that: the manufacture method of this semiconductor device is also contained in the step (F) after step (E), bend this first pin and this second pin and expose to part outside this sealing, make this first Conducting end portions and this second Conducting end portions this sealing surface contiguous respectively.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410092528.6A CN104916548B (en) | 2014-03-13 | 2014-03-13 | The preparation method of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410092528.6A CN104916548B (en) | 2014-03-13 | 2014-03-13 | The preparation method of semiconductor device |
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| CN104916548A true CN104916548A (en) | 2015-09-16 |
| CN104916548B CN104916548B (en) | 2018-01-19 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20190189544A1 (en) * | 2017-12-20 | 2019-06-20 | Nexperia B.V. | Semiconductor package and method of manufacture |
| EP3761358A1 (en) * | 2019-07-02 | 2021-01-06 | Nexperia B.V. | A lead frame assembly for a semiconductor device |
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| JP2003273311A (en) * | 2002-03-19 | 2003-09-26 | Seiko Epson Corp | Semiconductor device and manufacturing method therefor, circuit substrate, and electronic apparatus |
| CN1708206A (en) * | 2004-06-09 | 2005-12-14 | Nec化合物半导体器件株式会社 | Chip-component-mounted device and semiconductor device |
| TWM399518U (en) * | 2010-10-01 | 2011-03-01 | Ceramate Technical Co Ltd | Electric connector with semiconductor type anti-surge and -electrostatic functions |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003273311A (en) * | 2002-03-19 | 2003-09-26 | Seiko Epson Corp | Semiconductor device and manufacturing method therefor, circuit substrate, and electronic apparatus |
| CN1708206A (en) * | 2004-06-09 | 2005-12-14 | Nec化合物半导体器件株式会社 | Chip-component-mounted device and semiconductor device |
| TWM399518U (en) * | 2010-10-01 | 2011-03-01 | Ceramate Technical Co Ltd | Electric connector with semiconductor type anti-surge and -electrostatic functions |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20190189544A1 (en) * | 2017-12-20 | 2019-06-20 | Nexperia B.V. | Semiconductor package and method of manufacture |
| EP3503178A1 (en) * | 2017-12-20 | 2019-06-26 | Nexperia B.V. | Semiconductor package and method of manufacture |
| EP3761358A1 (en) * | 2019-07-02 | 2021-01-06 | Nexperia B.V. | A lead frame assembly for a semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104916548B (en) | 2018-01-19 |
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