CN104916310A - High noise margin high speed subthreshold memory cell - Google Patents
High noise margin high speed subthreshold memory cell Download PDFInfo
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- CN104916310A CN104916310A CN201410095162.8A CN201410095162A CN104916310A CN 104916310 A CN104916310 A CN 104916310A CN 201410095162 A CN201410095162 A CN 201410095162A CN 104916310 A CN104916310 A CN 104916310A
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Abstract
The invention provides a high noise margin high speed subthreshold memory cell, which includes: a first inverter, a second inverter, a first feedback pipe, a second feedback pipe, a first read-write control part and a second read-write control part. The first inverter and the second inverter respectively include a first stack pipe and a second stack pipe, the drain ends and the source ends of the stack pipes respectively serve as the output ends and virtual output ends of the inverters. The first read-write control part and the second read-write control part are connected to external circuit control signals, and respectively include a first write control pipe, a second write control pipe and a first read-write control pipe and a second read-write control pipe. By introducing virtual nodes, the high noise margin high speed subthreshold memory cell provided by the invention effectively isolates external interference during data reading, improves the noise margin of data reading, and is the currently known cell maintaining the largest noise margin under 300mv supply voltage.
Description
Technical field
The present invention relates to memory area, particularly relate to one strong noise tolerance limit high speed sub-threshold memory cell.
Background technology
The rise of the applications such as medical electronics, Internet of Things, RFID, makes large batch of wireless sensing node be widely used.The typical feature of this category node is that quantity required is large, system bulk is little, performance requirement is low, power consumption requirements is high.Storer has accounted for the power consumption of significant proportion of this category node, and therefore the reduction of power consumption of memory has very great help to reduction Overall Power Consumption.SRAM, as conventional storer, is extensively studied.In the technology of low-power consumption known at present, most effective method when directly reducing supply voltage.Therefore subthreshold value technology is recently studied more and more, but will become problem in the stability of subthreshold region storage unit, and how improving the stability of storage unit, is present facing challenges.In the sram cell of conventional 6 pipes, two back-to-back phase inverter voltage-transfer characteristic curve surround minimum area be exactly maximum noise margin, and when conventional 6 pipe units in read operation time, the noise margin read reduces greatly than the noise margin kept.In order to increase noise margin, the phase inverter of Si Mite structure is just introduced into.Due to the good noise margin of Si Mite structure, the noise margin of sram cell is made also greatly to become large.In the traditional design keeping noise margin to increase, the noise margin read does not have too many raising, and the speed read also has been sacrificed.
Therefore, need a kind of can maintenance while noise margin in increase badly, increase the memory device of the noise margin read and the speed read.
Summary of the invention
The invention provides a kind of strong noise tolerance limit high speed sub-threshold memory cell, this storage unit has maximum noise margin under the subthreshold voltage of 300mV, and passes through introducing and the difference read data pattern of dummy node, and read data speed is improved greatly.Concrete, this circuit comprises:
First phase inverter, the second phase inverter, the first feedback pipe, the second feedback pipe, the first Read-write Catrol part and the second Read-write Catrol part;
Comprise first, second stacked tubes respectively in first, second phase inverter described, the drain terminal of described stacked tubes and source are respectively as the output terminal of phase inverter and dummy output terminal;
The output terminal of described first phase inverter connects the input end of the input end of the second phase inverter, the output terminal of the first Read-write Catrol part and the first feedback pipe respectively; The output terminal of described second phase inverter connects the input end of the input end of the first phase inverter, the output terminal of the second Read-write Catrol part and the first feedback pipe respectively;
The dummy output terminal of described first phase inverter connects the output terminal of the first Read-write Catrol part and the first feedback pipe respectively; The dummy output terminal of described second phase inverter connects the output terminal of the second Read-write Catrol part and the second feedback pipe respectively;
First, second Read-write Catrol part described connects external circuit control signal, comprises first, second respectively and writes control tube and first, second Read-write Catrol pipe.
Wherein, described first phase inverter comprises the first PMOS and first, second NMOS tube, and wherein the first stacked tubes is the first NMOS tube; The source of the first PMOS connects supply voltage, the source ground connection of the second NMOS tube; The drain terminal of the first PMOS is connected as the output of the first phase inverter with the drain terminal of the first NMOS tube, the source of the first NMOS tube is connected the virtual output as the first phase inverter with the drain terminal of the second NMOS tube, the grid end of the first PMOS and first, second NMOS tube connects the output of the second phase inverter simultaneously.
Wherein, described second phase inverter comprises the second PMOS P2 and the 3rd, the 4th NMOS tube, and wherein the second stacked tubes is the 3rd NMOS tube; The source of the second PMOS P2 connects supply voltage, the source ground connection of the 4th NMOS tube; The drain terminal of the second PMOS P2 is connected as the output of the second phase inverter with the drain terminal of the 3rd NMOS tube, the source of the 3rd NMOS tube is connected the virtual output as the second phase inverter with the drain terminal of the 4th NMOS tube, the grid end of the second PMOS P2 and the 3rd, the 4th NMOS tube connects the output of the first phase inverter simultaneously.
Wherein, the drain terminal of described first feedback pipe connects supply voltage, the output of grid termination first phase inverter, and source connects the virtual output of the first phase inverter.
Wherein, the drain terminal of described second feedback pipe connects supply voltage, the output of grid termination second phase inverter, and source connects the virtual output of the second phase inverter.
Wherein, described first Read-write Catrol part comprises the 6th, the 7th NMOS tube, and wherein first to write control tube be the 6th NMOS tube, the first Read-write Catrol Guan Wei seven NMOS tube; Wherein the drain terminal of the 6th NMOS tube is connected with the source of the 7th NMOS tube, be connected to the virtual output of the first phase inverter, the source of the 6th NMOS tube connects the output of the first phase inverter, and the drain terminal of the 7th NMOS tube connects bit line BL, the grid end connection control signal WL of the 6th, the 7th NMOS tube and WWL.
Wherein, described second Read-write Catrol part comprises the 9th, the tenth NMOS tube, and wherein second to write control tube be the 9th NMOS tube, the second Read-write Catrol Guan Wei ten NMOS tube; Wherein the drain terminal of the 9th NMOS tube is connected with the source of the tenth NMOS tube, be connected to the virtual output of the second phase inverter, the source of the 9th NMOS tube connects the output of the second phase inverter, and the drain terminal of the tenth NMOS tube connects bit line BL, the grid end connection control signal WL of the 9th, the tenth NMOS tube and WWL.
Wherein, holding circuit, reading circuit and write circuit three kinds of functions can be realized by control signal.
Wherein, when control signal WL and WWL is low level, described storage unit is holding circuit.Wherein, described holding circuit comprises the first phase inverter, the second phase inverter, the first feedback pipe and the second feedback pipe.
Wherein, when control signal WL is high level, when WWL is low level, described storage unit is reading circuit.Wherein, described reading circuit comprises the 7th, the tenth NMOS tube in the first phase inverter, the second phase inverter, the first feedback pipe, the second feedback pipe and first, second control circuit.
Wherein, when control signal WL and WWL is high level, described storage unit is write circuit.Wherein, described write circuit comprises the first phase inverter, the second phase inverter, the first feedback pipe, second feedback pipe and first, second control circuit.
Strong noise tolerance limit high speed sub-threshold memory cell provided by the present invention is known under 300mv supply voltage at present, keeps noise margin maximum.By the introducing of dummy node, effectively isolate external disturbance during read data, improve the noise margin of read data; Dummy node and difference read data pattern make read data speed greatly improve; Meanwhile, during write data, use two transistors to control, effectively solve and write half selected problem.
Accompanying drawing explanation
By reading the detailed description done non-limiting example done with reference to the following drawings, other features, objects and advantages of the present invention will become more obvious:
Fig. 1 is memory cell structure of the present invention;
Fig. 2 is the maintenance noise margin of storage unit of the present invention under 300mv;
Fig. 3 is the read noise tolerance limit of storage unit of the present invention under 300mv;
Fig. 4 is that under the present invention and 8T unit 300mv, single-ended reading speed compares;
Fig. 5 is that the present invention feeds back electric leakage control;
In accompanying drawing, same or analogous Reference numeral represents same or analogous parts.
Embodiment
Below in conjunction with accompanying drawing and specific embodiments of the invention, the present invention is described in further detail.It is to be appreciated that the present invention is not limited to following particular implementation, those skilled in the art can make various distortion or amendment within the scope of the appended claims.
As shown in Figure 1, the invention provides a kind of subthreshold value memory circuit, this structure comprises:
First phase inverter, the second phase inverter, the first feedback pipe, the second feedback pipe, the first Read-write Catrol part and the second Read-write Catrol part; The output terminal of described first phase inverter connects the input end of the input end of the second phase inverter, the output terminal of the first Read-write Catrol part and the first feedback pipe respectively; The output terminal of described second phase inverter connects the input end of the input end of the first phase inverter, the output terminal of the second Read-write Catrol part and the first feedback pipe respectively; The dummy output terminal of described first phase inverter connects the output terminal of the first Read-write Catrol part and the first feedback pipe respectively; The dummy output terminal of described second phase inverter connects the output terminal of the second Read-write Catrol part and the second feedback pipe respectively; First Read-write Catrol part is connected external circuit control signal with the second Read-write Catrol part.
Wherein, described first phase inverter is made up of the first PMOS P1 and first, second NMOS tube N1, N2, and the source of the first PMOS P1 connects supply voltage, the source ground connection of the second NMOS tube N2; The drain terminal of the first PMOS P1 is connected as the output of the first phase inverter with the drain terminal of the first NMOS tube N1, the source of the first NMOS tube N1 is connected the virtual output as the first phase inverter with the drain terminal of the second NMOS tube N2, the grid end of the first PMOS P1 and first, second NMOS tube N1, N2 connects the output of the second phase inverter simultaneously.
Wherein, described second phase inverter is made up of the second PMOS P2 and the 3rd, the 4th NMOS tube N3, N4, and the source of the second PMOS P2 connects supply voltage, the source ground connection of the 4th NMOS tube N4; The drain terminal of the second PMOS P2 is connected as the output of the second phase inverter with the drain terminal of the 3rd NMOS tube N3, the source of the 3rd NMOS tube N3 is connected the virtual output as the second phase inverter with the drain terminal of the 4th NMOS tube N4, the grid end of the second PMOS P2 and the 3rd, the 4th NMOS tube N3, N4 connects the output of the first phase inverter simultaneously.
Wherein, the drain terminal of described first feedback pipe N5 connects supply voltage, the output of grid termination first phase inverter, and source connects the virtual output of the first phase inverter.
Wherein, the drain terminal of described second feedback pipe N8 connects supply voltage, the output of grid termination second phase inverter, and source connects the virtual output of the second phase inverter.
Wherein, described first Read-write Catrol part comprises the 6th, the 7th NMOS tube N6, N7, wherein the drain terminal of the 6th NMOS tube N6 is connected with the source of the 7th NMOS tube N7, be connected to the virtual output of the first phase inverter, the source of the 6th NMOS tube N6 connects the output of the first phase inverter, the drain terminal of the 7th NMOS tube N7 connects bit line BL, the grid end connection control signal WL of the 6th, the 7th NMOS tube N6, N7 and WWL.
Wherein, described second Read-write Catrol part comprises the 9th, the tenth NMOS tube N9, N10, wherein the drain terminal of the 9th NMOS tube N9 is connected with the source of the tenth NMOS tube N10, be connected to the virtual output of the second phase inverter, the source of the 9th NMOS tube N9 connects the output of the second phase inverter, the drain terminal of the tenth NMOS tube N10 connects bit line BL, the grid end connection control signal WL of the 9th, the tenth NMOS tube N9, N10 and WWL.
By changing the input of control signal WL and WWL, this storage unit can be controlled and realize keeping function, reading function or write function.
In the present embodiment, the initial output value Q of the first phase inverter is high level 1, and the initial output value QB of the second phase inverter is low level 0.
A. function is kept
When control signal WWL and WL is low level, metal-oxide-semiconductor N6, N7, N9, N10 in control circuit are turned off.First, second phase inverter composition feedback loop carries out data preservation, forms holding circuit.Now, the drain terminal of the first feedback pipe N5 connects supply voltage, the output of grid termination first phase inverter, and source connects the virtual output of first phase inverter.The drain terminal of the second feedback pipe N8 connects supply voltage, the output of grid termination second phase inverter, and source connects the virtual output of second phase inverter.
Now, if outside has noise to enter, change the store status of Q point, namely " 1 " to be become " 0 ", QB is changed to " 1 " from " 0 ", but in the process of interference, N5 controls by Q, opening at initial period, so dummy node PQ equals VVDD, is now high level, slowly open when QB becomes control N1 in the process of " 1 ", and the high level of dummy node PQ will pass on Q in the process slowly opened as N1, so original state can be kept, this in effect increases the noise margin of maintenance.Fig. 2 is the Monte Carlo simulation result that the present invention and traditional 6 pipe units keep noise margin under the supply voltage of 300mv, blue line (line on the limit that keeps left) in figure is the maintenance noise margin of traditional 6 pipe units, red line (line on limit of keeping right) is maintenance noise margin of the present invention, both more in Table 1, compare 6 traditional pipe units, the present invention keeps noise margin to improve about 42%.
Table 1. the present invention and traditional 6T unit keep the comparison of noise margin
| 6T | This structure | Number percent | |
| Mean value | 0.10018 | 0.14201 | Improve 42% |
| Standard deviation | 0.01172 | 0.00674 | Improve 43% |
B. function is read
When control signal WWL is low level, when WL is high level, metal-oxide-semiconductor N6, N9 close, and N7, N10 open.Now, first, second phase inverter composition feedback loop carries out data preservation, forms holding circuit.The drain terminal of the first feedback pipe N5 connects supply voltage, the output of grid termination first phase inverter, and source connects the virtual output of the first phase inverter.The drain terminal of the second feedback pipe N8 connects supply voltage, the output of grid termination second phase inverter, and source connects the virtual output of the second phase inverter.Now, metal-oxide-semiconductor N6, N9 close, N7 and N10 is comprised in the circuit read, and its grid end is for connecing high level, and the drain terminal of N7 connects readout bit line, and source connects the virtual output point of the first phase inverter.The drain terminal of N8 connects the readout bit line of phase inverter, and source connects the virtual output point of the second phase inverter.
Source due to N7 meets dummy node PQ, the source of N10 meets dummy node PQB, and when reading the data, can allow real node and the virtual node of N1 and N3 pipe carry out certain isolation, even if so outside has noise to enter, also can only affect virtual node and can not affect real node.To storage unit of the present invention and 6 traditional pipe units under the voltage of 300mv, carry out Monte Carlo simulation, Fig. 3 is simulation result, blue line (line on the limit that keeps left) is wherein the read noise tolerance limit of traditional 6 pipes, red line (line on limit of keeping right) is read noise tolerance limit of the present invention, and the average data of both read noise tolerance limits is recorded in table 2: read noise tolerance limit of the present invention improves 1.5 times than 6 traditional pipe units.
The read noise tolerance limit of table 2. the present invention and traditional 6T unit compares
| 6T | This structure | Number percent | |
| Mean value | 3.87E-02 | 0.100239 | Improve 150% |
The path read during read data comprises N10 and N4, N7 and N2 two paths, and can carry out difference and read, speed accelerates.Owing to being reading of difference, as long as two sense bit lines have certain pressure reduction, just can export, the speed comparing sense data single-ended under subthreshold value like this wants fast a lot.Even if invention unit reads without difference, read with single-ended, the speed of reading also more single-ended than other read fast.Fig. 4 be 32 invention unit when single-ended reading and the single-ended comparison of reading under 300mv of 8 pipe units, reading speed improves about 50%.For the reading of difference, 32 invention unit can make electric leakage electric leakage of blue line from Fig. 5 become the electric leakage of red line by the control of feedback, the sense amplifier when difference is read will be made like this to have enough large pressure reduction, change can be captured very soon, improve the speed read.
C. function is write
When control signal WWL and WL is high level, metal-oxide-semiconductor N6, N7, N9, N10 in control circuit are opened.Now, first, second phase inverter composition feedback loop carries out data preservation, forms holding circuit.The drain terminal of the first feedback pipe N5 connects supply voltage, the output of grid termination first phase inverter, and source connects the virtual output of the first phase inverter.The drain terminal of the second feedback pipe N8 connects supply voltage, the output of grid termination second phase inverter, and source connects the virtual output of the second phase inverter.Now, metal-oxide-semiconductor N6, N7, N9 and N10 are all opened, and are included in the circuit read, and its grid end is for connecing high level.The drain terminal of N6 connects the virtual output point of the first phase inverter, and the grid termination high level of N6, the source of N6 connects the output point of the first phase inverter.The drain terminal of N9 connects the virtual output point of the second phase inverter, and grid termination high level, source connects the output point of the second phase inverter.Meanwhile, the drain terminal of N5 connects low level, the output of grid termination first phase inverter, and source connects the virtual output of the first phase inverter.The drain terminal of N8 connects low level, the output of grid termination second phase inverter, and source connects the virtual output of the second phase inverter.
During write data, N7 and N6, N9 and N10 difference writes, owing to there being two pipes on the path write, so when half selected problem is write in solution, very effectively.
Strong noise tolerance limit high speed sub-threshold memory cell provided by the present invention is known under 300mv supply voltage at present, keeps noise margin maximum.By the introducing of dummy node, effectively isolate external disturbance during read data, improve the noise margin of read data; Dummy node and difference read data pattern make read data speed greatly improve; Meanwhile, during write data, use two transistors to control, effectively solve and write half selected problem.
Above specific embodiments of the invention are described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, those skilled in the art can make various distortion or amendment within the scope of the appended claims.
Claims (14)
1. a strong noise tolerance limit high speed sub-threshold memory cell, comprising: the first phase inverter, the second phase inverter, the first feedback pipe, the second feedback pipe, the first Read-write Catrol part and the second Read-write Catrol part.
Comprise first, second stacked tubes respectively in first, second phase inverter described, the drain terminal of described stacked tubes and source are respectively as the output terminal of phase inverter and dummy output terminal;
Described first inverter output connects the input end of the input end of the second phase inverter, the output terminal of the first Read-write Catrol part and the first feedback pipe respectively; The output terminal of described second phase inverter connects the input end of the input end of the first phase inverter, the output terminal of the second Read-write Catrol part and the first feedback pipe respectively;
The dummy output terminal of described first phase inverter connects the output terminal of the first Read-write Catrol part and the first feedback pipe respectively; The dummy output terminal of described second phase inverter connects the output terminal of the second Read-write Catrol part and the second feedback pipe respectively;
First, second Read-write Catrol part described connects external circuit control signal, comprises first, second respectively and writes control tube and first, second Read-write Catrol pipe.
2. strong noise tolerance limit high speed sub-threshold memory cell according to claim 1, it is characterized in that, described first phase inverter comprises the first PMOS (P1) and first, second NMOS tube (N1, N2), and wherein the first stacked tubes is the first NMOS tube (N1); The source of the first PMOS (P1) connects supply voltage, the source ground connection of the second NMOS tube (N2); The drain terminal of the first PMOS (P1) is connected as the output of the first phase inverter with the drain terminal of the first NMOS tube (N1), the source of the first NMOS tube (N1) is connected the virtual output as the first phase inverter with the drain terminal of the second NMOS tube (N2), the grid end of the first PMOS (P1) and first, second NMOS tube (N1, N2) connects the output of the second phase inverter simultaneously.
3. strong noise tolerance limit high speed sub-threshold memory cell according to claim 1, it is characterized in that, described second phase inverter comprises the second PMOS P2 and the 3rd, the 4th NMOS tube (N3, N4), and wherein the second stacked tubes is the 3rd NMOS tube (N3); The source of the second PMOS P2 connects supply voltage, the source ground connection of the 4th NMOS tube (N4); The drain terminal of the second PMOS P2 is connected as the output of the second phase inverter with the drain terminal of the 3rd NMOS tube (N3), the source of the 3rd NMOS tube (N3) is connected the virtual output as the second phase inverter with the drain terminal of the 4th NMOS tube (N4), the grid end of the second PMOS P2 and the 3rd, the 4th NMOS tube (N3, N4) connects the output of the first phase inverter simultaneously.
4. strong noise tolerance limit high speed sub-threshold memory cell according to claim 1, is characterized in that, the drain terminal of described first feedback pipe (N5) connects supply voltage, the output of grid termination first phase inverter, and source connects the virtual output of the first phase inverter.
5. strong noise tolerance limit high speed sub-threshold memory cell according to claim 1, is characterized in that, the drain terminal of described second feedback pipe (N8) connects supply voltage, the output of grid termination second phase inverter, and source connects the virtual output of the second phase inverter.
6. strong noise tolerance limit high speed sub-threshold memory cell according to claim 1, it is characterized in that, described first Read-write Catrol part comprises the 6th, the 7th NMOS tube (N6, N7), wherein first to write control tube be the 6th NMOS tube (N6), the first Read-write Catrol Guan Wei seven NMOS tube (N7); Wherein the drain terminal of the 6th NMOS tube (N6) is connected with the source of the 7th NMOS tube (N7), be connected to the virtual output of the first phase inverter, the source of the 6th NMOS tube (N6) connects the output of the first phase inverter, the drain terminal of the 7th NMOS tube (N7) connects bit line BL, the grid end connection control signal WL of the 6th, the 7th NMOS tube (N6, N7) and WWL.
7. strong noise tolerance limit high speed sub-threshold memory cell according to claim 1, it is characterized in that, described second Read-write Catrol part comprises the 9th, the tenth NMOS tube (N9, N10), wherein second to write control tube be the 9th NMOS tube (N9), the second Read-write Catrol Guan Wei ten NMOS tube (N10); Wherein the drain terminal of the 9th NMOS tube (N9) is connected with the source of the tenth NMOS tube (N10), be connected to the virtual output of the second phase inverter, the source of the 9th NMOS tube (N9) connects the output of the second phase inverter, the drain terminal of the tenth NMOS tube (N10) connects bit line BL, the grid end connection control signal WL of the 9th, the tenth NMOS tube (N9, N10) and WWL.
8. strong noise tolerance limit high speed sub-threshold memory cell according to claim 1, is characterized in that, can realize holding circuit, reading circuit and write circuit three kinds of functions by control signal.
9. the strong noise tolerance limit high speed sub-threshold memory cell according to claim 1 or 8, is characterized in that, when control signal WL and WWL is low level, described storage unit is holding circuit.
10. strong noise tolerance limit high speed sub-threshold memory cell according to claim 9, is characterized in that, described holding circuit comprises the first phase inverter, the second phase inverter, the first feedback pipe and the second feedback pipe.
11. strong noise tolerance limit high speed sub-threshold memory cells according to claim 1 or 8, it is characterized in that, when control signal WL is high level, when WWL is low level, described storage unit is reading circuit.
12. strong noise tolerance limit high speed sub-threshold memory cells according to claim 11, it is characterized in that, described reading circuit comprises the 7th, the tenth NMOS tube (N7, N1) in the first phase inverter, the second phase inverter, the first feedback pipe, the second feedback pipe and first, second control circuit.
13. strong noise tolerance limit high speed sub-threshold memory cells according to claim 1 or 8, it is characterized in that, when control signal WL and WWL is high level, described storage unit is write circuit.
14. strong noise tolerance limit high speed sub-threshold memory cells according to claim 13, is characterized in that, described write circuit comprises the first phase inverter, the second phase inverter, the first feedback pipe, second feedback pipe and first, second control circuit.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1423283A (en) * | 2001-12-07 | 2003-06-11 | 三菱电机株式会社 | Semiconductor storage circuit not easy to make soft mistakes |
| JP2005302121A (en) * | 2004-04-09 | 2005-10-27 | Seiko Epson Corp | Semiconductor memory device |
| CN201910251U (en) * | 2010-12-31 | 2011-07-27 | 东南大学 | Memory unit circuit with self-adaptive leakage current cutting-off mechanism |
| CN102176323A (en) * | 2010-12-31 | 2011-09-07 | 东南大学 | Storage unit circuit with adaptive leakage current cutoff mechanism |
| CN102543157A (en) * | 2012-02-17 | 2012-07-04 | 安徽大学 | Double-bit-line sub-threshold storage unit circuit |
-
2014
- 2014-03-14 CN CN201410095162.8A patent/CN104916310B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1423283A (en) * | 2001-12-07 | 2003-06-11 | 三菱电机株式会社 | Semiconductor storage circuit not easy to make soft mistakes |
| JP2005302121A (en) * | 2004-04-09 | 2005-10-27 | Seiko Epson Corp | Semiconductor memory device |
| CN201910251U (en) * | 2010-12-31 | 2011-07-27 | 东南大学 | Memory unit circuit with self-adaptive leakage current cutting-off mechanism |
| CN102176323A (en) * | 2010-12-31 | 2011-09-07 | 东南大学 | Storage unit circuit with adaptive leakage current cutoff mechanism |
| CN102543157A (en) * | 2012-02-17 | 2012-07-04 | 安徽大学 | Double-bit-line sub-threshold storage unit circuit |
Non-Patent Citations (1)
| Title |
|---|
| BAI NA: "A differential read subthreshold SRAM bitcell with self-adaptive leakage cut off scheme", 《23RD IEEE INTERNATIONAL SOC CONFERENCE》 * |
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