CN104866345A

CN104866345A - Storage method of executable code under ARMv7m architecture

Info

Publication number: CN104866345A
Application number: CN201510262282.7A
Authority: CN
Inventors: 林志伟; 黄健
Original assignee: Fujian Centerm Information Co Ltd
Current assignee: Fujian Centerm Information Co Ltd
Priority date: 2015-05-21
Filing date: 2015-05-21
Publication date: 2015-08-26
Anticipated expiration: 2035-05-21
Also published as: CN104866345B

Abstract

The present invention provides a storage method of executable code under an ARMv7m architecture. The method involves five logic units including a compilation and burning program, a startup program, an FPB association program, an execution program, and a bus exception handling program. According to the method, the FPB association program associates a RAM space to an address that is not associated with a physical flash, and uses the RAM space as a storage space where the executable code is stored, and a CPU kernel uses the storage space to acquire and execute a machine instruction. In addition, the RAM space may be dynamically updated to a new value, and may be re-reset and re-associated by the FPB to a new flash address. With the method according to the present invention, a small on-chip flash is used to store FPB management code. As such, a small RAM space and a cheap off-chip flash are used to expand the storage space of the executable code to 512 MB.

Description

The storage means of executable code under a kind of ARMv7m framework

Technical field

The present invention relates to the storage means of executable code under a kind of ARMv7m framework, particularly a kind of executable code to be stored in sheet under ARMv7m framework outer without the method on the Flash of XIP.

Background technology

In computer systems, which, CPU needs first to extract machine instruction, then decoding, finally could perform machine instruction.Machine instruction needs to be stored in CPU and on the storer of directly address, could can be extracted by CPU.CPU can the storer of directly address be generally the flash storage of ram in slice, the outer RAM of parallel bus of sheet or support XIP (sheet performs) function of parallel bus.The unit storage space price of such storer is all higher, so embedded MCU generally can not configure the jumbo storer for storing run time version.This makes available software function in embedded MCU be restricted.If come the space of extension storage run time version by the storer extending out parallel bus, then can take the PIN resource of CPU, available IO resource is tailed off.There is a kind of Flash of the spi bus with XIP function at present on the market, the CPU of the specific SPI of support XIP Flash can be used for storing run time version.But this makes the type selecting of product solution be limited to specific Flash and CPU device.

ARM v7m is that ARM company issues the 7th edition MCU kernel framework.Under this framework, again because CPU matches the difference of part, derive the subtypes number such as Cortex-M3, Cortex-M4.Its chip usefulness of MCU based on this framework is relatively significantly improved with the processor such as ARM9/ARM11 before, has a wide range of applications in fields such as Industry Control, communication apparatus, ip intelligent peripherals.But, the MCU of ARMv7m framework, by above-mentioned mention can the restriction of the direct space size of store executable code, be difficult to be applied in the equipment of complex application context.This makes the equipment of complex application context have to use the ARM9/ARM11 processor that chip usefulness is low, or the processor of the high cost such as ARM v7r, ARM v7a, and then has influence on the sexual valence of product.

And in ARM v7m framework, there is a CPU optional component, be called FPB (Flash patch and breakpoint module), this assembly is for general in the processor of ARM v7m framework and realizes on-line debugging function.Although FPB is optional component, the MCU of current most ARM v7m realizes with FPB assembly.The operating mechanism of FPB is that provisional adapter CPU core is to the access of the flash storage of some address, Flash content in corresponding address is replaced to the instruction code stored in breakpoint code or the RAM that specifies and return to CPU core, make CPU core out of service because performing break-poing instruction, or perform the target instruction target word code be replaced.Arrange in ARM v7m framework, the 512MB space of 0x00000000 ~ 0x1FFFFFFF address is the Flash space that can store run time version simultaneously.Even if CPU only possesses the Flash space of 16KB, the address space of 0x4000 ~ 0x1FFFFFFF is still treated as the process of Flash address space by CPU core, and FPB can come into force equally on the address that this sheet does not have actual association physics Flash, that is, a slice ram space can be associated with on the address that a place do not associate with physics Flash by FPB, it can be used as the storage space storing executable code, obtain for CPU core and perform machine instruction; Meanwhile, this sheet ram space can dynamically be updated to new value, and can be reset by FPB and be associated with on new Flash address.Run time version on RAM by use time, can also deposit in outside sheet without on the SPI Nor Flash of XIP function or on Nand Flash, to memory device without too large requirement.

Therefore, if the Flash in a little blade can be used to store FPB management code, just can utilize little ram space and the outer Flash of cheap sheet, expand the storage space of the executable code of CPU to 512MB.In view of this, the present inventor spy concentrate on studies this thought implementation method and just have the present invention to come out.

Summary of the invention

The technical problem to be solved in the present invention, is to provide the storage means of executable code under a kind of ARMv7m framework, consume internal memory little, do not rely on specific Flash device, can by the execution space enlargement of program code to 512MB.

The present invention is achieved in that the storage means of executable code under a kind of ARMv7m framework, in compiling and burning program, by the parameter configuration of compiler, start-up routine, FPB associated program, executive routine, bus exception handler and system and driver are positioned on Flash address space that physical storage in CPU sheet associates, and other programs are positioned on Flash address space that CPU do not have physical storage to associate, compiling generates the binary image file of target executable code, then, this start-up routine, FPB associated program, executive routine, bus exception handler and system and driver are burnt on the CPU physical storage of assigned address when it compiles by software developer, and by other burning programs described on the outer Flash of sheet, first stage after device power starts, described start-up routine first initialization system and these basic running environment of device drives, initialization FPB assembly and software global variable successively, then start-up routine extracts the Flash executive address of the Article 1 instruction code of down-stream, send into described FPB associated program and carry out FPB association process, described FPB associated program can be called by described start-up routine and described executive routine, described FPB associated program imports address into parameterfor the Flash executive address of the Article 1 instruction code that this needs association to perform, perform " loading is performed code and it is carried out to the process of FPB association ", after obtaining the Flash executive address of the code that caller imports into, check whether the code of corresponding address has been loaded in RAM buffering, if code is not loaded in RAM buffering, then corresponding code is loaded in RAM buffering from the Flash sheet by Flash driver, after loading completes, calculate the memory address of code corresponding to program order address in RAM, if it is available that FPB assembly one has n unit, the Flash address space of each unit association m byte, the size definition that this RAM cushions is k byte, then k byte should at least equal n*m byte, by arranging FPB, the Flash executive address of the address ram and code that this address are started n*m byte realizes associating, described executive routine is called after described FPB associated program, described executive routine to import address parameter into identical with the address parameter that described FPB associated program imports into, the address parameter imported into is sent into the PC register of CPU by described executive routine, and then CPU will complete follow-up code implementation automatically, when described executive routine implementation causes bus exception, described bus exception handler is called to be performed, by inquiring about the abnormality register of CPU, thus know that abnormal is caused by CPU instruction fetch or accessed by cpu data to cause, caused by CPU instruction fetch if abnormal, then abnormal address is carried out re-association process as FPB associated program described in parameter call, accessed by cpu data if abnormal and cause, then described bus exception handler continues to check whether the instruction of exception throw is LDM multiregister load instructions, if, then CPU is replaced to complete the function of LDM instruction by described bus exception handler, then returning to next instruction code address allows CPU continue to perform, if not, the data address then will accessed carries out re-association process for FPB associated program described in parameter call.

Further, if CPU possesses DMA function, then described FPB associated program also performs " loading the process being judged to the code segment being about to be performed in advance " after performing described " loading is performed code and it is carried out to the process of FPB association ", should cushion as auxiliary RAM by the process of the code segment being about to be performed " load be judged in advance " ram space of opening up a slice equal with the RAM buffer size k byte of described " loading is performed code and carries out to it process that FPB associates ", then the k syllabified code Flash outside sheet followed closely after code that described " loading is performed code and it is carried out to the process of FPB association " load is loaded into during auxiliary RAM cushions, this loading procedure is realized by DMA, and the result that this " loading is judged to the process of the code segment being about to be performed in advance " performs is for accelerating next time " loading is performed code and it is carried out to the process of FPB association ".

Tool of the present invention has the following advantages:

The invention provides a kind of method stored by run time version with sheet on outer expensive storage device that can realize on common ARM v7m processor, the method can by the execution space enlargement of program code to 512MB, consume internal memory little, do not rely on specific Flash device, realize that cost is little, to realize income obvious, and be conducive to the application scenarios of complexity to realize on the MCU based on ARM v7m, expand the application scenarios of the MCU of ARM v7m, and reduce the cost of corresponding product.

Accompanying drawing explanation

The present invention is further illustrated in conjunction with the embodiments with reference to the accompanying drawings.

Fig. 1 is the inventive method flowchart.

Embodiment

As shown in Figure 1, the inventive method participates in primarily of five logical blocks, respectively: compiling and burning program 1, start-up routine 2, FPB associated program 3, executive routine 4 and bus exception handler 5.The matching relationship of these five logical blocks in overall process as shown in Figure 1.The software simulating of described start-up routine 2, FPB associated program 3, executive routine 4 and these four logical blocks of bus exception handler 5 is all stored in the code memory of the primary support of CPU, such as, be stored in Flash or ROM in sheet.

In described compiling and burning program 1, by the parameter configuration of compiler, start-up routine 2, FPB associated program 3, executive routine 4, bus exception handler 5 and system and driver are positioned on Flash address space that physical storage in CPU sheet associates, and other programs are positioned on Flash address space that CPU do not have physical storage to associate; Compiling generates the binary image file of target executable code; Then, this start-up routine 2, FPB associated program 3, executive routine 4, bus exception handler 5 and system and driver are burnt on the CPU physical storage of assigned address when it compiles by software developer, and by other burning programs described on the outer Flash of sheet.Wherein, described system and driver refer to the program that the implementation effect such as boot, task scheduling, timing function, system exception process, interrupt management, hardware device drivers can obviously affect by the code execution time and the program segment realizing this patent function; Other program described refers to implementation effect affects unconspicuous program by the code execution time, generally comprises the middle layer code, application software etc. of pure software logic.

First stage after device power starts, described start-up routine 2 first initialization system and these basic running environment of device drives, initialization FPB assembly and software global variable successively, then start-up routine extracts the Flash executive address of the Article 1 instruction code of down-stream, sends into described FPB associated program 3 and carries out FPB association process.

Described FPB associated program 3 can be called by described start-up routine 2 and described executive routine 4; Described FPB associated program 3 imports address into parameterfor the Flash executive address of the Article 1 instruction code that this needs association to perform, order is performed " loading is performed code and it is carried out to the process of FPB association " and " loading the process being judged to the code segment being about to be performed in advance " two processes by described FPB associated program 3.Wherein, " loading is performed code and it is carried out to the process of FPB association " is essential process, " load the process being judged to the code segment being about to be performed in advance " to match according to the configuration of CPU, even CPU possesses DMA function, then described FPB associated program also performs " loading the process being judged to the code segment being about to be performed in advance " after performing " loading is performed code and it is carried out to the process of FPB association ".

Described " loading is performed code and it is carried out to the process of FPB association " is after obtaining the Flash executive address of the code that caller imports into, check whether the code of corresponding address has been loaded in RAM buffering, if code is not loaded in RAM buffering, then corresponding code is loaded in RAM buffering from the Flash sheet by Flash driver, after loading completes, this process computation goes out the memory address of code corresponding to program order address in RAM, if it is available that FPB assembly one has n unit, the Flash address space of each unit association m byte, the size definition that this RAM cushions is k byte, then k byte should at least equal n*m byte, by arranging FPB, the Flash executive address of the address ram and code that this address are started n*m byte realizes associating,

Should cushion as auxiliary RAM by the process of the code segment being about to be performed " load be judged in advance " ram space of opening up a slice equal with the RAM buffer size k byte of described " loading is performed code and carries out to it process that FPB associates ", then be loaded into by the k syllabified code Flash outside sheet followed closely after code that described " loading is performed code and it is carried out to the process of FPB association " load during auxiliary RAM cushions, this loading procedure is realized by DMA; And the result that this " loading is judged to the process of the code segment being about to be performed in advance " performs is for accelerating next time " loading is performed code and it is carried out to the process of FPB association ".

Described executive routine 4 is called after described FPB associated program 3, described executive routine 4 to import address parameter into identical with the address parameter that described FPB associated program 3 imports into, the address parameter imported into is sent into the PC register of CPU by described executive routine 4, and then CPU will complete follow-up code implementation automatically;

Described bus exception handler 5 can be triggered in the process of described executive routine 4, when described executive routine 4 performs, if code perform this not by the Flash address of FPB specified associations and do not belong to physics Flash associate address time, can cannot extract machine instruction code due to CPU core and cause a bus extremely, described bus exception handler 5 is just associated with in bus exception vector at software development phase, therefore, during abnormal generation, described bus exception handler 5 is called performs.When described bus exception handler 5 called execution, by inquiring about the abnormality register of CPU, thus know that abnormal is caused by CPU instruction fetch or accessed by cpu data to cause, caused by CPU instruction fetch if abnormal, then abnormal address is carried out re-association process as FPB associated program described in parameter call 3, accessed by cpu data if abnormal and cause, then described bus exception handler 5 continues to check whether the instruction of exception throw is LDM multiregister load instructions, if, then CPU is replaced to complete the function of LDM instruction by described bus exception handler 5, then returning to next instruction code address allows CPU continue to perform, if not, the data address then will accessed carries out re-association process for FPB associated program described in parameter call 3.

Although the foregoing describe the specific embodiment of the present invention; but be familiar with those skilled in the art to be to be understood that; specific embodiment described by us is illustrative; instead of for the restriction to scope of the present invention; those of ordinary skill in the art, in the modification of the equivalence done according to spirit of the present invention and change, should be encompassed in scope that claim of the present invention protects.

Claims

1. the storage means of executable code under ARMv7m framework, is characterized in that:

In compiling and burning program, by the parameter configuration of compiler, start-up routine, FPB associated program, executive routine, bus exception handler and system and driver are positioned on Flash address space that physical storage in CPU sheet associates, and other programs are positioned on Flash address space that CPU do not have physical storage to associate; Compiling generates the binary image file of target executable code; Then, this start-up routine, FPB associated program, executive routine, bus exception handler and system and driver are burnt on the CPU physical storage of assigned address when it compiles by software developer, and by other burning programs described on the outer Flash of sheet;

First stage after device power starts, described start-up routine first initialization system and these basic running environment of device drives, initialization FPB assembly and software global variable successively, then start-up routine extracts the Flash executive address of the Article 1 instruction code of down-stream, send into described FPB associated program and carry out FPB association process, described FPB associated program can be called by described start-up routine and described executive routine;

Described FPB associated program imports the Flash executive address that address parameter is the Article 1 instruction code that this needs association to perform into, performs " loading is performed code and it is carried out to the process of FPB association ", after obtaining the Flash executive address of the code that caller imports into, check whether the code of corresponding address has been loaded in RAM buffering, if code is not loaded in RAM buffering, then corresponding code is loaded in RAM buffering from the Flash sheet by Flash driver, after loading completes, calculate the memory address of code corresponding to program order address in RAM, if it is available that FPB assembly one has n unit, the Flash address space of each unit association m byte, the size definition that this RAM cushions is k byte, then k byte should at least equal n*m byte, by arranging FPB, the Flash executive address of the address ram and code that this address are started n*m byte realizes associating,

Described executive routine is called after described FPB associated program, described executive routine to import address parameter into identical with the address parameter that described FPB associated program imports into, the address parameter imported into is sent into the PC register of CPU by described executive routine, and then CPU will complete follow-up code implementation automatically;

When described executive routine implementation causes bus exception, described bus exception handler is called to be performed, by inquiring about the abnormality register of CPU, thus know that abnormal is caused by CPU instruction fetch or accessed by cpu data to cause, caused by CPU instruction fetch if abnormal, then abnormal address is carried out re-association process as FPB associated program described in parameter call, accessed by cpu data if abnormal and cause, then described bus exception handler continues to check whether the instruction of exception throw is LDM multiregister load instructions, if, then CPU is replaced to complete the function of LDM instruction by described bus exception handler, then returning to next instruction code address allows CPU continue to perform, if not, the data address then will accessed carries out re-association process for FPB associated program described in parameter call.

2. the storage means of executable code under a kind of ARMv7m framework according to claim 1, it is characterized in that: if CPU possesses DMA function, then described FPB associated program also performs " loading the process being judged to the code segment being about to be performed in advance " after performing described " loading is performed code and it is carried out to the process of FPB association ", should cushion as auxiliary RAM by the process of the code segment being about to be performed " load be judged in advance " ram space of opening up a slice equal with the RAM buffer size k byte of described " loading is performed code and carries out to it process that FPB associates ", then the k syllabified code Flash outside sheet followed closely after code that described " loading is performed code and it is carried out to the process of FPB association " load is loaded into during auxiliary RAM cushions, this loading procedure is realized by DMA, and the result that this " loading is judged to the process of the code segment being about to be performed in advance " performs is for accelerating next time " loading is performed code and it is carried out to the process of FPB association ".