CN104866345B

CN104866345B - The storage method of executable code under a kind of ARMv7m frameworks

Info

Publication number: CN104866345B
Application number: CN201510262282.7A
Authority: CN
Inventors: 林志伟; 黄健
Original assignee: Fujian Centerm Information Co Ltd
Current assignee: Fujian Centerm Information Co Ltd
Priority date: 2015-05-21
Filing date: 2015-05-21
Publication date: 2018-03-23
Anticipated expiration: 2035-05-21
Also published as: CN104866345A

Abstract

The present invention provides a kind of storage method of executable code under ARMv7m frameworks, participated in by compiling and five burning program, startup program, FPB associated programs, configuration processor and bus exception handler logic units, a piece of ram space is associated with the address not associated at one with physics Flash by FPB associated programs, as the memory space for storing executable code, machine instruction is obtained and performed for CPU core and is used.The ram space can dynamically be updated to newly be worth simultaneously, and can be reset and be associated with new Flash addresses by FPB.So, the Flash storage FPB management codes in a small pieces piece are used only in the inventive method, it is possible to using little ram space and the outer Flash of cheap piece, the memory space of CPU executable code is expanded into 512MB.

Description

The storage method of executable code under a kind of ARMv7m frameworks

Technical field

The present invention relates to a kind of storage method of executable code under ARMv7m frameworks, and more particularly to one kind is in ARMv7m framves Executable code is stored in the method outside piece on the Flash without XIP under structure.

Background technology

In computer systems, CPU needs first to extract machine instruction and then decoding, finally could perform machine instruction. Machine instruction needs to be stored on the directly addressable memories of CPU, could be extracted by CPU.CPU is directly addressable to be deposited Reservoir is usually that the RAM of the parallel bus or support XIP of parallel bus (performs) function outside on piece for ram in slice, piece Flash storage.The unit memory space price of such memory is all higher, so will not typically match somebody with somebody in embedded MCU Put the memory for being available for storage to perform code of Large Copacity.This make it that available software function is restricted in embedded MCU. If performing the space of code by extending out the memory of parallel bus come extension storage, CPU PIN resource can be taken, Available I/O resource is set to tail off.There is a kind of Flash of the spi bus with XIP functions on the market at present, specifically supporting It can be used for storing execution code on SPIXIPFlash CPU.But this causes the type selecting of products scheme to be limited to specifically Flash and CPU devices.

ARM v7m are that ARM companies issue the 7th edition MCU core architecture.Under this framework, and because the difference of CPU apolegamy parts It is different, derive the subtypes number such as Cortex-M3, Cortex-M4.MCU based on this framework its chip efficiency it is relative with before The processors such as ARM9/ARM11 are significantly improved, and widely should have in fields such as Industry Control, communication apparatus, ip intelligent peripherals With.However, the MCU of ARM v7m frameworks, is limited by the space size that can directly store executable code mentioned above, it is difficult To be applied in the equipment of complex application context.It is low using chip efficiency that this make it that the equipment of complex application context is had to ARM9/ARM11 processors, or the processor of the high cost such as ARM v7r, ARM v7a, and then have influence on the sexual valence of product.

And a CPU optional component in ARM v7m frameworks be present, and referred to as FPB (Flash patches and breakpoint module), the group Part is for general in the processor of ARMv7m frameworks and realizes on-line debugging function.Although FPB is optional component, current big portion The ARMv7m divided MCU, which is realized, all carries FPB components.FPB operating mechanism is provisional adapter CPU core to some addresses The access of flash storage, the Flash content in corresponding address is substituted for what is stored in breakpoint code or the RAM specified Instruction code returns to CPU core, makes CPU core out of service because break-poing instruction is gone to, or performs what is be replaced Target instruction target word code.Arrange simultaneously in ARMv7m frameworks, the 512MB spaces of 0x00000000~0x1FFFFFFF addresses are to deposit Storage performs the Flash spaces of code.Even if only possess 16KB Flash spaces, 0x4000~0x1FFFFFFF address on CPU Space is still treated by CPU core as the processing of Flash address spaces, and FPB equally can not have actual association thing in this piece Manage Flash address on come into force, that is to say, that can by FPB by a piece of ram space be associated with one not with physics Flash On the address of association, as the memory space for storing executable code, machine instruction is obtained and performed for CPU core to be made With；Meanwhile this piece ram space can dynamically be updated to new value, and it can be reset by FPB and be associated with new Flash On address.When execution code on RAM is not used, can also deposit on the SPINorFlash without XIP functions outside piece or On person NandFlash, to storage device without too big requirement.

Therefore, if the Flash storage FPB management codes in a small pieces piece can be used, it is possible to utilize little ram space With Flash outside cheap piece, the memory space of CPU executable code is expanded to 512MB.In view of this, the present inventor is special The implementation method for the thought of concentrating on studies and just have appearance of the present invention.

The content of the invention

The technical problem to be solved in the present invention, it is the storage method that executable code under a kind of ARMv7m frameworks is provided, Consume internal memory it is small, independent of specific Flash devices, can be by the execution space enlargement of program code to 512MB.

What the present invention was realized in：The storage method of executable code under a kind of ARMv7m frameworks, in compiling and burning In program, by the parameter configuration of compiler, by startup program, FPB associated programs, configuration processor, bus exception handler It is positioned at system and driver on the Flash address spaces that physical storage in CPU pieces associates, and other programs is positioned In on the Flash address spaces for not having physical storage to associate in CPU pieces；The binary system mirror of compiling generation target executable code As file；Then, software developer by the startup program, FPB associated programs, configuration processor, bus exception handler and System and driver are specified on the CPU physical storages of address when being burnt to its compiling, and other described burning programs are arrived On the outer Flash of piece；First stage after device power startup, the startup program first initializes system successively and equipment is driven Dynamic, initialization FPB components and software global variable these basic running environment, then startup program extract down-stream The Flash of first instruction code performs address, is sent into the FPB associated programs and carries out FPB association process, the FPB associations Program can be called by the startup program and the configuration processor；The FPB associated programs are passed to address parameter to be needed for this The Flash for associating first instruction code performed performs address, and " loading is performed code and carries out FPB associations to it for execution Process "；After the Flash for obtaining the incoming code of caller performs address, check corresponding address code whether by It is loaded into RAM bufferings, if code is not loaded into RAM bufferings, passes through Flash of the Flash drivers outside piece It is middle that corresponding code is loaded into RAM bufferings, after the completion of loading, calculate the depositing in RAM of code corresponding to program order address Address is stored up, n unit is available if FPB components one share, and each unit associates the Flash address spaces of m byte, should The size of RAM bufferings is defined as k bytes, then k bytes should be at least equal to n*m bytes, by setting FPB, by the storage address Start the address ram of n*m bytes to associate with the Flash execution address realization of code；The configuration processor associates journey in the FPB Called after sequence, the incoming address parameter of the configuration processor is identical with the address parameter that the FPB associated programs are passed to, institute The PC registers that incoming address parameter is sent into CPU by configuration processor are stated, then CPU performed follow-up code is automatically performed Journey；When the configuration processor implementation procedure triggers bus exception, the bus exception handler is called to be performed, by looking into CPU abnormality register is ask, so as to know that abnormal is to be triggered by CPU instruction fetch or accessed by cpu data to trigger, if different Often triggered by CPU instruction fetch, then re-association processing is carried out using abnormal address as FPB associated programs described in parameter call, if different Often accessed and triggered by cpu data, then the bus exception handler continues checking for triggering whether abnormal instruction is that LDM is posted more Storage loading instruction, if so, then replacing CPU to complete the function of LDM instructions by the bus exception handler, is then back to down One instruction code address allows CPU to continue executing with, if it is not, the data address that will then access is as FPB described in parameter call Associated program carries out re-association processing.

Further, if CPU possesses DMA functions, the FPB associated programs are " loading is performed code described in execution And the process of FPB associations is carried out to it " and " process of the pre- code segment for being judged to be performed of loading " is also performed afterwards, " it should add Carry the process of the pre- code segment for being judged to be performed " open up it is a piece of with described " loading is performed code and carries out FPB passes to it The ram space that the RAM buffer size k bytes of the process of connection " are equal buffers as auxiliary RAM, then tightens the Flash outside piece K syllabified codes loading after the code loaded with " loading is performed code and carries out the process of FPB associations to it " Into auxiliary RAM bufferings, the loading procedure is realized by DMA；And should the " mistake of the pre- code segment for being judged to be performed of loading The result that journey " performs is used to accelerate next time " loading is performed code and carries out the process of FPB associations to it ".

The invention has the advantages that：

The invention provides it is a kind of can be realized on common ARMv7m processors will perform code storage with piece outside Method on expensive storage device, this method can by the execution space enlargement of program code to 512MB, consume internal memory it is small, independent of In specific Flash devices, realize that cost is small, realize that income is obvious, and be advantageous to the application scenarios of complexity being now based in fact On ARMv7m MCU, expand ARMv7m MCU application scenarios, and reduce the cost of corresponding product.

Brief description of the drawings

The present invention is further illustrated in conjunction with the embodiments with reference to the accompanying drawings.

Fig. 1 is the inventive method execution flow chart.

Embodiment

As shown in figure 1, the inventive method is mainly participated in by five logic units, it is respectively：Compiling and burning program 1, open Dynamic program 2, FPB associated programs 3, configuration processor 4 and bus exception handler 5.This five logic units are in overall process In matching relationship it is as shown in Figure 1.The startup program 2, FPB associated programs 3, configuration processor 4 and bus abnormality processing journey The software of this four logic units of sequence 5 is realized and is stored in the code memory of the primary supports of CPU, such as is stored in piece In Flash or ROM.

In the compiling and burning program 1, by the parameter configuration of compiler, by startup program 2, FPB associated programs 3rd, configuration processor 4, bus exception handler 5 and system and driver are positioned at what physical storage in CPU pieces associated On Flash address spaces, and other programs are positioned in CPU pieces on the Flash address spaces for not having physical storage to associate； The binary image file of compiling generation target executable code；Then, software developer associates the startup program 2, FPB Program 3, configuration processor 4, bus exception handler 5 and system and driver are burnt to the CPU that address is specified during its compiling On physical storage, and by other described burning programs to Flash outside piece.Wherein, the system and driver refer to The implementation effects such as bootstrap, task scheduling, timing function, system exception processing, interrupt management, hardware device drivers can be obvious The program of time effects is performed by code and realizes the program segment of this patent function；Other programs refer to implementation effect by Code performs the unconspicuous program of time effects, generally comprises middle layer identification code, application software of pure software logic etc..

First stage after device power startup, the startup program 2 first initialize system and device drives, just successively Beginningization FPB components and software global variable these basic running environment, then startup program extract the first of down-stream The Flash of bar instruction code performs address, is sent into the FPB associated programs 3 and carries out FPB association process.

The FPB associated programs 3 can be called by the startup program 2 and the configuration processor 4；The FPB associated programs 3 Incoming addressParameterThe Flash that first instruction code performed is associated for this needs performs address, the FPB associated programs Order is performed " loading is performed code and carries out the process of FPB associations to it " and " the loading pre- generation for being judged to be performed by 3 Two processes of the process of code section ".Wherein, " loading is performed code and carries out the process of FPB associations to it " is essential process, " process of the pre- code segment for being judged to be performed of loading " can be matched according to CPU configuration, and even CPU possesses DMA functions, then The FPB associated programs also perform after " loading is performed code and carries out the process of FPB associations to it " is performed " to be loaded pre- It is judged to the process of code segment that will be performed ".

" loading is performed code and carries out the process of FPB associations to it " is obtaining the incoming code of caller After Flash performs address, check whether the code of corresponding address is already loaded into RAM bufferings, if code is not loaded In being buffered to RAM, then by the way that corresponding code is loaded into RAM bufferings in Flash of the Flash drivers outside piece, load Cheng Hou, the process calculate storage address of the code corresponding to program order address in RAM, if FPB components one share n list Member is available, and each unit associates the Flash address spaces of m byte, and the size of RAM bufferings is defined as k bytes, then k Byte at least equal to n*m bytes, by setting FPB, the storage address should be started the address ram and code of n*m bytes Flash performs address and realizes association；

Should " process of the pre- code segment for being judged to be performed of loading " open up it is a piece of with described " loading is performed code simultaneously The process of FPB associations is carried out to it " the equal ram space of RAM buffer size k bytes as auxiliary RAM bufferings, then by piece Follow the k after the code that " loading is performed code and carries out the process of FPB associations to it " is loaded on outer Flash closely Syllabified code is loaded into auxiliary RAM bufferings, and the loading procedure is realized by DMA；And " it should load and be judged to what will be performed in advance The result that the process of code segment " performs is used to accelerate next time " loading is performed code and carries out the process of FPB associations to it ".

The configuration processor 4 is called after the FPB associated programs 3, the incoming address parameter of the configuration processor 4 Identical with the address parameter that the FPB associated programs 3 are passed to, incoming address parameter is sent into CPU PC by the configuration processor 4 Register, then CPU will be automatically performed follow-up code implementation；

The bus exception handler 5 can be triggered during the configuration processor 4, in the configuration processor 4 During execution, if code goes to this not by the Flash addresses of FPB specified associations and is not belonging to the ground of physics Flash associations During location, because CPU core can not extract machine instruction code a secondary bus can be triggered abnormal, the bus abnormality processing journey Sequence 5 is just associated with bus exception vector in software development phase, therefore, bus exception handler when exception occurs 5 called execution.In the called execution of the bus exception handler 5, by inquiring about CPU abnormality register, , will if abnormal triggered by CPU instruction fetch so as to know that abnormal is to be triggered by CPU instruction fetch or accessed by cpu data to trigger Abnormal address carries out re-association processing as FPB associated programs 3 described in parameter call, if abnormal accessed by cpu data is triggered, The bus exception handler 5 continues checking for triggering whether abnormal instruction is the loading instruction of LDM multiregisters, if so, then Replace CPU to complete the function of LDM instructions by the bus exception handler 5, be then back to next instruction code address and allow CPU is continued executing with, if it is not, the data address that will then access carries out re-association as FPB associated programs 3 described in parameter call Processing.

Although the foregoing describing the embodiment of the present invention, those familiar with the art should manage Solution, the specific embodiment described by us are merely exemplary, rather than for the restriction to the scope of the present invention, are familiar with this The equivalent modification and change that the technical staff in field is made in the spirit according to the present invention, should all cover the present invention's In scope of the claimed protection.

Claims

A kind of 1. storage method of executable code under ARMv7m frameworks, it is characterised in that：

Compile and burning program in, by the parameter configuration of compiler, by startup program, FPB associated programs, configuration processor, Bus exception handler, system and driver are positioned on the Flash address spaces that physical storage associates in CPU pieces, And other programs are positioned in CPU pieces on the Flash address spaces for not having physical storage to associate；Compiling generation target can be held The binary image file of line code；Then, software developer is by the startup program, FPB associated programs, configuration processor, total Line exception handler, system and driver are specified on the CPU physical storages of address when being burnt to its compiling, and by described in Other burning programs are on Flash outside piece；

First stage after device power startup, the startup program first initialize system and device drives, initialization successively FPB components and software global variable these basic running environment, then startup program extract first finger of down-stream Make the Flash of code perform address, be sent into the FPB associated programs and carry out FPB association process, the FPB associated programs energy quilt The startup program and the configuration processor are called；

The Flash that the FPB associated programs are passed to first instruction code that address parameter associates execution for this needs is performed Address, perform " loading is performed code and carries out the process of FPB associations to it "；Obtaining the incoming code of caller After Flash performs address, check whether the code of corresponding address is already loaded into RAM bufferings, if code is not loaded In being buffered to RAM, then by the way that corresponding code is loaded into RAM bufferings in Flash of the Flash drivers outside piece, load Cheng Hou, storage address of the code corresponding to program order address in RAM is calculated, if FPB components one share n unit and are available for Use, each unit associates the Flash address spaces of m byte, and the size of RAM bufferings is defined as k bytes, then k bytes should , by setting FPB, the Flash of address ram and code that the storage address starts n*m bytes should be held at least equal to n*m bytes Row address realizes association；

The configuration processor is called after the FPB associated programs, the incoming address parameter of the configuration processor and described The incoming address parameter of FPB associated programs is identical, and incoming address parameter is sent into CPU PC registers by the configuration processor, Then CPU will be automatically performed follow-up code implementation；

When the configuration processor implementation procedure triggers bus exception, the bus exception handler is called to be performed, and is passed through CPU abnormality register is inquired about, so as to know that abnormal is to be triggered by CPU instruction fetch or accessed by cpu data to trigger, if It is abnormal to be triggered by CPU instruction fetch, then re-association processing is carried out using abnormal address as FPB associated programs described in parameter call, if Abnormal accessed by cpu data is triggered, then the bus exception handler continues checking for triggering whether abnormal instruction is LDM more Register load instruction, if so, then replacing CPU to complete the function of LDM instructions by the bus exception handler, it is then back to Next instruction code address allows CPU to continue executing with, if it is not, the data address that will then access is as described in parameter call FPB associated programs carry out re-association processing.
2. the storage method of executable code under a kind of ARMv7m frameworks according to claim 1, it is characterised in that：If CPU possesses DMA functions, then the FPB associated programs are " loading is performed code and carries out FPB associations to it described in execution Process " also performs " process of the pre- code segment for being judged to be performed of loading " afterwards, " should load and be judged to what will be performed in advance The process of code segment " is opened up a piece of big with the RAM bufferings of " loading is performed code and the process that FPB associates is carried out to it " Then the equal ram space of small k bytes will follow that described " loading is performed generation closely as auxiliary RAM bufferings on the Flash outside piece Code simultaneously carries out the process of FPB associations to it " the k syllabified codes after the code that is loaded are loaded into auxiliary RAM bufferings, should plus Load process is realized by DMA；And it is somebody's turn to do the result that " process of the pre- code segment for being judged to be performed of loading " performs and is used to accelerate " loading is performed code and carries out the process of FPB associations to it " next time.