CN104852736A - Analog-to-digital converter of gradually-approaching type, and conversion method - Google Patents
Analog-to-digital converter of gradually-approaching type, and conversion method Download PDFInfo
- Publication number
- CN104852736A CN104852736A CN201410052959.XA CN201410052959A CN104852736A CN 104852736 A CN104852736 A CN 104852736A CN 201410052959 A CN201410052959 A CN 201410052959A CN 104852736 A CN104852736 A CN 104852736A
- Authority
- CN
- China
- Prior art keywords
- sampling
- input signal
- capacitor
- capacitor array
- under
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
The invention reveals an analog-to-digital converter of gradually-approaching type, and a conversion method, and a sampling value of an input signal can be reduced, so as to avoid sampling distortion. The converter comprises a capacitor array which comprises at least one specific capacitor and at least one sampling capacitor and is used for sampling an input signal in one sampling mode; a comparator which is used for comparing a first voltage and a second voltage at a comparison mode, wherein the first and second voltages are from the capacitor array, thereby generating comparison results; a switching circuit which is used for determining the stored charge amount of the capacitor array in the sampling mode according to a control signal, and determining the first voltage in the comparison mode; and a control circuit which is used for generating the control signal in the sampling mode according to sampling setting, and generating the control signal in the comparison mode according to the comparison results. The specific capacitor does not carry out sampling in the sampling mode, and shares charges with the sampling capacitor in the comparison mode, so as to reduce the sampling value.
Description
Technical field
The present invention relates to modulus conversion technique, particularly relate to approaching analog to digital converter and conversion method gradually.
Background technology
Approaching analog to digital converter (Successive Approximation Analog-to-DigitalConverter) is that a kind of all possible quantification benchmark of foundation itself carries out dichotomizing search (Binary Search) to produce the transducer of digital output signal to analog input signal gradually.In the multiple analog to digital converter of approaching gradually, charge redistribution (Charge Redistribution) gradually approaching analog to digital converter is that kind of common enforcement is selected, and it utilizes a capacitor array to sample an analog input signal; Again the lower electrode plate of the multiple electric capacity in this capacitor array is coupled to a reference voltage according to capacitance order from large to small and a comparative result after completing sampling, with when charge conservation, change the voltage (that is voltage of the electric pole plate of the plurality of electric capacity) that this capacitor array exports; Then the output voltage of this capacitor array and the output voltage of another capacitor array or a fixed voltage is compared again successively, to produce above-mentioned comparative result; Finally produce a digital output signal according to this comparative result again.
For the device (such as a picture decoder) adopting above-mentioned charge redistribution approaching analog to digital converter gradually, if the peak value of analog input signal (such as a picture signal) is excessive and beyond the quantization resolution of this analog to digital converter, the digital output signal distortion of follow-up generation will be caused, therefore, prior art can utilize a programmable gain amplifier (Programmable Gain Amplifier, PGA) peak value of analog input signal is adjusted, to avoid the problem of described distortion.But, programmable gain amplifier has the characteristics such as the large and power consumption of circuit area is large, extra use programmable amplifier can cause cost to increase and power consumption problem, therefore the art solution of still needing one distortion can be avoided to reduce or prevent again cost and power consumption to increase.
Summary of the invention
An object of the present invention is to provide one approaching analog to digital converter and conversion method gradually, to solve the problem of prior art.
The invention discloses one approaching analog to digital converter gradually, the sampling value of an input signal can be determined.One embodiment of described transducer comprises: one first capacitor array, comprise multiple first electric capacity, be used for sampling one first input signal under a sampling mode, wherein the plurality of first electric capacity comprises at least one first specified capacitance and at least one first sampling capacitor, and often this first electric capacity comprise one first power on extreme with one first bottom electrode end; One comparator, is used under a comparison pattern, compare one first voltage from the first capacitor array and one second voltage, produces a comparative result by this; One first switching circuit, couple the first capacitor array, be used for determining the first capacitor array stored charge amount according to one first control signal under sampling mode, and determine according to this first control signal the first voltage that the first capacitor array exports under comparison pattern; And a control circuit, couple comparator and the first switching circuit, be used under sampling mode according to sampling setting generation first control signal, and the first control signal is produced according to comparative result under comparison pattern, wherein the first control signal makes the first specified capacitance not sample the first input signal via the first switching circuit under sampling mode, make the first sampling capacitor sample the first input signal simultaneously, and make the first capacitor array stop sampling via the first switching circuit under comparison pattern, and the first specified capacitance and the first sampling capacitor is made to share electric charge.
The invention also discloses one approaching D conversion method gradually, can determine the sampling value of an input signal, is performed by the analog to digital converter of approaching gradually of the present invention or its equivalent device.One embodiment of described method comprises: under a sampling mode, and utilize one first capacitor array sampling one first input signal, wherein the first capacitor array comprises at least one first specified capacitance and at least one first sampling capacitor; Under a comparison pattern, relatively from one first voltage and one second voltage of the first capacitor array, produce a comparative result by this, wherein the second voltage is relevant to one second input signal, and the second input signal is inversion signal or a predetermined reference signal of the first input signal; Under sampling mode, control one first switching circuit via one first control signal makes the first specified capacitance not sample this first input signal, makes the first sampling capacitor sample this first input signal simultaneously, determines the first capacitor array stored charge amount by this; Under comparison pattern, control the first switching circuit via the first control signal makes the first capacitor array stop sampling, and makes the first specified capacitance and the first sampling capacitor share electric charge, determines the first voltage that the first capacitor array exports by this; And according to sampling setting generation first control signal under sampling mode, and produce the first control signal according to comparative result under comparison pattern.
Another embodiment of the aforementioned D conversion method of approaching gradually comprises: receive one first input signal; One first capacitor array is utilized to sample this first input signal, to produce multiple first original samples value; Multiple comparative result is produced according to the plurality of first original samples value and multiple second original samples value or a reference value; Judge whether the change of the plurality of comparative result meets a preset style; And if the change of the plurality of comparative result meets this preset style, then adjust this first capacitor array, and sample this first input signal by this first capacitor array again, to produce multiple first adjustment sampling value, wherein the maximum of the plurality of first adjustment sampling value is less than the maximum of the plurality of first original samples value.
Feature for the present invention, implementation and effect, now coordinate diagram to be described in detail as follows preferred embodiment.
Accompanying drawing explanation
Fig. 1 a is the schematic diagram of the embodiment of the analog to digital converter of approaching gradually of the present invention under sampling mode;
Fig. 1 b is the schematic diagram of the embodiment of the analog to digital converter of approaching gradually of the present invention under comparison pattern;
Fig. 2 a is the schematic diagram of the embodiment of the analog to digital converter of approaching gradually of the present invention when sampling mode under Differential Input;
Fig. 2 b is the schematic diagram of the embodiment of the analog to digital converter of approaching gradually of the present invention when comparison pattern under Differential Input;
Fig. 3 a is the flow chart of an embodiment of the D conversion method of approaching gradually of the present invention;
Fig. 3 b is the flow chart of another embodiment of the D conversion method of approaching gradually of the present invention;
Fig. 4 a is the schematic diagram of the employing of the present invention embodiment of decoder under sampling mode of approaching analog to digital converter gradually; And
The schematic diagram of Fig. 4 b employing of the present invention embodiment of decoder under comparison pattern of approaching analog to digital converter gradually.
[the symbol simple declaration of figure]:
100 approaching analog to digital converters gradually
110 first capacitor arrays
112 first specified capacitance
114 first sampling capacitors
120 comparators
122 first input ends
124 second inputs
130 first switching circuits
132 first input switches
134 first sampling control switchs
140 control circuits
S1 first input signal
Ref1 first reference signal
V1 first voltage
V2 second voltage
Ctrl_1 first control signal
C1 first electric capacity
Embodiment
The term of following description is the idiom with reference to the art, and as this specification is illustrated part term or defines, the explanation of this part term should be as the criterion with the explanation of this specification or definition.
Content disclosed by the present invention comprises approaching analog to digital converter (SuccessiveApproximation Analog-to-Digital Converter gradually, SA ADC) with conversion method and adopt the decoder of approaching analog to digital converter gradually, the sampling value of an input signal can be reduced (if wherein this input signal is negative, this sampling value gets its absolute value), also decrement this input signal can be sampled, to avoid the problem of dtmf distortion DTMF that the peak value of this input signal is excessive caused.The present invention can be applicable to an integrated circuit (such as an analog front circuit) or a system and device (such as an image decoder), and being embodied as under possible prerequisite, the art has knows that the knowledgeable can select the assembly of equivalence to realize the present invention according to the disclosure of the specification usually.The members comprised due to device of the present invention may be separately known tip assemblies, therefore under the prerequisite not affecting the fully open of this device invention and exploitativeness, below illustrates that the details for known tip assemblies will be omitted.In addition, method of the present invention performs by device of the present invention or its equivalent device.Moreover, be embodied as under possible prerequisite, content disclosed by the art personnel Ke Yi the present invention and the demand of self optionally implement the part or all of technical characteristic of any embodiment, or optionally implement the combination of the part or all of technical characteristic of multiple embodiment, increase elasticity during the invention process by this.
Refer to Fig. 1 a and Fig. 1 b, it is the schematic diagram of an embodiment of the analog to digital converter of approaching gradually of the present invention, and wherein Fig. 1 a represents sampling mode, and Fig. 1 b represents comparison pattern.As shown in the figure, the transducer 100 of the present embodiment comprises: one first capacitor array 110; One comparator 120; One first switching circuit 130; And a control circuit 140.Described first capacitor array 110 comprises multiple first electric capacity C1, be used for sampling one first input signal S1 under a sampling mode, wherein multiple first electric capacity C1 comprises at least one first specified capacitance 112 and at least one first sampling capacitor 114, and each first electric capacity C1 all comprises one first powers on extreme with one first bottom electrode end, can be have polarity or non-polar electric capacity.Described comparator 120 comprises first input end 122 and one second input 124, be used under a comparison pattern, compare the one first voltage V1 from the first capacitor array 110 and one second voltage V2, produce a comparative result Comp by this, this comparative result Comp represents highest significant position (the Most SignificantBit of a digital output signal Dout respectively by generation order, MSB) to least significant bit (Least Significant Bit, LSB).Described first switching circuit 130 couples the first capacitor array 110, be used for determining the first capacitor array 110 stored charge amount according to one first control signal Ctrl_1 under sampling mode, and determine according to the first control signal Ctrl_1 the first voltage V1 that the first capacitor array 110 exports under comparison pattern.Described control circuit 140 couples comparator 120 and the first switching circuit 130, be used for setting generation first control signal Ctrl_1(as shown in Figure 1a according to a sampling under sampling mode), and the first control signal Ctrl_1(is produced as shown in Figure 1 b according to comparative result Comp under comparison pattern).More particularly, as shown in Figure 1a, the first control signal Ctrl_1 makes the first specified capacitance 112 not sample the first input signal S1 via the first switching circuit 130 under sampling mode, makes the first sampling capacitor 114 sample the first input signal S1 simultaneously; In addition, as shown in Figure 1 b, first control signal Ctrl_1 makes the first capacitor array 110 stop sampling via the first switching circuit 130 under comparison pattern, and make the first specified capacitance 112 and the first sampling capacitor 114 share electric charge, produce the initial value (that is sampling value of the first input signal S1) of the first voltage V1 by this, use for during follow-up comparison.After note that the initial value of generation first voltage V1, the transducer 100 of the present embodiment just can produce comparative result Comp successively according to existing manner of comparison and produce digital output signal Dout according to this; But, the control circuit 140 of the present embodiment except can according to aforementioned sampling setting via the first switching circuit 130 select from the first electric capacity C1 at least one of them as except the first specified capacitance 112, also can analyze digital output signal Dout(formerly further or say the result previously compared), and when analysis result points out output signal distortion or other problem, select other single or multiple first electric capacity C1 to be used as the first specified capacitance 112 by the first switching circuit 130, improve by this.
Referring again to Fig. 1 a, first switching circuit 130 comprises one first input switch 132 and one first and samples control switch 134, under sampling mode, the first control signal Ctrl_1 via the first input switch 132 to power on first of the first specified capacitance 112 extreme to be coupled in the first input signal S1 together with; And together with being coupled in the first input signal S1 by the first bottom electrode end of the first specified capacitance 112 via the first sampling control switch 134, avoid the first specified capacitance 112 to sample the first input signal S1 by this.In addition, same under sampling mode, first sampling capacitor 114 is coupled between the first input signal S1 and one first reference signal Ref1 via the first switching circuit 130 by the first control signal Ctrl_1, makes the first sampling capacitor 114 sample the first input signal S1 by this.Moreover refer to Fig. 1 b, under comparison pattern, the first control signal Ctrl_1 to power on first of the first specified capacitance 112 via the first input switch 132 and extremely to disconnect with the first input signal S1; And together with via the first sampling control switch 134 first bottom electrode end of the first specified capacitance 112 being coupled in the first reference signal Ref1; And share to realize electric charge via first of the first specified capacitance 112 and the first sampling capacitor 114 extreme connection that powers on, determine effective output voltage (that is first voltage V1) of the first capacitor array 110 by this, namely determine the efficient sampling value of the first input signal S1.
In sum, for example, assuming that the analog to digital converter 100 of the present embodiment is one or three bit pads, first capacitor array 110 comprises four the first electric capacity C1, the capacitance of the plurality of first electric capacity C1 is followed successively by 4C by size, 2C, C, C, wherein the capacitance of the first specified capacitance 112 is 4C, all the other electric capacity are the first sampling capacitor 114, in addition, first input signal S1 represents with common-mode voltage Vcm's and amplitude Vin/2 and (Vcm+Vin/2), first reference signal Ref1 represents with common-mode voltage Vcm's and reference voltage Vr and (Vcm+Vr), then at the end of sampling mode, the total electrical charge Qt that first capacitor array 110 stores is:
Qt＝4C×(S1-S1)+(2C+C+C)×(S1-Ref1)
＝4C×[(Vcm+Vin/2)-(Vcm+Vr)]
＝4C×[(Vin/2)-Vr]
=2C × Vin-4C × Vr (formula one)
Then, under comparison pattern, after the electric charge completed first shares (or saying charge redistribution), the total electrical charge Qt that the first capacitor array 110 stores is:
Qt＝4C×(V1-Ref1)+(2C+C+C)×(V1-Ref1)
＝8C×[(V1-(Vcm+Vr)]
=8C × V1-8C × Vcm-8C × Vr (formula two)
Due to electric charge share before and after total charge dosage answer conservation, therefore from the initial value that formula one and formula two can obtain the first voltage V1 be:
2C×Vin-4C×Vr＝8C×V1-8C×Vcm-8C×Vr
8C×V1＝2C×Vin+4C×Vr+8C×Vcm
V1=Vin/4+Vr/2+Vcm (formula three)
Therefore, utilize all electric capacity to carry out sampling with prior art and the initial value that obtains the first voltage V1 for compared with (Vin/2+Vcm), the initial value of the first voltage V1 (also for extreme value) can be adjusted to (Vin/4+Vr/2+Vcm) by the present embodiment, avoids the peak value (Vin/2) of the first input signal S1 excessive by this and the problem of dtmf distortion DTMF that causes.Please note, though above-mentioned example is the maximum capacitors (capacitance 4C) in the first capacitor array 110 for the first specified capacitance 112, but enforcement restriction not of the present invention, in practical operation, first specified capacitance 112 also can be other electric capacity, the electric capacity of to be such as capacitance be 2C or C, or capacitance is the available capacitor combination of (2C+C)=3C etc., in principle, the total capacitance value of the first specified capacitance 112 is larger, the more, that is the sampling value of input signal S1 reduces the more the range of decrease of the initial value of the first voltage V1.The ratio that wherein sampling value of this input signal S1 reduces depends on the total capacitance value of the first capacitor array 110 and the ratio of the first specified capacitance 112.
Please again consult Fig. 1 a, 1b, if the transducer of the present embodiment 100 is the transducer of a single ended input, then the second voltage V2 can be a predetermined reference signal (such as an earthed voltage or a direct voltage); If but transducer 100 is the transducer of a Differential Input, then the second voltage V2 can be the output voltage of another capacitor array.As shown in Fig. 2 a and Fig. 2 b, when transducer 100 be input as Differential Input time, transducer 100 comprises further: one second capacitor array 150, comprise multiple second electric capacity C2, be used under sampling mode, sampling one second input signal S2(as shown in Figure 2 a), wherein the second input signal S2 is the inversion signal of the first input signal S1, second electric capacity C2 comprises at least one second specified capacitance 152 and at least one second sampling capacitor 154, each second electric capacity C2 comprises one second and powers on extremely and one second bottom electrode end, and comparator 120 receives the second voltage V2 that the second capacitor array 150 exports and itself and the first voltage V1 is compared (as shown in Figure 2 b) under comparison pattern, and a second switch circuit 160, couple the second capacitor array 150, be used for determining the second capacitor array 150 stored charge amount (as shown in Figure 2 a) according to one second control signal Ctrl_2 under sampling mode, and under comparison pattern, the output voltage (i.e. the second voltage V2) (as shown in Figure 2 b) of the second capacitor array 150 is determined according to the second control signal Ctrl_2, wherein aforementioned control circuit 140 sets generation second control signal Ctrl_2 according to aforementioned sampling under sampling mode, separately under comparison pattern, produce the second control signal Ctrl_2 according to comparative result Comp.Described second control signal Ctrl_2 makes the second specified capacitance 152 not sample this second input signal S2 via second switch circuit 160 under sampling mode, makes at least one second sampling capacitor 154 in other second electric capacity C2 sample this second input signal S2 simultaneously; And make the second capacitor array 150 stop sampling via second switch circuit 160 under comparison pattern, and the second specified capacitance 152 and the second sampling capacitor 154 is made to share electric charge.
Be similar to the operation of the first switching circuit 130, second switch circuit 160 comprises one second input switch 162 and one second and samples control switch 164, under sampling mode, powering on of second specified capacitance 152 is extremely coupled to the second input signal S2 via this second input switch 162 by the second control signal Ctrl_2, via the second sampling control switch 164, the bottom electrode end of the first specified capacitance 152 is coupled to the second input signal S2, and via second switch circuit 160, second sampling capacitor 154 is coupled between the second input signal S2 and one second reference signal Ref2, under comparison pattern, second control signal Ctrl_2 to power on second of the second specified capacitance 152 via this second input switch 162 and extremely to disconnect with the second input signal S2, via the second sampling control switch 164, second bottom electrode end of the second specified capacitance 152 is coupled to the second reference signal Ref2, and shared to complete electric charge via second of the second specified capacitance 152 and the second sampling capacitor 154 extreme connection that powers on.
In the present embodiment, the structure of first and second capacitor array 110,150 is corresponding mutually with operation, wherein the capacitance of first and second specified capacitance 112,152 is equal, and the capacitance of first and second sampling capacitor 114,154 is equal, and first and second reference signal Ref1, Ref2 are equal.In addition, when comparator 120 complete primary relatively after, if the first voltage V1 is greater than the second voltage V2(that is highest significant position is 1), then the lower electrode plate of the maximum capacitor of the first capacitor array 110 can be coupled to the 3rd reference signal Ref3 in one the 3rd this example of reference signal Ref3(by the first reference signal Ref1 according to this comparative result Comp and be less than the first reference signal Ref1 by control circuit 140), then comparator 120 can carry out second time again and compares, if this time comparative result Comp shows the first voltage V1 and is less than the second voltage V2(that is secondary high significance bit is 0), then the lower electrode plate of the secondary bulky capacitor of the second capacitor array 150 can be coupled to the 4th reference signal in one the 4th this example of reference signal Ref4(by the second reference signal Ref2 and equal the 3rd reference signal Ref3 by control circuit 140), to carry out follow-up comparison according to similar fashion again, because above-mentioned manner of comparison belongs to prior art, and to be embodied as under possible prerequisite can replace by other manner of comparison, therefore do not affect disclosed by the present invention with exploitativeness when, the explanation of redundancy is omitted at this.Moreover, although the upper plate of specified capacitance keeps being connected with the upper plate of sampling capacitor in embodiment disclosed above, but those skilled in the art can arrange the isolated operation when sampling by specified capacitance and sampling capacitor according to disclosure of the present invention by switching circuit, to reach the object avoiding specified capacitance to sample and make sampling capacitor sample, in other words, the annexation of specified capacitance and sampling capacitor is not limited to the content of previous embodiment, but those skilled in the art can be adjusted change according to open and practical operation demand of the present invention.
Except device disclosed above invention, the present invention discloses one approaching D conversion method gradually accordingly, is to be performed by the analog to digital converter of approaching gradually of the present invention or its equivalent device.As shown in Figure 3 a, an embodiment of this method comprises the following step:
Step S310: under a sampling mode, utilize one first capacitor array sampling one first input signal, wherein the first capacitor array comprises at least one first specified capacitance and at least one first sampling capacitor.First capacitor array of this step is such as first capacitor array 110 of Fig. 1 a to Fig. 2 b.
Step S320: under a comparison pattern, relatively from one first voltage and one second voltage of the first capacitor array, produce a comparative result by this, wherein the second voltage is relevant to one second input signal, and the second input signal is inversion signal or a predetermined reference signal of the first input signal.This step performs by the comparator 120 of Fig. 1 a to Fig. 2 b.
Step S330: control one first switching circuit via one first control signal and make the first specified capacitance not sample the first input signal under aforementioned sampling mode, make the first sampling capacitor sample the first input signal simultaneously, determine the first capacitor array stored charge amount by this.First switching circuit of this step is such as first switching circuit 130 of Fig. 1 a to Fig. 2 b.
Step S340: control the first switching circuit via the first control signal and make the first capacitor array stop sampling under aforementioned comparison pattern, and make the first specified capacitance and the first sampling capacitor share electric charge, determine the first voltage that the first capacitor array exports by this.This step performs by the control circuit 140 of Fig. 1 a to Fig. 2 b.
Step S350: produce this first control signal according to a sampling setting under this sampling mode, and produce this first control signal according to aforementioned comparative result under this comparison pattern.This step performs by the control circuit 140 of Fig. 1 a to Fig. 2 b equally.
In addition to the implementation, another embodiment of this method first can judge that whether the sampling value of an input signal is excessive, more accordingly to determine whether reduce this input signal of sampling.As shown in Figure 3 b, described embodiment comprises the following step:
Step S30: receive one first input signal.
Step S32: utilize one first capacitor array to sample this first input signal, to produce multiple first original samples value.Described first capacitor array is such as first capacitor array 110 of Fig. 1 a to Fig. 2 b.
Step S34: produce multiple comparative result according to the plurality of first original samples value and multiple second original samples value or a reference value, wherein the plurality of second original samples value is such as the value that aforementioned second capacitor array 150 produces, and this reference value is such as a default fixed voltage.This step performs by the comparison circuit 120 of Fig. 1 a to Fig. 2 b.
Step S36: judge whether the change of the plurality of comparative result meets a preset style.In the present embodiment, this preset style refers to that the plurality of comparative result is all identical and (is such as 1, represents maximum or this reference value that all first original samples values are all greater than the second original samples value; Or be 0, represent minimum value or this reference value that all first original samples values are all less than the second original samples value).This step performs by the control circuit 140 of Fig. 1 a to Fig. 2 b.
Step S38: if the change of the plurality of comparative result meets this preset style, then adjust the electrical connection of this first capacitor array, and sample this first input signal by this first capacitor array again, to produce multiple first adjustment sampling value, wherein the maximum of the plurality of first adjustment sampling value is less than the maximum of the plurality of first original samples value.Described adjustment first capacitor array is such as make the current potential of two electrode tips of at least one first specified capacitance of the first capacitor array equal and can not sample, and makes two electrode tips of at least one first sampling capacitor of the first capacitor array couple this first input signal and one first reference signal respectively and can sample this first input signal; In addition, the sum total of the capacitance of above-mentioned first specified capacitance and the capacitance of the first sampling capacitor is a total capacitance value, and the maximum of the first original samples value and the first ratio adjusting the maximum of sampling value are decided by the ratio of the capacitance of this total capacitance value and this first sampling capacitor.This step performs by the control circuit 140 of Fig. 1 a to Fig. 2 b, switching circuit 130 and the first capacitor array 110.
Consider that the art has and usually know that the knowledgeable can understand this method working of an invention details and change by the disclosure content of disclosed device invention above, more particularly, the technical characteristic of aforementioned means invention all can be applicable in this method invention, therefore, under the prerequisite not affecting requirement and exploitativeness disclosed by this method invention, the explanation of repetition and redundancy is omitted at this.
In addition, present invention also proposes a kind of decoder adopting approaching analog to digital converter gradually, can avoid without the need to using programmable gain amplifier the problem of dtmf distortion DTMF that sampling value is excessive caused.As shown in Fig. 4 a and Fig. 4 b, an embodiment 400 of described decoder comprises: a filter 410, is used for producing a filtering signal Fin according to a primary signal Sin; And an approaching analog to digital converter 420 gradually, be used for producing a decoded signal Dout according to filtering signal Fin.Above-mentioned transducer 420 can be the transducer 100 of Fig. 1 a to Fig. 2 b, comprise: one first capacitor array 110, comprise multiple first electric capacity C1, be used for sampling the one first input signal S1(of filtering signal Fin under a sampling mode as shown in fig. 4 a), wherein multiple first electric capacity C1 comprises at least one first specified capacitance 112 and at least one first sampling capacitor 114; One comparator 120, is used under a comparison pattern, compare the one first voltage V1 from the first capacitor array 110 and one second voltage V2, produces a comparative result Comp(by this as shown in Figure 4 b); One first switching circuit 130, couple the first capacitor array 110, be used for determining the first capacitor array 110 stored charge amount according to one first control signal Ctrl_1 under sampling mode, and determine according to this first control signal Ctrl_1 the first voltage V1 that the first capacitor array 110 exports under comparison pattern; And a control circuit 140, couple comparator 120 and the first switching circuit 130, be used for according to a sampling setting generation first control signal Ctrl_1 under sampling mode, and produce the first control signal Ctrl_1 and decoded signal Dout according to comparative result Comp under comparison pattern.Described first control signal Ctrl_1 makes the first specified capacitance 112 not sample the first input signal S1 via the first switching circuit 130 under sampling mode, makes this first sampling capacitor 114 sample the first input signal S1 simultaneously; And make the first capacitor array 110 stop sampling via the first switching circuit 130 under comparison pattern, and the first specified capacitance 112 and the first sampling capacitor 114 is made to share electric charge.
Similarly, the art has knows that the knowledgeable can according to the explanation of disclosed apparatus and method embodiment to understand implementation detail and the change of the present embodiment usually above, more particularly, the technical characteristic of previous embodiment all can be applicable in the invention of this device, therefore, under the prerequisite not affecting this device disclosure of an invention requirement and exploitativeness, the explanation of repetition and redundancy is omitted at this.
Please note, though the embodiment of foregoing disclosure does not describe the practice of comparator, switching circuit and control circuit in detail, but the implementation detail of the plurality of circuit is this area have usually know the knowledgeable can according to disclosed by the present invention and prior art implemented, therefore not omitted at this about the part of technical characteristic of the present invention.Separately note that in the icon of this specification, the shape, size, ratio etc. of assembly are only signal, are to have for the art that usually to know that the knowledgeable understands the present invention used, and are not used to limit the present invention.
In sum, the analog to digital converter of approaching gradually of the present invention and conversion method and adopt the decoder of approaching analog to digital converter gradually can reduce the sampling value of an input signal to avoid distortion (if wherein this input signal is negative, then this sampling value gets its absolute value), and comprise at least following advantages: design uncomplicated, implement easily, can realize without the need to the design and production cost expending great number; Without the need to the sampling value adopting programmable gain amplifier can change input signal, reach the object of saving cost and power consumption.
Although describe embodiments of the invention as mentioned above; but the plurality of embodiment is not used for limiting the present invention; the art has knows that the knowledgeable can impose change according to the content expressed or imply of the present invention to technical characteristic of the present invention usually; all this kind change all may belong to patent protection category of the presently claimed invention; in other words, scope of patent protection of the present invention must be as the criterion depending on the claim person of defining of this specification.
[symbol description]
100: approaching analog to digital converter gradually
110: the first capacitor arrays
112: the first specified capacitance
114: the first sampling capacitors
120: comparator
122: first input end
124: the second inputs
130: the first switching circuits
132: the first input switches
134: the first sampling control switchs
140: control circuit
150: the second capacitor arrays
152: the second specified capacitance
154: the second sampling capacitors
160: second switch circuit
400: decoder
410: filter
420: analog to digital converter
S1: the first input signal
S2: the second input signal
Sin: primary signal
Fin: filtering signal
Ref1: the first reference signal
Ref2: the second reference signal
V1: the first voltage
V2: the second voltage
Comp: comparative result
Ctrl_1: the first control signal
Ctrl_2: the second control signal
Dout: digital output signal, decoded signal
C1: the first electric capacity
C2: the second electric capacity
S310: under a sampling mode, utilize one first capacitor array sampling one first input signal, wherein the first capacitor array comprises at least one first specified capacitance and at least one first sampling capacitor
S320: under a comparison pattern, compare one first voltage from the first capacitor array and one second voltage, produce a comparative result by this, wherein the second voltage is relevant to one second input signal
S330: control one first switching circuit via one first control signal and make the first specified capacitance not sample the first input signal under aforementioned sampling mode, make the first sampling capacitor sample the first input signal simultaneously, determine the first capacitor array stored charge amount by this
S340: control the first switching circuit via the first control signal and make the first capacitor array stop sampling under aforementioned comparison pattern, and make the first specified capacitance and the first sampling capacitor share electric charge, determine the first voltage that the first capacitor array exports by this
S350: produce this first control signal according to a sampling setting under this sampling mode, and produce this first control signal according to aforementioned comparative result under this comparison pattern
S30: receive one first input signal
S32: utilize one first capacitor array to sample this first input signal, to produce multiple first original samples value
S34: produce multiple comparative result according to the plurality of first original samples value and multiple second original samples value or a reference value
S36: judge whether the change of the plurality of comparative result meets a preset style.
S38: if the change of the plurality of comparative result meets this preset style, then adjust this first capacitor array, and again sample this first input signal by this first capacitor array, to produce multiple first adjustment sampling value, wherein the maximum of the plurality of first adjustment sampling value is less than the maximum of the plurality of first original samples value.
Claims (17)
1. an approaching analog to digital converter gradually, can determine the sampling value of an input signal, comprise:
One first capacitor array, comprise multiple first electric capacity, be used for sampling one first input signal under a sampling mode, wherein said multiple first electric capacity comprises at least one first specified capacitance and at least one first sampling capacitor, and each in described multiple first electric capacity all comprise one first power on extreme with one first bottom electrode end;
One comparator, is used under a comparison pattern, comparing one first voltage from described first capacitor array and one second voltage, to produce a comparative result;
One first switching circuit, couple described first capacitor array, be used for determining described first capacitor array stored charge amount according to one first control signal under described sampling mode, and determine according to described first control signal described first voltage that described first capacitor array exports under described comparison pattern; And
One control circuit, couples described comparator and described first switching circuit, is used for producing described first control signal according to a sampling setting under described sampling mode, and produces described first control signal according to described comparative result under described comparison pattern,
Wherein said first control signal makes described at least one first specified capacitance not sample described first input signal via described first switching circuit under described sampling mode, make described first input signal of described at least one first sampling capacitor sampling simultaneously, and make described first capacitor array stop sampling via described first switching circuit under described comparison pattern, and described at least one first specified capacitance and described at least one first sampling capacitor is made to share electric charge.
2. transducer according to claim 1, wherein said first switching circuit comprises one first input switch and one first and samples control switch, and under described sampling mode, described first control signal couples first of described at least one first specified capacitance via described first input switch and powers on extremely and described first input signal, the first bottom electrode end of described at least one first specified capacitance and described first input signal is coupled via described first sampling control switch, and via described first switching circuit, described at least one first sampling capacitor is coupled between described first input signal and one first reference signal, under described comparison pattern, described first control signal disconnects first of described at least one first specified capacitance via described first input switch and powers on extremely and described first input signal, the first bottom electrode end of described at least one first specified capacitance and described first reference signal is coupled via described first sampling control switch, and shared to reach electric charge via first of described at least one first specified capacitance and the described at least one first sampling capacitor extreme connection that powers on.
3. transducer according to claim 1, comprises further:
One second capacitor array, comprise multiple second electric capacity, be used for sampling one second input signal, and export described second voltage, wherein said multiple second electric capacity comprises at least one second specified capacitance and at least one second sampling capacitor, and each in described multiple second electric capacity all comprise one second power on extreme with one second bottom electrode end; And
One second switch circuit, couple described second capacitor array, be used for determining described second capacitor array stored charge amount according to one second control signal under described sampling mode, and determine according to described second control signal described second voltage that described second capacitor array exports under described comparison pattern, wherein said control circuit produces described second control signal according to described sampling setting under described sampling mode, and described second control signal is produced according to described comparative result under described comparison pattern
Wherein said second control signal makes described at least one second specified capacitance not sample described second input signal via described second switch circuit under described sampling mode, make described second input signal of described at least one second sampling capacitor sampling simultaneously, and make described second capacitor array stop sampling via described second switch circuit under described comparison pattern, and described at least one second specified capacitance and described at least one second sampling capacitor is made to share electric charge.
4. transducer according to claim 3, wherein said second switch circuit comprises one second input switch and one second and samples control switch, and under described sampling mode, described second control signal couples extreme and described second input signal of powering on of described at least one second specified capacitance via described second input switch, the bottom electrode end of described at least one first specified capacitance and described second input signal is coupled via described second sampling control switch, and via described second switch circuit, described at least one second sampling capacitor is coupled between described second input signal and one second reference signal, under described comparison pattern, described second control signal disconnects second of described at least one second specified capacitance via described second input switch and powers on extremely and described second input signal, the second bottom electrode end of described at least one second specified capacitance and described second reference signal is coupled via described second sampling control switch, and shared to complete electric charge via second of described at least one second specified capacitance and the described at least one second sampling capacitor extreme connection that powers on.
5. transducer according to claim 3, wherein said at least one first specified capacitance is equal with the capacitance of described at least one second specified capacitance, described at least one first sampling capacitor is equal with the capacitance of described at least one second sampling capacitor, and first and second reference signal described is equal.
6. transducer according to claim 1, wherein said second input signal is the inversion signal of described first input signal.
7. transducer according to claim 1, wherein said second input signal is a predetermined reference signal.
8. transducer according to claim 1, wherein said control circuit according to described sampling setting or the analysis of a previous comparative result, by described first switching circuit select from described multiple first electric capacity at least one of them as described at least one first specified capacitance.
9. an approaching D conversion method gradually, be by one gradually approaching analog to digital converter perform, the described analog to digital converter of approaching gradually can determine the sampling value of an input signal, and described method comprises:
Under a sampling mode, utilize one first capacitor array sampling one first input signal, wherein said first capacitor array comprises at least one first specified capacitance and at least one first sampling capacitor;
Under a comparison pattern, relatively from one first voltage and one second voltage of described first capacitor array, to produce a comparative result, wherein said second voltage is relevant to one second input signal, and described second input signal is inversion signal or a predetermined reference signal of described first input signal;
Under described sampling mode, control one first switching circuit via one first control signal makes described at least one first specified capacitance not sample described first input signal, make described first input signal of described at least one first sampling capacitor sampling, to determine described first capacitor array stored charge amount simultaneously;
Under described comparison pattern, control described first switching circuit via described first control signal makes described first capacitor array stop sampling, and make described at least one first specified capacitance and described at least one first sampling capacitor share electric charge, to determine described first voltage that described first capacitor array exports; And
Under described sampling mode, produce described first control signal according to a sampling setting, and produce described first control signal according to described comparative result under described comparison pattern.
10. conversion method according to claim 9, the step wherein making described at least one first specified capacitance not sample described first input signal comprises:
Under described sampling mode, controlling described first switching circuit via described first control signal makes two electrode tips of described at least one first specified capacitance all couple described first input signal, make described at least one first sampling capacitor be coupled between described first input signal and one first reference signal simultaneously
And the step making described at least one first specified capacitance and described at least one first sampling capacitor share electric charge comprises:
Under described comparison pattern, control described first switching circuit via described first control signal and described at least one first specified capacitance is coupled between described first reference signal and described at least one first sampling capacitor with shared electric charge.
11. conversion methods according to claim 9, wherein when described second input signal is the inversion signal of described first input signal, described conversion method comprises further:
Utilize described second input signal of one second capacitor array sampling, wherein said second capacitor array comprises at least one second specified capacitance and at least one second sampling capacitor;
Under described sampling mode, control a second switch circuit via one second control signal makes described at least one second specified capacitance not sample described second input signal, make described second input signal of described at least one second sampling capacitor sampling, to determine described second capacitor array stored charge amount simultaneously;
Under described comparison pattern, control described second switch circuit via described second control signal makes described second capacitor array stop sampling, and make described at least one second specified capacitance and described at least one second sampling capacitor share electric charge, to determine described second voltage that described second capacitor array exports; And
Under described sampling mode, produce described second control signal according to described sampling setting, and produce described second control signal according to described comparative result under described comparison pattern.
12. conversion methods according to claim 11, the step wherein making described at least one second specified capacitance not sample described second input signal comprises:
Under described sampling mode, controlling described second switch circuit via described second control signal makes two electrode tips of described at least one second specified capacitance all couple described second input signal, make described at least one second sampling capacitor be coupled between described second input signal and one second reference signal simultaneously
And the step making described at least one second specified capacitance and described at least one second sampling capacitor share electric charge comprises:
Under described comparison pattern, control described second switch circuit via described second control signal and described at least one second specified capacitance is coupled between described second reference signal and described at least one second sampling capacitor with shared electric charge.
13. conversion methods according to claim 9, comprise further:
According to the described analysis sampling setting or a previous comparative result, from described first capacitor array, select the combination of an electric capacity or multiple electric capacity as described at least one first specified capacitance by described first switching circuit.
14. 1 kinds of approaching D conversion methods gradually, be by one gradually approaching analog to digital converter perform, sampling one input signal can be reduced, comprise:
Receive one first input signal;
Utilize described first input signal of one first capacitor array sampling, to produce multiple first original samples value;
Multiple comparative result is produced according to described multiple first original samples value and multiple second original samples value or a reference value;
Judge whether the change of described multiple comparative result meets a preset style; And
If the change of described multiple comparative result meets described the preset style, then adjust described first capacitor array, and again by described first input signal of described first capacitor array sampling, to produce multiple first adjustment sampling value,
The maximum of wherein said multiple first adjustment sampling value is less than the maximum of described multiple first original samples value.
15. conversion methods according to claim 14, wherein said first capacitor array comprises at least one first specified capacitance and at least one first sampling capacitor, and the step adjusting described first capacitor array comprises:
Make two electrode tip equipotentials of described at least one first specified capacitance and can not sample, and making two electrode tips of described at least one first sampling capacitor couple described first input signal and one first reference signal respectively and can sample described first input signal.
16. conversion methods according to claim 15, the summation of the capacitance of wherein said at least one first specified capacitance and the capacitance of described at least one first sampling capacitor is a total capacitance value, and the maximum of described multiple first original samples value and described multiple first ratio adjusting the maximum of sampling value depend on the ratio of the capacitance of described total capacitance value and described at least one first sampling capacitor.
17. conversion methods according to claim 14, wherein said the preset style refers to that described multiple comparative result is all identical.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410052959.XA CN104852736B (en) | 2014-02-17 | 2014-02-17 | Gradual approaching analog-digital converter and conversion method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410052959.XA CN104852736B (en) | 2014-02-17 | 2014-02-17 | Gradual approaching analog-digital converter and conversion method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104852736A true CN104852736A (en) | 2015-08-19 |
| CN104852736B CN104852736B (en) | 2018-05-04 |
Family
ID=53852117
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410052959.XA Active CN104852736B (en) | 2014-02-17 | 2014-02-17 | Gradual approaching analog-digital converter and conversion method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104852736B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1732624A (en) * | 2002-12-27 | 2006-02-08 | 模拟装置公司 | Programmable input range SAR ADC |
| CN103036570A (en) * | 2011-10-10 | 2013-04-10 | 台湾积体电路制造股份有限公司 | Method and apparatus for programmable gain control useful with digital to analog converter |
| TW201332300A (en) * | 2012-01-17 | 2013-08-01 | Univ Nat Chiao Tung | Successive approximation analog-to-digital converter |
| CN103580692A (en) * | 2012-08-06 | 2014-02-12 | 瑞昱半导体股份有限公司 | Continuous Progressive Analog-to-Digital Converter and Analog-to-Digital Conversion Method |
-
2014
- 2014-02-17 CN CN201410052959.XA patent/CN104852736B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1732624A (en) * | 2002-12-27 | 2006-02-08 | 模拟装置公司 | Programmable input range SAR ADC |
| CN103036570A (en) * | 2011-10-10 | 2013-04-10 | 台湾积体电路制造股份有限公司 | Method and apparatus for programmable gain control useful with digital to analog converter |
| TW201332300A (en) * | 2012-01-17 | 2013-08-01 | Univ Nat Chiao Tung | Successive approximation analog-to-digital converter |
| CN103580692A (en) * | 2012-08-06 | 2014-02-12 | 瑞昱半导体股份有限公司 | Continuous Progressive Analog-to-Digital Converter and Analog-to-Digital Conversion Method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104852736B (en) | 2018-05-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102386923B (en) | Asynchronous successive approximation analog-to-digital converter and conversion method | |
| CN105391451A (en) | Successive approximation register analog to digital converter (SAR ADC) and switching method during analog-digital conversion thereof | |
| TWI521887B (en) | Successive approximation register anolog-to-digital converter | |
| KR20180044232A (en) | DAC capacitance array, SAR-type analog-to-digital converter and method of reducing power consumption | |
| CN106656185B (en) | Monoclinic analog-to-digital converter with digital double sampling function, chip and terminal | |
| US20110084866A1 (en) | Successive approximation analog to digital converter and method thereof | |
| CN102111156B (en) | Successive approximation register analog-to-digital conversion circuit for realizing minimal dynamic range | |
| US9041575B2 (en) | Analog-to-digital conversion apparatus and method capable of achieving fast settling | |
| CN107888190B (en) | Successive approximation type analog-digital converter based on asymmetric differential capacitor array | |
| CN106059589A (en) | N-bit low-power-consumption successive approximation analog-to-digital converter | |
| US7969204B1 (en) | Sample hold circuit and method thereof for eliminating offset voltage of analog signal | |
| CN104410419A (en) | Analog-digital converter with digital programmable gating window | |
| TWI524678B (en) | Successive approximation analog-to-digital converter and conversion method | |
| KR102139939B1 (en) | low power switching successive approximation register(SAR) analog-digital converter(ADC) and analog-digital converting method using the same | |
| CN102055475B (en) | Successive approximation analog-digital converter and method thereof | |
| CN107968656B (en) | Successive approximation type analog-digital converter and application switching method thereof | |
| CN108111171A (en) | Suitable for differential configuration gradual approaching A/D converter dullness formula method of switching | |
| CN101350621A (en) | A/D converter | |
| CN102480293B (en) | Analogue-digital converting device | |
| CN105811985A (en) | Second quantitative hybrid ADC (Analog-to-Digital Converter) | |
| CN101207383A (en) | Analog-digital converter structure | |
| CN109450449B (en) | Reference voltage control circuit and analog-to-digital converter | |
| CN113328752A (en) | Differential input type successive approximation analog-to-digital converter | |
| CN104852736A (en) | Analog-to-digital converter of gradually-approaching type, and conversion method | |
| CN115296670A (en) | Analog-to-digital conversion circuit, conversion method and fully-differential segmented ADC (analog-to-digital converter) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| EXSB | Decision made by sipo to initiate substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |