CN104852736B - Gradual approaching analog-digital converter and conversion method - Google Patents
Gradual approaching analog-digital converter and conversion method Download PDFInfo
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- CN104852736B CN104852736B CN201410052959.XA CN201410052959A CN104852736B CN 104852736 B CN104852736 B CN 104852736B CN 201410052959 A CN201410052959 A CN 201410052959A CN 104852736 B CN104852736 B CN 104852736B
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Abstract
The present invention discloses a kind of gradually approaching analog-digital converter and conversion method, the sampling value that can reduce an input signal includes to avoid sampling distortion, the gradual approaching analog-digital converter：One capacitor array, comprising an at least specified capacitance and an at least sampling capacitor, for sampling an input signal under a sampling mode；One comparator, for comparing the first voltage from the capacitor array and a second voltage under a comparison pattern, thereby produces a comparative result；One on-off circuit, for making decision the capacitor array stored charge amount in sampling mode according to a control signal, and makes decision the first voltage in comparison pattern；And a control circuit, for producing the control signal according to a sampling setting under sampling mode, and the comparative result according to comparator under comparison pattern produces the control signal.The specified capacitance, without sampling, and shares electric charge, to reduce sampling value under comparison pattern under sampling mode with sampling capacitor.
Description
Technical field
The present invention relates to modulus conversion technique, more particularly to gradually approaching analog-digital converter and conversion method.
Background technology
Gradual approaching analog-digital converter（Successive Approximation Analog-to-Digital
Converter）It is that one kind to carry out dichotomizing search to analog input signal according to all possible quantization benchmark itself
（Binary Search）To produce the converter of digital output signal.In a variety of gradually approaching analog-digital converters, electric charge weight
Distribution（Charge Redistribution）Gradual approaching analog-digital converter is kind of a common implementation selection, it utilizes an electricity
Hold array to be sampled an analog input signal；Complete after sampling again by the bottom electrode plate of multiple capacitances in the capacitor array
A reference voltage is coupled to according to capacitance order from large to small and a comparative result, in the case of charge conservation, to change
Become the voltage that the capacitor array is exported（That is, the voltage of the electric pole plate of the plurality of capacitance）；Then the capacitance is compared successively again
The output voltage or a fixed voltage of the output voltage of array and another capacitor array, to produce above-mentioned comparative result；Again finally
A digital output signal is produced according to the comparative result.
To the device using the gradual approaching analog-digital converter of above-mentioned charge redistribution（A such as picture decoder）For,
If analog input signal（A such as picture signal）Peak value is excessive and quantization resolution beyond this analog-digital converter, just
It can cause the digital output signal distortion subsequently produced, therefore, the prior art can utilize a programmable gain amplifier
（Programmable Gain Amplifier,PGA）To adjust the peak value of analog input signal, to avoid asking for the distortion
Topic.However, programmable gain amplifier has circuit area big and the characteristics such as power consumption is big, additionally using programmable amplifier
It can cause cost increase and power consumption problem, therefore the art stills need one and distortion can be avoided to reduce or prevent into again
Sheet and the increased solution of power consumption.
The content of the invention
The purpose of the present invention is to provide a kind of gradually approaching analog-digital converter and conversion method, to solve previous skill
The problem of art.
The invention discloses a kind of gradually approaching analog-digital converter, the sampling value of an input signal can be determined.It is described
One embodiment of converter includes：One first capacitor array, comprising multiple first capacitances, for sampling one under a sampling mode
First input signal, wherein the plurality of first capacitance includes at least one first specified capacitance and at least one first sampling capacitor, and
Often first capacitance comprising one first power on extremely with one first bottom electrode end；One comparator, for comparing under a comparison pattern
Compared with the first voltage from the first capacitor array and a second voltage, a comparative result is thereby produced；One first switch circuit,
The first capacitor array is coupled, for determining the electricity that the first capacitor array stored according to a first control signal under sampling mode
Lotus amount, and under comparison pattern the first voltage that the first capacitor array exported is determined according to the first control signal；And one
Control circuit, coupling comparator and first switch circuit, for producing the first control according to a sampling setting under sampling mode
Signal, and first control signal is produced according to comparative result under comparison pattern, wherein first control signal is under sampling mode
The first specified capacitance is not sampled the first input signal via first switch circuit, while make the sampling first of the first sampling capacitor defeated
Enter signal, and the first capacitor array is stopped sampling via first switch circuit under comparison pattern, and make first to specify electricity
Hold and share electric charge with the first sampling capacitor.
The invention also discloses a kind of gradually approaching D conversion method, the sampling value of an input signal can be determined,
It is to be performed by gradual the approaching analog-digital converter or its equivalent device of the present invention.One embodiment of the method includes：
Under one sampling mode, one first input signal is sampled using one first capacitor array, wherein the first capacitor array includes at least one
First specified capacitance and at least one first sampling capacitor；Under a comparison pattern, compare one first from the first capacitor array
Voltage and a second voltage, thereby produce a comparative result, wherein second voltage is related to one second input signal, and second is defeated
Enter the inversion signal or a predetermined reference signal that signal is the first input signal；Via a first control signal under sampling mode
Control a first switch circuit the first specified capacitance is not sampled first input signal, while make the sampling of the first sampling capacitor should
First input signal, thereby determines the first capacitor array stored charge amount；Via first control signal under comparison pattern
Control first switch circuit makes the first capacitor array stop sampling, and the first specified capacitance is shared electricity with the first sampling capacitor
Lotus, thereby determines the first voltage that the first capacitor array is exported；And the is produced according to a sampling setting under sampling mode
One control signal, and under comparison pattern first control signal is produced according to comparative result.
Another embodiment of foregoing gradually approaching D conversion method includes：Receive one first input signal；Utilize one
First capacitor array samples first input signal, to produce multiple first original samples values；Original taken according to the plurality of first
Sample value and multiple second original samples values or a reference value produce multiple comparative results；Judge the change of the plurality of comparative result
Whether a preset style is met；And if the change of the plurality of comparative result meets the preset style, first capacitance is adjusted
Array, and first input signal is sampled by first capacitor array again, to produce multiple first adjustment sampling values, wherein should
The maximum of multiple first adjustment sampling values is less than the maximum of the plurality of first original samples value.
Feature, implementation and effect for the present invention, now coordinate diagram to describe preferred embodiment in detail as follows.
Brief description of the drawings
Fig. 1 a are the schematic diagram of an embodiment of the gradual approaching analog-digital converter of the present invention under sampling mode；
Fig. 1 b are the schematic diagram of an embodiment of the gradual approaching analog-digital converter of the present invention under comparison pattern；
Fig. 2 a are the embodiment of gradual approaching analog-digital converter of the invention under Differential Input in sampling mode
Schematic diagram；
Fig. 2 b are the embodiment of gradual approaching analog-digital converter of the invention under Differential Input in comparison pattern
Schematic diagram；
Fig. 3 a are the flow chart of an embodiment of the gradual approaching D conversion method of the present invention；
Fig. 3 b are the flow chart of another embodiment of the gradual approaching D conversion method of the present invention；
Fig. 4 a are an embodiment of the decoder of the gradual approaching analog-digital converter of use of the present invention under sampling mode
Schematic diagram；And
An embodiment of the decoder of the gradual approaching analog-digital converter of use of Fig. 4 b present invention under comparison pattern
Schematic diagram.
[the symbol simple declaration of figure]：
100 gradual approaching analog-digital converters
110 first capacitor arrays
112 first specified capacitances
114 first sampling capacitors
120 comparators
122 first input ends
124 second input terminals
130 first switch circuits
132 first input switches
134 first sampling controlling switches
140 control circuits
The first input signals of S1
The first reference signals of Ref1
V1 first voltages
V2 second voltages
Ctrl_1 first control signals
The first capacitances of C1
Embodiment
The term of following description is the idiom with reference to the art, is added as this specification has part term
To illustrate or define, the explanation of the part term should be subject to this specification explanation or definition.
Presently disclosed content includes gradual approaching analog-digital converter（Successive Approximation
Analog-to-Digital Converter,SA ADC）Translating with conversion method and using gradual approaching analog-digital converter
Code device, can reduce the sampling value of an input signal（If wherein the input signal is negative, which takes its absolute value）, that is,
It can be reduced and sample the input signal, to avoid the excessive caused problem of dtmf distortion DTMF of peak value of the input signal.The present invention can apply
In an integrated circuit（A such as analog front circuit）An or system and device（A such as image decoder）, and be embodied as can
On the premise of energy, it is real that the art tool usually intellectual can select equivalent component according to the disclosure of the specification
The existing present invention.It may be known tip assemblies for the members that are included by the device of the invention are independent, not influence
On the premise of the abundant open and exploitativeness of the device inventions, illustrate to be omitted for the details of known tip assemblies below.
In addition, the method for the present invention can be performed by the device of the invention or its equivalent device.Furthermore it is being embodied as possible premise
Under, those skilled in the art can optionally implement the portion of any embodiment according to presently disclosed content and the demand of itself
Point or all technical characteristic, or optionally implement the combination of the part or all of technical characteristic of multiple embodiments, thereby increase
Add elasticity during present invention implementation.
A and Fig. 1 b are please referred to Fig.1, it is the schematic diagram of an embodiment of the gradual approaching analog-digital converter of the present invention,
Wherein Fig. 1 a are to represent sampling mode, and Fig. 1 b are to represent comparison pattern.As shown in the figure, the converter 100 of the present embodiment includes：One
First capacitor array 110；One comparator 120；One first switch circuit 130；An and control circuit 140.First capacitance
Array 110 includes multiple first capacitance C1, for the one first input signal S1 of sampling under a sampling mode, plurality of first
Capacitance C1 includes at least one first specified capacitance 112 and at least one first sampling capacitor 114, and each first capacitance C1 is included
One first powers on extremely with one first bottom electrode end, can be polarized or non-polar capacitance.The comparator 120 includes one
122 and 1 second input terminal 124 of first input end, for comparing one from the first capacitor array 110 under a comparison pattern
A first voltage V1 and second voltage V2, thereby produces a comparative result Comp, and comparative result Comp is distinguished by generation order
Represent the highest significant position of a digital output signal Dout（Most Significant Bit,MSB）To least significant bit
（Least Significant Bit,LSB）.The first switch circuit 130 couples the first capacitor array 110, for sampling
Under pattern 110 stored charge amount of the first capacitor array is determined according to a first control signal Ctrl_1, and in comparison pattern
It is lower to determine the first voltage V1 that the first capacitor array 110 is exported according to first control signal Ctrl_1.The control circuit 140
Comparator 120 and first switch circuit 130 are then coupled, for producing the first control letter according to a sampling setting under sampling mode
Number Ctrl_1（As shown in Figure 1a）, and under comparison pattern first control signal Ctrl_1 is produced according to comparative result Comp（Such as
Shown in Fig. 1 b）.More particularly, as shown in Figure 1a, first control signal Ctrl_1 is electric via first switch under sampling mode
Road 130 makes the first specified capacitance 112 not sample the first input signal S1, while makes the first input of the first sampling capacitor 114 sampling
Signal S1；In addition, as shown in Figure 1 b, first control signal Ctrl_1 makes under comparison pattern via first switch circuit 130
One capacitor array 110 stops sampling, and the first specified capacitance 112 and the first sampling capacitor 114 is shared electric charge, thereby produces the
The initial value of one voltage V1（That is, first input signal S1 sampling value）, for being used during follow-up compare.It note that generation
After the initial value of one voltage V1, the converter 100 of the present embodiment can be sequentially generated comparative result according to existing manner of comparison
Comp simultaneously produces digital output signal Dout according to this；However, the control circuit 140 of the present embodiment according to foregoing sampling except can set
It is fixed selected via first switch circuit 130 from the first capacitance C1 at least one as the first specified capacitance 112 outside, also may be used
Further analyze first digital output signal Dout（Or say previous result of the comparison）, and point out output signal in analysis result
When distortion or other problems, other single or multiple first capacitance C1 are selected to be used as the first finger by first switch circuit 130
Determine capacitance 112, thereby improved.
Referring again to Fig. 1 a, first switch circuit 130 includes one first input switch 132 and one first sampling controlling switch
134, under sampling mode, first control signal Ctrl_1 is via the first input switch 132 by the first of the first specified capacitance 112
Power on and be extremely coupled together with the first input signal S1；And controlling switch 134 is sampled by the first specified capacitance 112 via first
The first bottom electrode end be coupled together with the first input signal S1, thereby avoid the first specified capacitance 112 sampling first input
Signal S1.In addition, equally under sampling mode, first control signal Ctrl_1 is sampled via first switch circuit 130 by first
Capacitance 114 is coupled between the first input signal S1 and one first reference signal Ref1, thereby samples the first sampling capacitor 114
First input signal S1.Furthermore b is please referred to Fig.1, under comparison pattern, first control signal Ctrl_1 is opened via the first input
Pass 132 powers on the first of the first specified capacitance 112 and is extremely disconnected with the first input signal S1；And opened via the first sampling control
134 are closed to be coupled together at the first bottom electrode end of the first specified capacitance 112 with the first reference signal Ref1；And via first
Specified capacitance 112 powers on extreme connection to realize that electric charge is shared with the first of the first sampling capacitor 114, thereby determines the first electricity
Hold effective output voltage of array 110（That is, first voltage V1）, that is, determine the efficient sampling value of the first input signal S1.
In conclusion for example, it is assumed that the analog-digital converter 100 of the present embodiment is one or three bit pads, the first capacitance
Array 110 includes four the first capacitance C1, and the capacitance of the plurality of first capacitance C1 is followed successively by 4C, 2C, C, C by size, wherein
The capacitance of first specified capacitance 112 is 4C, remaining capacitance is the first sampling capacitor 114, in addition, the first input signal S1 with
Common-mode voltage Vcm and amplitude Vin/2's and (Vcm+Vin/2) represent that the first reference signal Ref1 is with common-mode voltage Vcm and ginseng
Examine voltage Vr and (Vcm+Vr) represent, then at the end of sampling mode, total electrical charge Qt that the first capacitor array 110 is stored
For：
Qt=4C × (S1-S1)+(2C+C+C) × (S1-Ref1)
=4C × [(Vcm+Vin/2)-(Vcm+Vr)]
=4C × [(Vin/2)-Vr]
=2C × Vin-4C × Vr（Formula one）
Then, under comparison pattern, the electric charge completed first is shared（Or say charge redistribution）Afterwards, the first capacitor array
The 110 total electrical charge Qt stored are：
Qt=4C × (V1-Ref1)+(2C+C+C) × (V1-Ref1)
=8C × [(V1- (Vcm+Vr)]
=8C × V1-8C × Vcm-8C × Vr（Formula two）
Front and rear total charge dosage is shared due to electric charge and answers conservation, therefore can obtain first voltage V1's from formula one and formula two
Initial value is：
2C × Vin-4C × Vr=8C × V1-8C × Vcm-8C × Vr
8C × V1=2C × Vin+4C × Vr+8C × Vcm
V1=Vin/4+Vr/2+Vcm（Formula three）
Therefore, it is (Vin/2+ using the initial value that all capacitances were sampled and obtained first voltage V1 with prior art
Vcm) compare, the present embodiment can be by the initial value of first voltage V1（Also it is extreme value）(Vin/4+Vr/2+Vcm) is adjusted to, thereby
Problem of dtmf distortion DTMF caused by avoiding the peak value (Vin/2) of the first input signal S1 excessive.It note that though above-mentioned example refers to first
It is the maximum capacitor in the first capacitor array 110 to determine capacitance 112（Capacitance 4C）Exemplified by, but the simultaneously implementation limit of non-invention
System, in practical operation, the first specified capacitance 112 can also be other capacitances, be, for example, the capacitance that capacitance is 2C or C, or
Capacitance is (2C+C)=3C etc. available capacitor combination, and in principle, the total capacitance value of the first specified capacitance 112 is bigger,
The more, that is, the sampling value of input signal S1 reduces the more the range of decrease of the initial value of first voltage V1.The wherein input signal
The sampling value reduced scale of S1 depends on the total capacitance value of the first capacitor array 110 and the ratio of the first specified capacitance 112.
Referring to Fig. 1 a, 1b, if the converter 100 of the present embodiment is the converter of a single ended input, the second electricity
It can be a predetermined reference signal to press V2（Such as ground voltage or a DC voltage）；But if converter 100 is defeated for a difference
The converter entered, then second voltage V2 can be the output voltage of another capacitor array.As shown in Fig. 2 a and Fig. 2 b, work as converter
When 100 input is Differential Input, converter 100 further includes：One second capacitor array 150, includes multiple second capacitances
C2, for sampling one second input signal S2 under sampling mode（As shown in Figure 2 a）, wherein the second input signal S2 is first
The inversion signal of input signal S1, the second capacitance C2 include at least one second specified capacitance 152 and at least one second sampling capacitor
154, each second capacitance C2 are powered on extremely with one second bottom electrode end comprising one second, and comparator 120 is under comparison pattern
Receive the second voltage V2 that the second capacitor array 150 is exported and by it compared with first voltage V1（As shown in Figure 2 b）；
And a second switch circuit 160, couple the second capacitor array 150, under sampling mode according to a second control signal
Ctrl_2 determines 150 stored charge amount of the second capacitor array（As shown in Figure 2 a）, and controlled under comparison pattern according to second
Signal Ctrl_2 processed determines the output voltage of the second capacitor array 150（That is second voltage V2）（As shown in Figure 2 b）, wherein foregoing
Control circuit 140 produces second control signal Ctrl_2 under sampling mode according to foregoing sampling setting, separately under comparison pattern
Second control signal Ctrl_2 is produced according to comparative result Comp.The second control signal Ctrl_2 under sampling mode via
Second switch circuit 160 makes the second specified capacitance 152 not sample second input signal S2, while makes in other second capacitance C2
At least one second sampling capacitor 154 sample second input signal S2；And via second switch circuit under comparison pattern
160 make the second capacitor array 150 stop sampling, and the second specified capacitance 152 and the second sampling capacitor 154 is shared electric charge.
Similar to the operation of first switch circuit 130, second switch circuit 160 includes one second input switch 162 and one
Second sampling controlling switch 164, under sampling mode, second control signal Ctrl_2 is via second input switch 162 by the
Powering on for two specified capacitances 152 is extremely coupled to the second input signal S2, is specified via the second sampling controlling switch 164 by first
The bottom electrode end of capacitance 152 is coupled to the second input signal S2, and via second switch circuit 160 by the second sampling capacitor
154 are coupled between the second input signal S2 and one second reference signal Ref2；Under comparison pattern, second control signal
Ctrl_2 is powered on via second input switch 162 by the second of the second specified capacitance 152 extremely to break with the second input signal S2
Open, second bottom electrode end of the second specified capacitance 152 is coupled to the second reference signal via the second sampling controlling switch 164
Ref2, and power on extreme connection with the second of the second sampling capacitor 154 via the second specified capacitance 152 and be total to complete electric charge
Enjoy.
In the present embodiment, the structure of first and second capacitor array 110,150 and operation are mutually corresponding, wherein first with
The capacitance of second specified capacitance 112,152 is equal, and the capacitance of first and second sampling capacitor 114,154 is equal, and first
It is equal with the second reference signal Ref1, Ref2.In addition, after comparator 120 completes the comparison of first time, if first voltage V1 is big
In second voltage V2（That is, highest significant position is 1）, then control circuit 140 can be according to this comparative result Comp by the first capacitance battle array
The bottom electrode plate of the maximum capacitor of row 110 is coupled to one the 3rd reference signal Ref3 by the first reference signal Ref1（In this example
Three reference signal Ref3 are less than the first reference signal Ref1）, then comparator 120 can be compared for the second time again, if this time comparing
Show that first voltage V1 is less than second voltage V2 compared with result Comp（That is, secondary high significance bit is 0）, then control circuit 140 can be by the
The bottom electrode plate of the secondary bulky capacitor of two capacitor arrays 150 is coupled to one the 4th reference signal Ref4 by the second reference signal Ref2
（The 4th reference signal is equal to the 3rd reference signal Ref3 in this example）, subsequently to be compared according to similar fashion again, due to upper
State manner of comparison and belong to the prior art, and be embodied as it is possible under the premise of can be substituted by other manner of comparison, therefore
Do not influence it is presently disclosed with exploitativeness in the case of, the explanation of redundancy is omitted herein.It is furthermore described above
Although embodiment in the upper plate of specified capacitance and the upper plate of sampling capacitor keep connecting, but those skilled in the art can be according to the present invention
Disclosure by the setting of on-off circuit by specified capacitance and sampling capacitor the isolated operation in sampling, avoid specifying electricity to reach
The purpose held sampling and sample sampling capacitor, in other words, before the connection relation of specified capacitance and sampling capacitor is not limited to
State the content of embodiment, but those skilled in the art can disclosure under this invention and practical operation demand adjusted change.
In addition to device inventions described above, the present invention accordingly discloses a kind of gradually approaching analog-to-digital conversion side
Method, is performed by gradual the approaching analog-digital converter or its equivalent device of the present invention.As shown in Figure 3a, the one of this method is real
Example is applied to comprise the steps of：
Step S310：Under a sampling mode, one first input signal is sampled using one first capacitor array, wherein first
Capacitor array includes at least one first specified capacitance and at least one first sampling capacitor.First capacitor array of this step is, for example,
The first capacitor array 110 of Fig. 1 a to Fig. 2 b.
Step S320：Under a comparison pattern, compare a first voltage and a second voltage from the first capacitor array,
A comparative result is thereby produced, wherein second voltage is related to one second input signal, and the second input signal is the first input
The inversion signal of signal or a predetermined reference signal.This step can be performed by the comparator 120 of Fig. 1 a to Fig. 2 b.
Step S330：A first switch circuit is controlled to make the first finger via a first control signal under foregoing sampling mode
Determine capacitance and do not sample the first input signal, while the first sampling capacitor is sampled the first input signal, thereby determine the first capacitance
Array stored charge amount.The first switch circuit of this step is, for example, the first switch circuit 130 of Fig. 1 a to Fig. 2 b.
Step S340：Make the first capacitance battle array via first control signal control first switch circuit under foregoing comparison pattern
Row stop sampling, and the first specified capacitance is shared electric charge with the first sampling capacitor, thereby determine that the first capacitor array is exported
First voltage.This step can be performed by the control circuit 140 of Fig. 1 a to Fig. 2 b.
Step S350：The first control signal is produced according to a sampling setting under the sampling mode, and is compared at this
Under pattern the first control signal is produced according to foregoing comparative result.This step can equally pass through the control circuit of Fig. 1 a to Fig. 2 b
140 perform.
In addition to the implementation, another embodiment of this method can first judge whether the sampling value of an input signal is excessive,
Again accordingly to decide whether to down-sample the input signal.As shown in Figure 3b, the embodiment comprises the steps of：
Step S30：Receive one first input signal.
Step S32：First input signal is sampled using one first capacitor array, to produce multiple first original samples
Value.First capacitor array is, for example, the first capacitor array 110 of Fig. 1 a to Fig. 2 b.
Step S34：Produced according to the plurality of first original samples value and multiple second original samples values or a reference value
Multiple comparative results, wherein the plurality of second original samples value is, for example, value caused by foregoing second capacitor array 150, the ginseng
It is, for example, a default fixed voltage to examine value.This step can be performed by the comparison circuit 120 of Fig. 1 a to Fig. 2 b.
Step S36：Judge whether the change of the plurality of comparative result meets a preset style.In the present embodiment, this is default
Pattern refers to the plurality of comparative result all same（Such as be 1, represent all first original samples values and be all higher than second and original take
The maximum of sample value or the reference value；Or be 0, represent all first original samples values and be respectively less than the second original samples value most
Small value or the reference value）.This step can be performed by the control circuit 140 of Fig. 1 a to Fig. 2 b.
Step S38：If the change of the plurality of comparative result meets the preset style, the electricity of first capacitor array is adjusted
Property connection relation, and first input signal is sampled by first capacitor array again, to produce multiple first adjustment sampling values,
The maximum of wherein the plurality of first adjustment sampling value is less than the maximum of the plurality of first original samples value.The adjustment first
Capacitor array be, for example, make the first capacitor array at least two electrode tips of one first specified capacitance current potential it is equal and cannot
It is sampled, and two electrode tips of at least one first sampling capacitor of the first capacitor array is respectively coupled to the first input letter
Number first input signal can be sampled with one first reference signal；In addition, the capacitance of above-mentioned first specified capacitance
Sum total with the capacitance of the first sampling capacitor is a total capacitance value, and the maximum of the first original samples value takes with the first adjustment
The ratio of the maximum of sample value is decided by the total capacitance value and the ratio of the capacitance of first sampling capacitor.This step can pass through
The control circuit 140 of Fig. 1 a to Fig. 2 b, on-off circuit 130 are performed with the first capacitor array 110.
In view of the art, tool usually intellectual can pass through the disclosure content of device inventions described above
To understand the implementation detail of present method invention and change, more particularly, the technical characteristic of aforementioned means invention can be applied to
In present method invention, therefore, on the premise of requirement and the exploitativeness disclosed by present method invention is not influenced, repetition and redundancy
Explanation omitted herein.
In addition, present invention also proposes a kind of decoder using gradual approaching analog-digital converter, without using that can compile
Journey gain amplifier can avoid the excessive caused problem of dtmf distortion DTMF of sampling value.As shown in Fig. 4 a and Fig. 4 b, the decoder
One embodiment 400 includes：One wave filter 410, for producing a filtering signal Fin according to an original signal Sin；And one is gradual
Approaching analog-digital converter 420, for producing a decoded signal Dout according to filtering signal Fin.Above-mentioned converter 420 can be
The converter 100 of Fig. 1 a to Fig. 2 b, comprising：One first capacitor array 110, comprising multiple first capacitance C1, in a sampling
The one first input signal S1 of filtering signal Fin is sampled under pattern（As shown in fig. 4 a）, plurality of first capacitance C1 is comprising extremely
Few one first specified capacitance 112 and at least one first sampling capacitor 114；One comparator 120, for comparing under a comparison pattern
A first voltage V1 and a second voltage V2 from the first capacitor array 110, thereby produce a comparative result Comp（Such as Fig. 4 b
It is shown）；One first switch circuit 130, couples the first capacitor array 110, for believing under sampling mode according to one first control
Number Ctrl_1 determines 110 stored charge amount of the first capacitor array, and according to the first control signal under comparison pattern
Ctrl_1 determines the first voltage V1 that the first capacitor array 110 is exported；And a control circuit 140, coupling comparator 120 with
First switch circuit 130, for producing first control signal Ctrl_1 according to a sampling setting under sampling mode, and is comparing
Under pattern first control signal Ctrl_1 and decoded signal Dout is produced according to comparative result Comp.The first control signal
Ctrl_1 makes the first specified capacitance 112 not sample the first input signal S1 under sampling mode via first switch circuit 130, together
When make first sampling capacitor 114 sample the first input signal S1；And make under comparison pattern via first switch circuit 130
First capacitor array 110 stops sampling, and the first specified capacitance 112 and the first sampling capacitor 114 is shared electric charge.
Similarly, the art tool usually intellectual can be according to apparatus and method embodiment described above
Illustrate the implementation detail to understand the present embodiment and change, more particularly, the technical characteristic of previous embodiment can be applied to
In present apparatus invention, therefore, on the premise of the open request of present apparatus invention and exploitativeness is not influenced, repeat and redundancy
Illustrate to be omitted herein.
It note that though the practice of comparator, on-off circuit and control circuit is not described in detail for the embodiment of foregoing disclosure, but should
The implementation detail of multiple circuits is that one skilled in the art can come according to the presently disclosed and prior art
It is carried out, therefore not the part on the technical characteristic of the present invention is omitted herein.Separately it note that this specification
In icon, the shape of component, size, ratio etc. are only to illustrate, and are to understand the present invention for the art tool usually intellectual
It is used, and it is not used to the limitation present invention.
In conclusion the gradual approaching analog-digital converter of the present invention is with conversion method and using gradual approaching modulus
The decoder of converter can reduce the sampling value of an input signal to avoid distortion（If wherein the input signal is negative, this takes
Sample value takes its absolute value）, and include at least following advantages：Design uncomplicated, it is easy to implement, without expending the design and life of great number
Cost is produced to can be achieved；The sampling value of input signal can be changed without programmable gain amplifier, reach saving cost
With the purpose of power consumption.
Although the embodiment that the invention has been described as described above, but the plurality of embodiment is not used for limiting the present invention,
The art tool usually intellectual can impose the technical characteristic of the present invention according to the content expressed or implied of the present invention
Change, all this kind change may belong to patent protection category of the presently claimed invention, in other words, patent protection of the invention
Scope must be regarded subject to the as defined in claim of this specification.
[symbol description]
100：Gradual approaching analog-digital converter
110：First capacitor array
112：First specified capacitance
114：First sampling capacitor
120：Comparator
122：First input end
124：Second input terminal
130：First switch circuit
132：First input switch
134：First sampling controlling switch
140：Control circuit
150：Second capacitor array
152：Second specified capacitance
154：Second sampling capacitor
160：Second switch circuit
400：Decoder
410：Wave filter
420：Analog-digital converter
S1：First input signal
S2：Second input signal
Sin：Original signal
Fin：Filtering signal
Ref1：First reference signal
Ref2：Second reference signal
V1：First voltage
V2：Second voltage
Comp：Comparative result
Ctrl_1：First control signal
Ctrl_2：Second control signal
Dout：Digital output signal, decoded signal
C1：First capacitance
C2：Second capacitance
S310：Under a sampling mode, one first input signal is sampled using one first capacitor array, wherein the first capacitance
Array includes at least one first specified capacitance and at least one first sampling capacitor
S320：Under a comparison pattern, compare a first voltage and a second voltage from the first capacitor array, thereby
A comparative result is produced, wherein second voltage is related to one second input signal
S330：A first switch circuit is controlled to make first to specify electricity via a first control signal under foregoing sampling mode
Appearance does not sample the first input signal, while the first sampling capacitor is sampled the first input signal, thereby determines the first capacitor array
Stored charge amount
S340：Stop the first capacitor array via first control signal control first switch circuit under foregoing comparison pattern
Only sample, and the first specified capacitance and the first sampling capacitor is shared electric charge, thereby determine that the first capacitor array exported the
One voltage
S350：The first control signal is produced according to a sampling setting under the sampling mode, and in the comparison pattern
It is lower to produce the first control signal according to foregoing comparative result
S30：Receive one first input signal
S32：First input signal is sampled using one first capacitor array, to produce multiple first original samples values
S34：Produced according to the plurality of first original samples value and multiple second original samples values or a reference value multiple
Comparative result
S36：Judge whether the change of the plurality of comparative result meets a preset style.
S38：If the change of the plurality of comparative result meets the preset style, first capacitor array is adjusted, and again
First input signal is sampled by first capacitor array, to produce multiple first adjustment sampling values, wherein the plurality of first
The maximum for adjusting sampling value is less than the maximum of the plurality of first original samples value.
Claims (17)
1. a kind of gradually approaching analog-digital converter, can determine the sampling value of an input signal, comprising：
One first capacitor array, comprising multiple first capacitances, for sampling one first input signal under a sampling mode, wherein
The multiple first capacitance includes at least one first specified capacitance and at least one first sampling capacitor, and the multiple first capacitance
In each comprising one first power on extremely with one first bottom electrode end；
One comparator, for comparing the first voltage from first capacitor array and one second electricity under a comparison pattern
Pressure, to produce a comparative result；
One first switch circuit, couples first capacitor array, for believing under the sampling mode according to one first control
Number determine the first capacitor array stored charge amount,
And under the comparison pattern determine that first capacitor array exported according to the first control signal described the
One voltage；And
One control circuit, couples the comparator and the first switch circuit, for being taken under the sampling mode according to one
Sample setting produces the first control signal, and produces first control according to the comparative result under the comparison pattern
Signal,
Wherein described first control signal makes described at least one first under the sampling mode via the first switch circuit
Specified capacitance does not sample first input signal, while makes at least one first sampling capacitor sampling the first input letter
Number, and first capacitor array is stopped sampling via the first switch circuit under the comparison pattern, and make institute
State at least one first specified capacitance and share electric charge with least one first sampling capacitor.
2. converter according to claim 1, wherein the first switch circuit includes one first input switch and one the
One sampling controlling switch, and under the sampling mode, the first control signal couples institute via first input switch
State the first of at least one first specified capacitance and power on extreme and first input signal, via the described first sampling controlling switch
First bottom electrode end of at least one first specified capacitance described in coupling and first input signal, and opened via described first
At least one first sampling capacitor is coupled between first input signal and one first reference signal by powered-down road；Institute
State under comparison pattern, the first control signal is via at least one first specified capacitance described in first input switch disconnection
First powers on extreme and first input signal, is specified via described in the described first sampling controlling switch coupling at least one first
First bottom electrode end of capacitance and first reference signal, and via at least one first specified capacitance with it is described at least
The first of one first sampling capacitor powers on extreme connection and is shared to reach electric charge.
3. converter according to claim 1, further includes：
One second capacitor array, comprising multiple second capacitances, for sampling one second input signal, and exports second electricity
Pressure, wherein the multiple second capacitance includes at least one second specified capacitance and at least one second sampling capacitor, and the multiple
In second capacitance each comprising one second power on extremely with one second bottom electrode end；And
One second switch circuit, couples second capacitor array, for believing under the sampling mode according to one second control
Number determine the second capacitor array stored charge amount,
And under the comparison pattern determine that second capacitor array exported according to the second control signal described the
Two voltages, wherein the control circuit produces the second control signal under the sampling mode according to the sampling setting,
And the second control signal is produced according to the comparative result under the comparison pattern,
Wherein described second control signal makes described at least one second under the sampling mode via the second switch circuit
Specified capacitance does not sample second input signal, while makes at least one second sampling capacitor sampling the second input letter
Number, and second capacitor array is stopped sampling via the second switch circuit under the comparison pattern, and make institute
State at least one second specified capacitance and share electric charge with least one second sampling capacitor.
4. converter according to claim 3, wherein the second switch circuit includes one second input switch and one the
Two sampling controlling switches, and under the sampling mode, the second control signal is coupled via second input switch
At least one second specified capacitance powers on extreme and second input signal, via the described second sampling controlling switch coupling
At least bottom electrode end of one first specified capacitance and second input signal are connect, and via the second switch circuit
At least one second sampling capacitor is coupled between second input signal and one second reference signal；In the comparison
Under pattern, the second control signal via second input switch disconnect described at least one second specified capacitance second on
Electrode tip and second input signal, via at least one second specified capacitance described in the described second sampling controlling switch coupling
Second bottom electrode end and second reference signal, and via at least one second specified capacitance and described at least one second
The second of sampling capacitor powers on extreme connection and is shared to complete electric charge.
5. converter according to claim 3, wherein at least one first specified capacitance refers to described at least one second
Determine that the capacitance of capacitance is equal, the capacitance phase of at least one first sampling capacitor and at least one second sampling capacitor
Deng.
6. converter according to claim 3, wherein second input signal is the anti-phase of first input signal
Signal.
7. converter according to claim 3, wherein second input signal is a predetermined reference signal.
8. converter according to claim 1, wherein the control circuit had previously compared according to the sampling setting or one
As a result analysis, selected by the first switch circuit from the multiple first capacitance at least one be used as it is described to
Few one first specified capacitance.
9. a kind of gradually approaching D conversion method, is performed by a gradual approaching analog-digital converter, described gradually to become
Nearly formula analog-digital converter can determine the sampling value of an input signal, and the method includes：
Under a sampling mode, one first input signal is sampled using one first capacitor array,
Wherein described first capacitor array includes at least one first specified capacitance and at least one first sampling capacitor；
Under a comparison pattern, compare a first voltage and a second voltage from first capacitor array, to produce one
Comparative result, wherein the second voltage is related to one second input signal, and second input signal is described first defeated
Enter the inversion signal or a predetermined reference signal of signal；
A first switch circuit is controlled to make described at least one first to specify via a first control signal under the sampling mode
Capacitance does not sample first input signal, while at least one first sampling capacitor is sampled first input signal,
To determine the first capacitor array stored charge amount；
The first switch circuit is controlled to make the first capacitance battle array via the first control signal under the comparison pattern
Row stop sampling, and at least one first specified capacitance is shared electric charge with least one first sampling capacitor, to determine
The first voltage that first capacitor array is exported；And
Produce the first control signal according to a sampling setting under the sampling mode, and under the comparison pattern according to
The first control signal is produced according to the comparative result.
10. conversion method according to claim 9, wherein making at least one first specified capacitance not sample described first
The step of input signal, includes：
Under the sampling mode, the first switch circuit is controlled to make described at least one first via the first control signal
Two electrode tips of specified capacitance couple first input signal, while are coupled at least one first sampling capacitor
Between first input signal and one first reference signal,
And at least one first specified capacitance is set to be included with described the step of at least one first sampling capacitor shares electric charge：
Under the comparison pattern, the first switch circuit is controlled to make described at least one first via the first control signal
Specified capacitance is coupled between first reference signal and at least one first sampling capacitor to share electric charge.
11. conversion method according to claim 9, wherein when second input signal is first input signal
During inversion signal, the conversion method further includes：
Second input signal is sampled using one second capacitor array, wherein second capacitor array includes at least one second
Specified capacitance and at least one second sampling capacitor；
A second switch circuit is controlled to make described at least one second to specify via a second control signal under the sampling mode
Capacitance does not sample second input signal, while at least one second sampling capacitor is sampled second input signal,
To determine the second capacitor array stored charge amount；
The second switch circuit is controlled to make the second capacitance battle array via the second control signal under the comparison pattern
Row stop sampling, and at least one second specified capacitance is shared electric charge with least one second sampling capacitor, to determine
The second voltage that second capacitor array is exported；And
The second control signal is produced according to the sampling setting under the sampling mode, and under the comparison pattern
The second control signal is produced according to the comparative result.
12. conversion method according to claim 11, wherein making at least one second specified capacitance not sample described the
The step of two input signals, includes：
Under the sampling mode, the second switch circuit is controlled to make described at least one second via the second control signal
Two electrode tips of specified capacitance couple second input signal, while are coupled at least one second sampling capacitor
Between second input signal and one second reference signal,
And at least one second specified capacitance is set to be included with described the step of at least one second sampling capacitor shares electric charge：
Under the comparison pattern, the second switch circuit is controlled to make described at least one second via the second control signal
Specified capacitance is coupled between second reference signal and at least one second sampling capacitor to share electric charge.
13. conversion method according to claim 9, further includes：
According to the sampling setting or the analysis of a previous comparative result, by the first switch circuit from first capacitance
The combination of a capacitance or multiple capacitances at least one first specified capacitance as described in is selected in array.
14. a kind of gradually approaching D conversion method, is to be performed by a gradual approaching analog-digital converter, can reduce and take
One input signal of sample, comprising：
Receive one first input signal；
First input signal is sampled using one first capacitor array, to produce multiple first original samples values；
Multiple relatively knots are produced according to the multiple first original samples value and multiple second original samples values or a reference value
Fruit；
Judge whether the change of the multiple comparative result meets a preset style；And
If the change of the multiple comparative result meets described the preset style, first capacitor array is adjusted, and pass through again
First capacitor array samples first input signal,
To produce multiple first adjustment sampling values,
The maximum of wherein the multiple first adjustment sampling value is less than the maximum of the multiple first original samples value.
15. conversion method according to claim 14, wherein first capacitor array, which includes at least one first, specifies electricity
Appearance and at least one first sampling capacitor, and the step of adjustment first capacitor array includes：
Make two electrode tip equipotentials of at least one first specified capacitance and cannot be sampled, and make described at least 1 the
Two electrode tips of one sampling capacitor are respectively coupled to first input signal and one first reference signal and can be to described the
One input signal is sampled.
16. conversion method according to claim 15, wherein at least capacitance of one first specified capacitance with it is described
At least summation of the capacitance of one first sampling capacitor is a total capacitance value, the maximum of the multiple first original samples value with
The ratio of the maximum of the multiple first adjustment sampling value depends on the total capacitance value and described at least one first sampling electricity
The ratio of the capacitance of appearance.
17. conversion method according to claim 14, wherein described the preset style refers to that the multiple comparative result is homogeneous
Together.
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| CN1732624A (en) * | 2002-12-27 | 2006-02-08 | 模拟装置公司 | Programmable input range SAR ADC |
| CN103036570A (en) * | 2011-10-10 | 2013-04-10 | 台湾积体电路制造股份有限公司 | Method and apparatus for programmable gain control useful with digital to analog converter |
| TW201332300A (en) * | 2012-01-17 | 2013-08-01 | Univ Nat Chiao Tung | Successive approximation analog-to-digital converter |
| CN103580692A (en) * | 2012-08-06 | 2014-02-12 | 瑞昱半导体股份有限公司 | Continuous Progressive Analog-to-Digital Converter and Analog-to-Digital Conversion Method |
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| CN1732624A (en) * | 2002-12-27 | 2006-02-08 | 模拟装置公司 | Programmable input range SAR ADC |
| CN103036570A (en) * | 2011-10-10 | 2013-04-10 | 台湾积体电路制造股份有限公司 | Method and apparatus for programmable gain control useful with digital to analog converter |
| TW201332300A (en) * | 2012-01-17 | 2013-08-01 | Univ Nat Chiao Tung | Successive approximation analog-to-digital converter |
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