CN104852731B - Half rate clock pulse and data recovery circuit - Google Patents
Half rate clock pulse and data recovery circuit Download PDFInfo
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- CN104852731B CN104852731B CN201410050526.0A CN201410050526A CN104852731B CN 104852731 B CN104852731 B CN 104852731B CN 201410050526 A CN201410050526 A CN 201410050526A CN 104852731 B CN104852731 B CN 104852731B
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Abstract
The present invention is, about a kind of half rate clock pulse and data recovery circuit, to include first and second gate-type voltage controlled oscillator, and first and second frequency detector.First frequency detector according to reference signal and the second frequency elimination clock pulses to produce the first output current, and second frequency detector according to the first frequency elimination clock pulses and the second frequency elimination clock pulses to produce the second output current.Loop filter changes the first or second output current into the first output voltage to control second clock pulse, and according to the first control voltage to produce the second control voltage, to control the first clock pulses.Lock detector and receive reference signal and the second frequency elimination clock pulses, so as to producing locking signal.Tool area efficiency proposed by the present invention and the half rate clock pulse of power efficiency and data recovery circuit, will not change it with enhanced shake tolerance and shake transfer function, be very suitable for practicality again.
Description
Technical field
The present invention is relevant clock pulses and data recovery（clock and data recovery,CDR）, particularly close
In a kind of half rate（half-rate）Clock pulses and data recovery circuit.
Background technology
Clock pulses is line communication system with data recovery circuit（Such as optical fiber or serial-connection system）Receiver weight
Want component.Shake tolerance（jitter tolerance）With shake transfer function（jitter transfer function）It is
Two important parameters of clock pulses and data recovery circuit.Shake tolerance, which is defined as sinusoidal jitter signal, will not increase position
Error rate（BER）On the premise of peak swing.Shake transfer function is defined as the corresponding output jitter signal of various speed institutes
Divided by input jiffer signal.In order to strengthen the shake tolerance of clock pulses and data recovery circuit, usually increase loop band
It is wide.The shake transfer function however, the increase of loop bandwidth can then degenerate.Therefore, conventional clock pulse is needed with data recovery circuit
One is obtained between the two in shake tolerance with shake transfer function to trade off.
The defect existed in view of above-mentioned existing clock pulses and data recovery circuit, the present inventor is based on being engaged in such
Product design manufacture abundant for many years practical experience and professional knowledge, and coordinate the utilization of scientific principle, actively it is subject to research and innovation, with
Phase founds a kind of novel clock pulses and data recovery circuit, and shake will not be sacrificed again by making it have enhanced shake tolerance
Transfer function, more practicality.By constantly research, design, and after studying sample repeatedly and improving, create finally
The present invention having practical value.
The content of the invention
It is a primary object of the present invention to, the defect for overcoming existing clock pulses to exist with data recovery circuit, and carry
Go out a kind of new tool area efficiency and the half rate clock pulse of power efficiency and data recovery circuit, technology to be solved is asked
Topic is to make it have enhanced shake tolerance to change its shake transfer function again, is very suitable for practicality.
The object of the invention to solve the technical problems is realized using following technical scheme.According to present invention proposition
Half rate clock pulse and data recovery circuit, include the first gate-type voltage controlled oscillator（first gated voltage-
controlled oscillator）（GVCO1）, the second gate-type voltage controlled oscillator（GVCO2）, first frequency detector, second frequency
Rate detector, loop filter and locking detector.First gate-type voltage controlled oscillator produces the first clock pulses, its frequency of oscillation
For the half of input data；And second gate-type voltage controlled oscillator produce second clock pulse, its frequency of oscillation is input data
Half.First frequency detector receives reference signal and leads the second frequency elimination clock pulses from second clock pulse, and according to ginseng
The difference on the frequency of signal and the second frequency elimination clock pulses is examined to produce the first output current.Second frequency detector receives the second frequency elimination
Clock pulses and the first frequency elimination clock pulses from the first clock pulses is led, and according to the first frequency elimination clock pulses and the second frequency elimination
The difference on the frequency of clock pulses is to produce the second output current.Loop filter changes the first output current or the second output current is
First output voltage, is fed to the second gate-type voltage controlled oscillator to control the frequency of oscillation of second clock pulse, and loop filter
According to the first control voltage to produce the second control voltage, it is fed to the first gate-type voltage controlled oscillator to control the first clock pulses
Frequency of oscillation.Lock detector and receive reference signal and the second frequency elimination clock pulses, so as to producing locking signal.
The object of the invention to solve the technical problems can be also applied to the following technical measures to achieve further.
Foregoing half rate clock pulse and data recovery circuit, it further includes the first frequency eliminator（frequency
divider）, it is by the frequency frequency elimination of first clock pulses to produce the first frequency elimination clock pulses.
Foregoing half rate clock pulse and data recovery circuit, it further includes the second frequency eliminator, and it is by the second clock
The frequency frequency elimination of pulse is to produce the second frequency elimination clock pulses.
Foregoing half rate clock pulse and data recovery circuit, wherein the first frequency detector are included：Phase frequency
Detector（phase frequency detector）（PFD）, it receives the reference signal and the second frequency elimination clock pulses, and
Output, difference on the frequency of its ratio between the reference signal and the second frequency elimination clock pulses are produced according to this；And charge pump
（charge pump）（CP）, the output of the phase frequency detector is converted to first output current by it.
Foregoing half rate clock pulse and data recovery circuit, wherein the second frequency detector are included：Phase frequency
Detector, it receives the first frequency elimination clock pulses and the second frequency elimination clock pulses, and produces output according to this, and its ratio is in this
Difference on the frequency between first frequency elimination clock pulses and the second frequency elimination clock pulses；And charge pump, it detects the phase frequency
The output of device is converted to second output current.
Foregoing half rate clock pulse and data recovery circuit, the wherein loop filter include low pass filter
（low-pass filter）, it is connected between first control voltage and ground, second control voltage is the low pass filter institute
The low pass output voltage of generation.
Foregoing half rate clock pulse and data recovery circuit, wherein the first or second gate-type voltage controlled oscillator bag
Contain：First annular oscillator（ring oscillator）, multiple multiplexers comprising concatenation（multiplexer）；Second annular
One of oscillator, multiple multiplexers comprising concatenation, the first annular oscillator and second ring oscillator basis
The logic level of input data and start；And buffering multiplexer, secondly individual input is respectively connecting to first or second annular and shaken
Swing two input nodes of second multiplexer of device, to produce this first or second clock pulse；Wherein this is first annular
Other multiplexers of oscillator in addition to first multiplexer are common to second ring oscillator except first multiplexer
Outside other multiplexers；And the output of wherein last multiplexer of first or second ring oscillator is inverted and returned
An input of first multiplexer is fed to, and the output of second multiplexer of first or second ring oscillator is fed back to
Another input of first multiplexer.
Foregoing half rate clock pulse and data recovery circuit, it further includes latch unit, its reception input data, and in
The rising edge of the second clock pulse samples input data with drop edge, thus produces reply data.
The D types of foregoing half rate clock pulse and data recovery circuit, the wherein latch unit comprising multiple concatenations are positive and negative
Device（flip-flop）（DFF）.
Foregoing half rate clock pulse and data recovery circuit, it further includes active inductive load（active
inductive load）, it includes the first branch and the second branch, the first ends of two branches be respectively connecting to this first or
The positive output and negative output of the multiplexer of second gate-type voltage controlled oscillator, the second end of two branches are connected to by current source
Ground.
Foregoing half rate clock pulse and data recovery circuit, wherein first branch or the second branch are included：N-type gold
Category oxidation semiconductor（NMOS）Transistor, its source electrode is connected to the current source, and drain electrode is connected to the positive output or negative of the multiplexer
Output；And resistor, it is connected to the N-type metal-oxide semiconductor（NMOS）Between the drain electrode of transistor and grid.
Foregoing half rate clock pulse and data recovery circuit, wherein when the reference signal and the second frequency elimination clock arteries and veins
The difference on the frequency of punching is in default lock-in range, and the locking signal opens the second frequency detector and closes the first frequency and detects
Survey device；Otherwise, the locking signal opens the first frequency detector and closes the second frequency detector.
By above-mentioned technical proposal, half rate clock pulse of the present invention and data recovery circuit at least have have the advantage that and
Beneficial effect：The present invention proposes a kind of half rate clock pulse of new tool area efficiency and power efficiency and data recovery electricity
Road, will not change it with enhanced shake tolerance and shake transfer function, be very suitable for practicality again.
Described above is only the general introduction of technical solution of the present invention, in order to better understand the technological means of the present invention,
And can be practiced according to the content of specification, and in order to allow the above and other objects, features and advantages of the present invention can
Become apparent, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, describe in detail as follows.
Brief description of the drawings
Fig. 1 shows half rate clock pulse and the data recovery of the embodiment of the present invention（CDR）The block diagram of circuit.
Fig. 2 shows the thin portion circuit diagram of Fig. 1 first/second gate-type voltage controlled oscillator.
Fig. 3 shows the circuit diagram of active inductive load, and it is applicable to Fig. 1 first/second gate-type voltage controlled oscillator.
Fig. 4 solid line represents Fig. 1 clock pulses and data recovery circuit in frequency preset（presetting）Pattern
Signal processing path and block.
Fig. 5 solid line represents Fig. 1 signal processing path of clock pulses and data recovery circuit in data recovery pattern
And block.
【Main element symbol description】
100:Clock pulses and data recovery circuit 11:First frequency detector
111:Phase frequency detector 112:Charge pump
12:Second frequency detector 121:Phase frequency detector
122:Charge pump 13:First gate-type voltage controlled oscillator
14:Second gate-type voltage controlled oscillator 15:First frequency eliminator
16:Second frequency eliminator 17:Loop filter
18:Lock detector 19:Latch unit
300:Active inductive load 31:Current source
Vc1:First control voltage Vc2:Second control voltage
R:Resistor C:Capacitor
Fref:Reference frequency Lock:Locking signal
Mux1~Mux8:Multiplexer Vc:Control voltage
CK:Clock pulses A:Node
B:Node R 1:Resistor
R2:Resistor M1:Nmos pass transistor
M2:Nmos pass transistor Voutn:Negative output
Voutp:Positive output
Embodiment
Further to illustrate the present invention to reach the technological means and effect that predetermined goal of the invention is taken, below in conjunction with
Accompanying drawing and preferred embodiment, to according to half rate clock pulse proposed by the present invention and its specific embodiment party of data recovery circuit
Formula, method, step, feature and its effect, are described in detail as after.
Fig. 1 shows half rate clock pulse and the data recovery of the embodiment of the present invention（CDR）The block diagram of circuit 100.
In the present embodiment, clock pulses mainly includes first frequency detector 11, second frequency detector with data recovery circuit 100
12nd, first（Half rate）Gate-type voltage controlled oscillator 13 and second（Half rate）Gate-type voltage controlled oscillator 14.First gate-type is voltage-controlled to shake
Swing the gate-type voltage controlled oscillator 14 of device 13 and second and produce the first clock pulses and second clock pulse respectively.Due to the first gate-type pressure
The frequency of oscillation of the gate-type voltage controlled oscillator 14 of controlled oscillator 13 and second is about the half of input data frequency, thus forms one
Plant half rate clock pulse and data recovery circuit.In one example, the speed of input data is 3.2Gb/s, and when first
Clock and the frequency of second clock pulse are 1.6Gb/s.
First frequency detector 11 receives reference signal（It has reference frequency Fref）With（Second）Frequency elimination clock pulses,
Wherein the second frequency elimination clock pulses be by second clock pulse by（Second）The frequency elimination of frequency eliminator 16（For example divided by 8）And obtain
Arrive.According to the difference on the frequency between reference signal and the second frequency elimination clock pulses, it is defeated that first frequency detector 11 thus produces first
Go out electric current, it is converted to by loop filter 17（First）Control voltage Vc1.First control voltage Vc1 is then fed to
Two gate-type voltage controlled oscillators 14, to control the frequency of oscillation of second clock pulse.
On the other hand, second frequency detector 12 receives the first frequency elimination clock pulses and the second frequency elimination clock pulses, wherein
The first frequency elimination clock pulses be by the first clock pulses by（First）The frequency elimination of frequency eliminator 15（For example divided by 8）And obtain.
According to the difference on the frequency between the first frequency elimination clock pulses and the second frequency elimination clock pulses, second frequency detector 12 thus produces the
Two output currents, it is converted to by loop filter 17（First）Control voltage Vc1.First control voltage Vc1 is then presented
To the second gate-type voltage controlled oscillator 14, to control the frequency of oscillation of second clock pulse.It is worth noting that, in any time,
It is running that first frequency detector 11 only has one with second frequency detector 12（And another is then closed or left unused）, therefore the
One frequency detector 11 is all denoted as the first control voltage Vc1 with the control voltage produced by second frequency detector 12.
The first frequency detector 11 of the present embodiment can include phase frequency detector（PFD1）111, it is received with reference to letter
Number with the second frequency elimination clock pulses, and according to this produce output, its ratio is between reference signal and the second frequency elimination clock pulses
Difference on the frequency.The first frequency detector 11 of the present embodiment can also include charge pump（CP1）112, it is by phase frequency detector 111
Output be converted to the first output current.Similar situation, second frequency detector 12 can include phase frequency detector
（PFD2）121, it receives first frequency elimination clock pulses and the second frequency elimination clock pulses, and produces output according to this, and its ratio is in the
Difference on the frequency between one frequency elimination clock pulses and the second frequency elimination clock pulses.Second frequency detector 12 can also include charge pump
（CP2）122, the output of phase frequency detector 121 is converted to the second output current by it.
In the present embodiment, loop filter 17 according to the first control voltage Vc1 to produce the second control voltage Vc2.The
Two control voltage Vc2 are then fed to the first gate-type voltage controlled oscillator 13, to control the frequency of oscillation of the first clock pulses.This implementation
The loop filter 17 of example includes low pass filter, its include be serially connected with resistor R between the first control voltage Vc1 and ground with
Capacitor C.Second control voltage Vc2 is the low pass output voltage produced by above-mentioned low pass filter.In stable state, the first control
Voltage Vc1 processed is approximately equal to the second control voltage Vc2.
Fig. 2 shows the thin portion circuit diagram of gate-type voltage controlled oscillator, and it is applicable to the first gate-type voltage controlled oscillator 13 or the
Two gate-type voltage controlled oscillators 14.In the drawings, Vc represents control voltage, and it can be（Second gate-type voltage controlled oscillator 14）Vc1
Or（First gate-type voltage controlled oscillator 13）Vc2；CK represents clock pulses, and it can be（First gate-type voltage controlled oscillator 13）The
One clock pulses or（Second gate-type voltage controlled oscillator 14）Second clock pulse.
Gate-type voltage controlled oscillator shown in Fig. 2 can include two quadravalence ring oscillators.When input data is logic high
On time, four multiplexer Mux1, Mux3, Mux4 and Mux5 the first quadravalence ring oscillators of composition, wherein multiplexer Mux1,
Mux3, Mux4 are concatenated with Mux5, and the 4th multiplexer Mux5 output is inverted and be fed back to the one of first multiplexer Mux1
Individual input, second multiplexer Mux3 output is fed back to first multiplexer Mux1 another input.First quadravalence annular
Each multiplexer of oscillator produces 45 ° of phase offsets, and node A and node B（That is, the two of second multiplexer Mux3
Individual input node）Between phase difference be 90 °.
On the other hand, when input data is logic low level, four multiplexer Mux2, Mux3, Mux4 and Mux5 compositions
Second quadravalence ring oscillator, wherein multiplexer Mux2, Mux3, Mux4 is concatenated with Mux5, the 4th multiplexer Mux5 output
A first multiplexer Mux2 input is inverted and is fed back to, second multiplexer Mux3 output is fed back to more than first
Work device Mux2 another input.Phase difference between node A and node B is also 90 °.It is worth noting that, the first quadravalence ring
The second of shape oscillator to second to the 4th multiplexer of the 4th multiplexer and the second quadravalence ring oscillator is shared.
Gate-type voltage controlled oscillator shown in Fig. 2 can also be comprising buffering multiplexer Mux6, secondly individual input is respectively connecting to section
Point A and node B, to produce output clock pulses CK.Gate-type voltage controlled oscillator shown in Fig. 2 can also include two void
（dummy）Multiplexer Mux7 and Mux8, the output loading to balance multiplexer Mux4 and Mux5 respectively.Control voltage Vc allows door
Formula voltage controlled oscillator is vibrated in required frequency.Above-mentioned gate-type voltage controlled oscillator input data transform strike slip boundary, by adjustment
Export clock pulses CK phase and be able to reach that fast phase is locked.
Refering to Fig. 1, the clock pulses and data recovery circuit 100 of the present embodiment can also include locking detector（LD）18,
It receives reference signal and the second frequency elimination clock pulses.When the difference on the frequency between reference signal and the second frequency elimination clock pulses between
The lock-in range of acquiescence, then lock detector 18 and produce locking signal（Lock）, to open second frequency detector 12（And
Close first frequency detector 11）；Otherwise, locking detector 18 produces locking signal（Lock）To open first frequency detector
11（And close second frequency detector 12）.
The clock pulses of the present embodiment can include latch unit 19 with data recovery circuit 100, receive input data, and the
The rising edge of two clock pulses samples input data with drop edge, thus produces reply data.In the present embodiment, breech lock
Device 19 can include the D-type flip-flop of multiple concatenations（DFF）.
One of feature according to the present embodiment, can be used active inductive load in first/second gate-type voltage controlled oscillator 13/
14, to reduce complexity and reach high oscillation frequency, and tool low power consumption.Fig. 3 shows the active sense of the embodiment of the present invention
300 circuit diagram should be loaded.In the present embodiment, active inductive load 300 includes two branches, that is, the first branch and second
Branch, its first end is respectively connecting to（Fig. 2's）The positive output and negative output of multiplexer.Second end of two branches is by electric current
Source 31 is connected to the ground.Each branch includes N-type metal-oxide semiconductor（NMOS）Transistor M1/M2, its source electrode is connected to electricity
Stream source 31, drain electrode is respectively connecting to the positive output and negative output of multiplexer.Each branch also includes resistor R1/R2, connection
In corresponding N-type metal-oxide semiconductor（NMOS）Between transistor M1/M2 drain electrode and grid.Active inductive load 300 can drop
Low main body effect（body effect）.When output voltage is minimum, due to N-type metal-oxide semiconductor（NMOS）Crystal
Pipe M1/M2 maintains saturation（saturation）Region, therefore output voltage swing（swing）It will not change.Whereby, actively sense negative
Frequency of oscillation can be lifted and reduce power consumption by carrying 300.
Above-mentioned clock pulses has two operator schemes with data recovery circuit 100：Frequency preset pattern and data recovery
Pattern.Fig. 4 solid line represents clock pulses and signal processing path and area of the data recovery circuit 100 in frequency preset pattern
Block, and Fig. 5 solid line represents clock pulses and signal processing path and area of the data recovery circuit 100 in data recovery pattern
Block.
Refering to Fig. 4, in frequency preset pattern, the phase frequency detector of first frequency detector 11（PFD1）111 monitorings
The difference on the frequency of reference signal and the second frequency elimination clock pulses.The charge pump of first frequency detector 11（CP1）112 turn difference on the frequency
The first output current is changed to, its ratio is in the difference on the frequency.Then, the first output current is converted to the first control by loop filter 17
Voltage Vc1 processed, it causes the first gate-type voltage controlled oscillator 13 and the second gate-type voltage controlled oscillator 14 to oscillate respectively at the half of acquiescence
The clock pulses of speed control one and second clock pulse.In stable state, the first control voltage Vc1 of loop filter 17 and second
Control voltage Vc2 is approximately equivalent.One of feature according to the present embodiment, the charge pump of second frequency detector 12（CP2）122 are
Close, to reduce power consumption.When locking detector 18 continues to monitor reference signal with the second frequency elimination during two patterns
Difference on the frequency between clock.When difference on the frequency is between acquiescence lock-in range, then the first gate-type voltage controlled oscillator 13 and the second gate-type
Voltage controlled oscillator 14 can be vibrated in target frequency, now complete frequency preset pattern.
Then, as shown in figure 5, in data recovery pattern, because the first control voltage Vc1 and the second control voltage Vc2 exists
The later stage of frequency preset pattern is up to equal, therefore the first gate-type voltage controlled oscillator 13 can shake with the second gate-type voltage controlled oscillator 14
Swing in target frequency.The phase of first clock pulses of the first gate-type voltage controlled oscillator 13 is to be decided by input data, and by
Adjustment input to the second gate-type voltage controlled oscillator 14 the first control voltage Vc1 so that the of the second gate-type voltage controlled oscillator 14
Two clock pulses pursue the first clock pulses to complete PGC demodulation.Removed when locking detector 18 detects reference signal with second
The difference on the frequency of frequency clock pulses is no longer in lock-in range, then operator scheme will switch to frequency preset pattern.
The above described is only a preferred embodiment of the present invention, any formal limitation not is made to the present invention, though
So the present invention is disclosed above with preferred embodiment, but is not limited to the present invention, any to be familiar with this professional technology people
Member, without departing from the scope of the present invention, when the technology contents using the disclosure above make a little change or modification
For the equivalent embodiment of equivalent variations, as long as being the technical spirit pair according to the present invention without departing from technical solution of the present invention content
Any simple modification, equivalent variations and modification that above example is made, in the range of still falling within technical solution of the present invention.
Claims (9)
1. a kind of half rate clock pulse and data recovery circuit, it is characterised in that it is included：
First gate-type voltage controlled oscillator, produces the first clock pulses, and its frequency of oscillation is the half of input data；
Second gate-type voltage controlled oscillator, produces second clock pulse, and its frequency of oscillation is the half of input data；
First frequency detector, receives reference signal and leads the second frequency elimination clock pulses from the second clock pulse, this first
Frequency detector is according to the difference on the frequency of the reference signal and the second frequency elimination clock pulses to produce the first output current；
Second frequency detector, receives the second frequency elimination clock pulses and leads the first frequency elimination clock arteries and veins from first clock pulses
Punching, the second frequency detector is according to the difference on the frequency of the first frequency elimination clock pulses and the second frequency elimination clock pulses to produce the
Two output currents；
Loop filter, changes first output current or second output current into the first control voltage, is fed to this second
Formula voltage controlled oscillator to control the frequency of oscillation of second clock pulse, and the loop filter according to first control voltage to produce
Raw second control voltage, is fed to the first gate-type voltage controlled oscillator to control the frequency of oscillation of the first clock pulses；And
Detector is locked, the reference signal and the second frequency elimination clock pulses is received, so as to producing locking signal；
Described half rate clock pulse has two operator schemes with data recovery circuit：Frequency preset pattern and data recovery
Pattern, the locking detector is continued to monitor during two patterns between the reference signal and the second frequency elimination clock pulses
Difference on the frequency, when the difference on the frequency is in default lock-in range, the locking signal opens the second frequency detector and close should
First frequency detector；Otherwise, the locking signal opens the first frequency detector and closes the second frequency detector.
2. half rate clock pulse according to claim 1 and data recovery circuit, it is characterised in that it further includes first
Frequency eliminator, it is by the frequency frequency elimination of first clock pulses to produce the first frequency elimination clock pulses.
3. half rate clock pulse according to claim 1 and data recovery circuit, it is characterised in that it further includes second
Frequency eliminator, it is by the frequency frequency elimination of the second clock pulse to produce the second frequency elimination clock pulses.
4. half rate clock pulse according to claim 1 and data recovery circuit, it is characterised in that wherein first frequency
Rate detector is included：
Phase frequency detector, it receives the reference signal and the second frequency elimination clock pulses, and produces output, its ratio according to this
Difference on the frequency between the reference signal and the second frequency elimination clock pulses；And
Charge pump, the output of the phase frequency detector is converted to first output current by it.
5. half rate clock pulse according to claim 1 and data recovery circuit, it is characterised in that wherein second frequency
Rate detector is included：
Phase frequency detector, it receives the first frequency elimination clock pulses and the second frequency elimination clock pulses, and produces according to this defeated
Go out, difference on the frequency of its ratio between the first frequency elimination clock pulses and the second frequency elimination clock pulses；And
Charge pump, the output of the phase frequency detector is converted to second output current by it.
6. half rate clock pulse according to claim 1 and data recovery circuit, it is characterised in that wherein the loop is filtered
Ripple device includes low pass filter, is connected between first control voltage and ground, and second control voltage is the low pass filter
Produced low pass output voltage.
7. half rate clock pulse according to claim 1 and data recovery circuit, it is characterised in that wherein this first or
Second gate-type voltage controlled oscillator is included：
First annular oscillator, multiple multiplexers comprising concatenation；
Second ring oscillator, multiple multiplexers comprising concatenation, the first annular oscillator and second ring oscillator
One of them starts according to the logic level of input data；And
Multiplexer is buffered, secondly individual input second multiplexer for being respectively connecting to first or second ring oscillator two
Input node, to produce this first or second clock pulse；
Wherein other multiplexers of the first annular oscillator in addition to first multiplexer are common to second ring oscillation
Other multiplexers of device in addition to first multiplexer；And
The output of wherein last multiplexer of first or second ring oscillator is inverted and is fed back to first multiplexing
One of device input, and the output of second multiplexer of first or second ring oscillator is fed back to first multiplexer
Another input.
8. half rate clock pulse according to claim 1 and data recovery circuit, it is characterised in that it further includes breech lock
Device, it receives input data, and samples input data in the rising edge of the second clock pulse and drop edge, thus produces
Reply data.
9. half rate clock pulse according to claim 8 and data recovery circuit, it is characterised in that the wherein latch unit
Include the D-type flip-flop of multiple concatenations.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410050526.0A CN104852731B (en) | 2014-02-13 | 2014-02-13 | Half rate clock pulse and data recovery circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410050526.0A CN104852731B (en) | 2014-02-13 | 2014-02-13 | Half rate clock pulse and data recovery circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104852731A CN104852731A (en) | 2015-08-19 |
| CN104852731B true CN104852731B (en) | 2017-10-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410050526.0A Active CN104852731B (en) | 2014-02-13 | 2014-02-13 | Half rate clock pulse and data recovery circuit |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1398879A1 (en) * | 2002-09-12 | 2004-03-17 | Fujitsu Limited | PLL clock generator circuit and clock generation method |
| CN102064825A (en) * | 2010-12-15 | 2011-05-18 | 硅谷数模半导体（北京）有限公司 | Clock and data recovery circuit and integrated chip with same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8228126B2 (en) * | 2007-04-19 | 2012-07-24 | Mediatek Inc. | Multi-band burst-mode clock and data recovery circuit |
-
2014
- 2014-02-13 CN CN201410050526.0A patent/CN104852731B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1398879A1 (en) * | 2002-09-12 | 2004-03-17 | Fujitsu Limited | PLL clock generator circuit and clock generation method |
| CN102064825A (en) * | 2010-12-15 | 2011-05-18 | 硅谷数模半导体（北京）有限公司 | Clock and data recovery circuit and integrated chip with same |
Non-Patent Citations (2)
| Title |
|---|
| 10-Gb/s Inductorless CDRs With Digital Frequency Calibration;Che-Fu Liang 等;《IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS》;20081031;第55卷(第9期);2514-2524页 * |
| 2.5Gbps时钟数据恢复电路的设计;杨宗雄;《中国优秀硕士学位论文全文数据库 信息科技辑》;20130115(第1期);I135-212页，12-15页 * |
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| CN104852731A (en) | 2015-08-19 |
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