CN104835815A - 复合电路元件的布局 - Google Patents
复合电路元件的布局 Download PDFInfo
- Publication number
- CN104835815A CN104835815A CN201510062364.7A CN201510062364A CN104835815A CN 104835815 A CN104835815 A CN 104835815A CN 201510062364 A CN201510062364 A CN 201510062364A CN 104835815 A CN104835815 A CN 104835815A
- Authority
- CN
- China
- Prior art keywords
- transistor
- group
- circuit
- area
- circuit element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
Claims (25)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201461937094P | 2014-02-07 | 2014-02-07 | |
US61/937,094 | 2014-02-07 | ||
US14/271,044 | 2014-05-06 | ||
US14/271,044 US9299692B2 (en) | 2014-02-07 | 2014-05-06 | Layout of composite circuit elements |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104835815A true CN104835815A (zh) | 2015-08-12 |
CN104835815B CN104835815B (zh) | 2019-04-16 |
Family
ID=53775611
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510062364.7A Active CN104835815B (zh) | 2014-02-07 | 2015-02-06 | 复合电路元件的布局 |
Country Status (2)
Country | Link |
---|---|
US (1) | US9299692B2 (zh) |
CN (1) | CN104835815B (zh) |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6500764B1 (en) * | 2001-10-29 | 2002-12-31 | Fairchild Semiconductor Corporation | Method for thinning a semiconductor substrate |
KR100665850B1 (ko) * | 2005-07-22 | 2007-01-09 | 삼성전자주식회사 | 고집적 반도체 메모리 소자용 모오스 트랜지스터들의배치구조 및 그에 따른 배치방법 |
CN1906755A (zh) * | 2004-04-30 | 2007-01-31 | 松下电器产业株式会社 | 半导体制造方法及半导体装置 |
WO2009037808A1 (ja) * | 2007-09-18 | 2009-03-26 | Panasonic Corporation | 半導体集積回路 |
CN101533843A (zh) * | 2008-03-12 | 2009-09-16 | 索尼株式会社 | 半导体装置 |
US7772920B1 (en) * | 2009-05-29 | 2010-08-10 | Linear Technology Corporation | Low thermal hysteresis bandgap voltage reference |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7118273B1 (en) | 2003-04-10 | 2006-10-10 | Transmeta Corporation | System for on-chip temperature measurement in integrated circuits |
US6858917B1 (en) * | 2003-12-05 | 2005-02-22 | National Semiconductor Corporation | Metal oxide semiconductor (MOS) bandgap voltage reference circuit |
JP2007173463A (ja) | 2005-12-21 | 2007-07-05 | Ricoh Co Ltd | 基準電圧発生回路 |
EP2308096A1 (en) * | 2008-07-28 | 2011-04-13 | Nxp B.V. | Integrated circuit and method for manufacturing an integrated circuit |
US9030000B2 (en) * | 2013-06-14 | 2015-05-12 | Freescale Semiconductor, Inc. | Mold cap for semiconductor device |
-
2014
- 2014-05-06 US US14/271,044 patent/US9299692B2/en active Active
-
2015
- 2015-02-06 CN CN201510062364.7A patent/CN104835815B/zh active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6500764B1 (en) * | 2001-10-29 | 2002-12-31 | Fairchild Semiconductor Corporation | Method for thinning a semiconductor substrate |
CN1906755A (zh) * | 2004-04-30 | 2007-01-31 | 松下电器产业株式会社 | 半导体制造方法及半导体装置 |
KR100665850B1 (ko) * | 2005-07-22 | 2007-01-09 | 삼성전자주식회사 | 고집적 반도체 메모리 소자용 모오스 트랜지스터들의배치구조 및 그에 따른 배치방법 |
WO2009037808A1 (ja) * | 2007-09-18 | 2009-03-26 | Panasonic Corporation | 半導体集積回路 |
CN101533843A (zh) * | 2008-03-12 | 2009-09-16 | 索尼株式会社 | 半导体装置 |
US7772920B1 (en) * | 2009-05-29 | 2010-08-10 | Linear Technology Corporation | Low thermal hysteresis bandgap voltage reference |
Also Published As
Publication number | Publication date |
---|---|
US20150228636A1 (en) | 2015-08-13 |
CN104835815B (zh) | 2019-04-16 |
US9299692B2 (en) | 2016-03-29 |
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GR01 | Patent grant | ||
GR01 | Patent grant | ||
CP01 | Change in the name or title of a patent holder |
Address after: Limerick Patentee after: Analog Devices Global Unlimited Co. Address before: Limerick Patentee before: Analog Devices Global |
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CP01 | Change in the name or title of a patent holder | ||
CP02 | Change in the address of a patent holder |
Address after: Limerick Patentee after: Analog Devices Global Address before: Bermuda (UK) Hamilton Patentee before: Analog Devices Global |
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CP02 | Change in the address of a patent holder | ||
TR01 | Transfer of patent right |
Effective date of registration: 20210629 Address after: Limerick Patentee after: ANALOG DEVICES INTERNATIONAL UNLIMITED Co. Address before: Limerick Patentee before: Analog Devices Global Unlimited Co. |
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TR01 | Transfer of patent right |