CN104821871A - 16 quadrature amplitude modulation (QAM) demodulation synchronization method - Google Patents

Abstract

The invention provides a 16 quadrature amplitude modulation (QAM) demodulation synchronization method. The method comprises a first step of adding a power detection technology on a traditional costas loop of quadrature phase shift keying (QPSK) so as to finish carrier recovery; a second step of performing matched filtering on each same-phase orthogonal component signal, so as to reduce noise effect and prepare for bit synchronization; a third step of performing bit timing recovery on same-phase orthogonal signals through an "early-late gate"; a fourth step of setting a threshold, and performing sampling judgment and 4-2 level conversion on each of two paths of signal to obtain parallel signals; and a fifth step of performing differential decoding and parallel-serial conversion on the parallel signals, then recovering and obtaining original signals. According to the introduced novel carrier synchronization technology, the carrier recovery is finished by using a phase-locked loop; on the basis of the traditional costas loop, the power detection technology is added, so that the linear output of a phase discriminator is guaranteed, the tracking precision and speed are improved, and the novel carrier synchronization technology passes field programmable gate array (FPGA) hardware verification.

Description

A kind of 16QAM demodulation synchronous method

Technical field

The present invention relates to the communications field, specifically a kind of 16QAM demodulation synchronous method.

Background technology

In multi-system keying system, the bandwidth sum power of phase keying takies aspect and all has superiority, and namely bandwidth occupancy is little, and bit signal to noise ratio requires low.MPSK (Multiple Phase Shift Keying), MDPSK (MultipleDifferential Phase Shift Keying) have permanent envelope, feature that power efficiency is high, but secondary lobe is higher, spectrum leakage is larger, easy generation spread spectrum, and along with the increase of M, the distance of adjacent phase reduces gradually, noise margin reduces thereupon, and the error rate is difficult to ensure.Quadrature amplitude modulation (QAM, Quadrature Amplitude Modulation) is a kind of modulation technique two enterprising line amplitude modulation of quadrature carrier that modern communications often adopts, and which improves the noise margin of MPSK when M is large.16QAM is the representative signal of QAM modulation, it has the advantage that the error rate is low, transmission rate is high and band efficiency is high, can be applicable in the communication fields such as HSDPA (High Speed Downlink Packet Access), satellite communication and broadband wireless access.But because 16QAM is non-constant envelope signal, if adopt the Costas loop of traditional Q PSK in carrier auxiliary process, easily cause the defects such as precision is low, tracking velocity is slow.In addition, the FPGA tool software being core with DSP Builder exploitation QAM modulation demodulator, though simple, its stability, portability are poor, and application limitation is large.Because 16QAM exists 90 ° of phase fuzzy problem, if the carrier wave when carrier wave produced during carrier auxiliary and modulation is non-with frequency homophase, then decoding error can be produced.

This patent adopts quadrature amplitude modulation method to carry out 16QAM modulation, and carries out differential coding to baseband signal before modulation, at the laggard row differential decoding of bit synchronization, can overcome the impact of phase ambiguity.In carrier synchronization module, this patent, on the COSTAS loop basis of traditional Q PSK, increases power detection judgement, to overcome the non-permanent envelope of 16QAM to the impact of phase discriminator.Timing recovery module in place, certain phase deviation and clock skew can be there is thus cause error code in the clock due to transmitter and receiver, therefore the present invention adopts based on the self synchronous algorithm of door sooner or later, be applicable to the system of high power sample rate, can "ball-park" estimate clock skew, simple for structure, be easy to FPGA hardware implementing.Through making rational planning for, well-designed, the complete 16QAM modulation demodulation system comprising this new demodulation simultaneous techniques is achieved in the large-scale F PGA chip of monolithic ALTERA company, and on development board, carried out detailed testing authentication.

Summary of the invention

The present invention, in order to solve the problem of prior art, the COSTAS loop basis of traditional Q PSK is improved, and provides a kind of 16QAM demodulation synchronous method, overcomes the non-permanent envelope of 16QAM to the impact of phase discriminator, improves systematic function.

The invention provides a kind of 16QAM demodulation synchronous method, comprise the following steps:

1) carrier synchronization: suppose that n reception is to signal y (n), obtains signal q (n) after demodulation, τ is power detection thresholding, when | q (n) | ²during < τ, phase discriminator exports is 0, | q (n) | ²during > τ, phase discriminator exports phase error e (n) of this time-ofday signals point, and phase error control NCO after loop filter is level and smooth eliminates frequency deviation, skew gradually, reaches carrier synchronization; Choose suitable power detection thresholding τ, the phase error detection planisphere of 16QAM is converted to the planisphere of QPSK, then adopt COSTAS loop to carry out demodulation; 16QAM is after power detection judgement, the a (k), the b (k) that enter phase discriminator calculating only have a kind of amplitude, therefore | a (k) |+| b (k) | be constant, error amount control NCO after loop filter is level and smooth eliminates frequency deviation residual error and phase error gradually, reaches carrier synchronization.

2) respectively matched filtering is carried out to inphase quadrature component signal;

3) because the clock of transmitter and receiver can exist certain phase deviation and clock skew, along with the accumulation gradually of skew then can cause error code, systematic function is had a strong impact on.The present invention adopts based on the algorithm of door sooner or later of self-synchronizing method, is applicable to the system of high power sample rate, can "ball-park" estimate clock skew, is simple for structurely easy to hardware implementing.By " sooner or later door ", bit timing recovery is carried out to inphase quadrature signal, makes τ=T/2, the model of Timing Error Detector can be derived:

$\begin{array}{c}e\left(n\right)=u_I(n+\mathrm{\&tau;}\left(n\right))[u_I(n+\frac{1}{2}+\mathrm{\&tau;}\left(n\right))-u_I(n-\frac{1}{2}+\mathrm{\&tau;}(n-1))]\\ +u_Q(n+\mathrm{\&tau;}\left(n\right))[u_Q(n+\frac{1}{2}+\mathrm{\&tau;}\left(n\right))-u_Q(n-\frac{1}{2}+\mathrm{\&tau;}(n-1))]\end{array}$

In formula, τ (n) is the sampling clock compensated, represent the transition value of the (n+1)th and n-th code element, represent the transition value of n-th and (n-1)th code element.Can obtain NCO output by formula (6) is:

τ(n+1)＝τ(n)+γ·e(n)；

4) arrange thresholding to two paths of signals carry out respectively sampling judgement and 4-2 level conversion obtain parallel signal;

5), after differential decoding and parallel-serial conversion being carried out to parallel signal, primary signal is recovered.

Step 1) in phase error e (n) derive as follows, if Received signal strength r (k) is:

r(k)＝a(k)cos[(ω _c±ω _d)kT _s+θ]-b(k)sin[(ω _c±ω _d)kT _s+θ]+n(t),

ω in formula _dfor Doppler frequency shift, θ is carrier phase, and n (t) is receiving terminal Gaussian noise, the homophase that a (k), b (k) are base band symbol and quadrature component, T _sfor the sampling period; Signal obtains after quadrature downconvert, low-pass filtering removing high fdrequency component:

U _I(k)＝a(k)cos[(ω _c±ω _d-ω _o)kT _s+θ-θ _o]-b(k)sin[(ω _c±ω _d-ω _o)kT _s+θ-θ _o],

U _Q(k)＝b(k)cos[(ω _c±ω _d-ω _o)kT _s+θ-θ _o]+a(k)sin[(ω _c±ω _d-ω _o)kT _s+θ-θ _o],

Power detection value P (k) is:

P(k) _＝(U _I(k)) ²+(U _Q(k)) ²

As P (k) < τ, phase detector error e (k)=0; As P (k) > τ, make Δ φ=(ω _c± ω _d-ω _o) k _st+ θ- _oθ, by U _i, U _qsend into phase discriminator, phase discriminator is based on hard decision algorithm herein, when time very little, can phase detector error e (k) be obtained:

Beneficial effect of the present invention is:

1, introduce Novel carrier wave simultaneous techniques, utilize phase-locked loop to complete carrier auxiliary, and on the basis of traditional Costas loop, increase power detection techniques, ensure the linear convergent rate of phase discriminator, improve tracking accuracy and speed.

2, the algorithm of door sooner or later that carrier synchronization adopts is easy to FPGA and realizes.

3, overcome the harmful effect of 16QAM to phase discriminator in demodulation is synchronous, significantly improve systematic function.

Accompanying drawing explanation

Fig. 1 is 16QAM signal constellation and mapping.

Fig. 2 is that 16QAM modulation FPGA realizes block diagram.

Fig. 3 is 16QAM power spectrum chart.

Fig. 4 is that 16QAM demodulation FPGA realizes block diagram.

Fig. 5 is carrier synchronization ring theory diagram.

Fig. 6 is Timing Synchronization ring theory diagram.

Fig. 7 (a) is rectangular pulse signal schematic diagram.

Fig. 7 (b) is that door algorithm utilizes the symmetry of signal after matched filter to carry out the synchronous matched filtering output schematic diagram of bit timing sooner or later.

Fig. 8 is total system FPGA schematic diagram.

Fig. 9 is the modulation signal of transmitting terminal after differential coding.

Figure 10 (a) is Matlab reading FPGA output waveform data figure

The planisphere that Figure 10 (b) calculates for Matlab reading FPGA output waveform.

Figure 11 be carrier wave without frequency deviation, the FPGA test result of carrier auxiliary during phase deviation 22.5 °.

Figure 12 is carrier wave frequency deviation 3KHz, without the FPGA test result of carrier auxiliary during skew.

Figure 13 is carrier wave frequency deviation 3KHz, the FPGA test result of carrier auxiliary during skew 45 °.

Figure 14 is the planisphere after carrier synchronization.

Figure 15 (a) is bit synchronization FPGA test result overview.

Figure 15 (b) is bit synchronization FPGA test result detailed view.

Figure 16 (a) is differential decoding, parallel-serial conversion FPGA test result overview.

Figure 16 (b) is differential decoding, parallel-serial conversion FPGA test result detailed view.

Figure 17 is that the theoretical error rate of 16QAM and Simulated BER contrast schematic diagram.

Embodiment

Be described below in conjunction with the modulation and demodulation process of accompanying drawing to 16QAM signal integrity, and verified by FPGA hardware.

One, modulation principle

1, differential coding

Consider the phase fuzzy problem of 16QAM, send signal and adopt Partial Differential coded system, namely only differential coding is carried out to the first two bit of 4bit parallel data.This coded system decreases the bit number of differential coding relative to fully differential coding, because this reducing error code diffusion, has good error performance.

In Partial Differential coding, with the first two bit a ₁a ₂quadrant residing for specified signal, and differential coding is carried out to it; Two remaining bit b ₁b ₂be used for specifying the configuration of signal phasor in each quadrant, and make configuration present the rotational symmetry of pi/2, as shown in Figure 1.

Coding rule:

If [ab] is absolute code, namely send information code element, [cd] is relocatable code, the code element namely after differential coding.

If $c_{i-1}\&CirclePlus;d_{i-1}=0,$ Then $\left\{\begin{array}{c}{c}_i=a_i\&CirclePlus;c_{i-1}\\ d_i=b_i\&CirclePlus;d_{i-1}\end{array}\right.;$ If $c_{i-1}\&CirclePlus;d_{i-1}=1,$ Then $\left\{\begin{array}{c}{c}_i=b_i\&CirclePlus;c_{i-1}\\ d_i=a_i\&CirclePlus;d_{i-1}\end{array}\right..$

Note: for mould 2 adds, i is Symbol times.

2, modulation principle

16QAM modulation of the present invention adopts quadrature amplitude modulation method, and the four level magnitudes keying signals utilizing two-way orthogonal are formed by stacking, and modulation FPGA realizes block diagram as shown in Figure 2.Input binary sequence becomes 4bit parallel data a through serioparallel exchange ₁a ₂b ₁b ₂, to a ₁a ₂a ' is obtained as differential coding ₁a ' ₂, b ₁b ₂remain unchanged, then to a ' ₁a ' ₂, b ₁b ₂carry out 2-4 level conversion respectively, produce the PAM signal of four level, this PAM signal has 2 kinds of amplitudes and 2 kinds of phase places.Two PAM signals modulate homophase and quadrature carrier respectively, and the modulation of each road has 4 kinds of possible outputs, and merge through adder and produce 16QAM signal, its formula is described as:

s(k)＝a(k)cos[ω _ckT _s+θ ₁]-b(k)sin[ω _ckT _s+θ ₁]

W in formula _cfor carrier frequency shift, θ ₁for initial phase, the homophase that a (k), b (k) they are base band symbol and quadrature component, T _sfor the sampling period.

The power spectrum of 16QAM signal as shown in Figure 3.Visible, 16QAM power spectrum signal is comparatively compact, and the availability of frequency spectrum is high, and the rate of information throughput is fast, can meet the demand of satellite communication.

Two, 16QAM signal receiving synchronization principles

Satellite received signal after Gaussian channel transmission can be expressed as:

r(k)＝a(k)cos[(ω _c±ω _d)kT _s+θ]-b(k)sin[(ω _c±ω _d)kT _s+θ]+n(t)

In formula, θ is carrier phase, ω _dfor Doppler frequency shift, n (t) is receiving terminal Gaussian noise.Received signal strength r (t) obtains homophase, orthogonal component signal after carrier auxiliary, low-pass filtering (LPF), thresholding is set carries out 4 level judgements by bit timing recovery, eventually pass level conversion and obtain parallel 4bit data, be i.e. the inverse process of constellation mapping.Corresponding Partial Differential decoding is carried out to the 4bit data after demodulation, can original information data be recovered by parallel-serial conversion.The synchronous FPGA theory diagram of demodulation as shown in Figure 4.

Three, 16QAM signal receiving process

1, carrier synchronization ring

Because 16QAM is non-constant envelope signal, what adopt the COSTAS loop demodulation of traditional Q PSK the very little guarantee phase discriminator that loop bandwidth is arranged must be exported is linear, and precision is not high, and tracking velocity is slow.The present invention, on the COSTAS loop basis of traditional Q PSK, increases the method for power detection judgement.Method is summarized as follows: suppose that n reception is to signal y (n), obtains signal q (n) after demodulation.Then power detection is carried out to signal q (n), namely by judging q (n) ²whether > τ (τ is power detection thresholding) becomes Rob Roy to select to need the received signal points of phase demodulation.| q (n) | ²during < τ, phase discriminator exports is 0, | q (n) | ²during > τ, phase discriminator exports phase error e (n) of this time-ofday signals point.Phase error control NCO after loop filter (LF) is level and smooth eliminates frequency deviation, skew gradually, reaches carrier synchronization.By choosing suitable power detection thresholding τ, then the phase error detection planisphere of 16QAM can be converted to the planisphere of QPSK, then adopt classical COSTAS loop to carry out demodulation, overcome the impact on phase discriminator of the non-permanent envelope of 16QAM.Its FPGA realizes theory diagram as shown in Figure 5.

Loop algorithm is derived as follows.If Received signal strength r (k) is:

r(k)＝a(k)cos[(ω _c±ω _d)kT _s+θ]-b(k)sin[(ω _c±ω _d)kT _s+θ]+n(t)

ω in formula _dfor Doppler frequency shift, θ is carrier phase, and n (t) is receiving terminal Gaussian noise, the homophase that a (k), b (k) are base band symbol and quadrature component, T _sfor the sampling period.Signal obtains after quadrature downconvert, low-pass filtering removing high fdrequency component:

U _I(k)＝a(k)cos[(ω _c±ω _d-ω _o)kT _s+θ-θ _o]-b(k)sin[(ω _c±ω _d-ω _o)kT _s+θ-θ _o]

U _Q(k)＝b(k)cos[(ω _c±ω _d-ω _o)kT _s+θ-θ _o]+a(k)sin[(ω _c±ω _d-ω _o)kT _s+θ-θ _o]

Power detection value P (k):

P(k)＝(U _I(k)) ²+(U _Q(k)) ²

As P (k) < τ, phase detector error e (k)=0; As P (k) > τ, make Δ φ=(ω _c± ω _d-ω _o) kT _s+ θ-θ _o, by U _i, U _qsend into phase discriminator, phase discriminator is based on hard decision algorithm herein.When time very little, can phase detector error e (k) be obtained:

16QAM is after power detection judgement, the a (k), the b (k) that enter phase discriminator calculating only have a kind of amplitude, therefore | a (k) |+| b (k) | be constant, error amount control NCO after loop filter is level and smooth eliminates frequency deviation residual error and phase error gradually, reaches carrier synchronization.

2, bit timing synchronous ring

Because the clock of transmitter and receiver can exist certain phase deviation and clock skew, along with the accumulation gradually of skew then can cause error code, have a strong impact on systematic function.The present invention adopts based on the algorithm of door sooner or later of self-synchronizing method, is applicable to the system of high power sample rate, can "ball-park" estimate clock skew, is simple for structurely easy to hardware implementing.Its FPGA realizes block diagram as shown in Figure 6.

Door algorithm utilizes the symmetry of signal after matched filter to carry out bit timing synchronously sooner or later, and as shown in Figure 7, wherein Fig. 7 (a) is rectangular pulse signal schematic diagram, and Fig. 7 (b) is that matched filtering exports schematic diagram.。

Signal optimum sampling moment after matched filter is t=nT, but due to noise, clock skew may cause sampling cannot in the code element signal to noise ratio maximum moment.When the sample value in transition value t=nT-τ and t '=nT+ τ moment is equal, the optimum sampling moment is just at the center time point of two sampling instants.If there is sampling late, the difference of adjacent transition value can be detected, by feedback loop control sampling clock, as the same during generation early sampling.Based on this principle, utilize adjacent two symbol transition values whether equal, add amplitude and this information of polarity of optimum sampling point, make τ=T/2, the model of Timing Error Detector can be derived:

$\begin{array}{c}e\left(n\right)=u_I(n+\mathrm{\&tau;}\left(n\right))[u_I(n+\frac{1}{2}+\mathrm{\&tau;}\left(n\right))-u_I(n-\frac{1}{2}+\mathrm{\&tau;}(n-1))]\\ +u_Q(n+\mathrm{\&tau;}\left(n\right))[u_Q(n+\frac{1}{2}+\mathrm{\&tau;}\left(n\right))-u_Q(n-\frac{1}{2}+\mathrm{\&tau;}(n-1))]\end{array}$

In formula, τ (n) is the sampling clock compensated, represent the transition value of the (n+1)th and n-th code element, represent the transition value of n-th and (n-1)th code element, NCO exports and is can be obtained fom the above equation:

τ(n+1)＝τ(n)+γ·e(n)

In formula, γ is step parameter, and τ (n) is the sampling clock compensated.Finally obtain the 4bit parallel data after demodulation through over level conversion after many level sample judgements, now also need differential decoding and parallel-serial conversion just can restore original binary code stream.

3, differential decoding

Differential coding is corresponding, if [ab] is absolute code, the information code element namely restored, [cd] is relocatable code, the code element namely after demodulation.

If $c_{i-1}\&CirclePlus;d_{i-1}=0,$ Then $\left\{\begin{array}{c}{a}_i=c_i\&CirclePlus;c_{i-1}\\ b_i=d_i\&CirclePlus;d_{i-1}\end{array}\right.;$ If $c_{i-1}\&CirclePlus;d_{i-1}=1,$ Then $\left\{\begin{array}{c}{a}_i=d_i\&CirclePlus;d_{i-1}\\ b_i=c_i\&CirclePlus;c_{i-1}\end{array}\right..$

Note: for mould 2 adds, i is Symbol times.

Four, the FPGA checking of total system

As shown in Figure 8, transmitter module produces 16QAM modulation signal to the FPGA schematic diagram of total system, is converted to analog signal by D/A; A/D by SMA cable sampling transmitter module produce signal, the receiver module in chip carries out demodulation to sampled signal again, data by JTAG mouth and PC mutual.

1, modulation signal produces

Test condition: sample rate f _s=100MHz, information rate R _b=100M/16=6.25Mbps, carrier frequency f _c=100M/8=12.5MHz.

The modulation signal of transmitting terminal after differential coding as shown in Figure 9.

Utilize MATLAB to read the FPGA output waveform of QUARTUS-II software grabs as shown in Figure 10 (a), calculate the planisphere of 16QAM modulation signal as shown in Figure 10 (b).

From time domain waveform and planisphere, the 16QAM signal that FPGA internal modulation goes out meets the requirements.Because the local carrier produced when FPGA internal modulation carrier wave and MATLAB software demodulation exists frequency difference, differs, therefore square constellations has inclination, by carrier synchronization, just need can obtain correct planisphere, and then demodulate signal.

2, carrier auxiliary test

The FPGA test result of carrier auxiliary is as follows:

(1) carrier wave is without frequency deviation, and as shown in figure 11, first via signal is Phase Tracking curve in phase deviation 22.5 °, because skew is fixed and without frequency deviation, therefore pursuit gain perseverance is constant, shows successfully to follow the tracks of skew.Second, third road signal is respectively baseband inphase, quadrature component after carrier auxiliary, is 4 level signals after recovery.

(2) carrier wave frequency deviation 3KHz, without skew as shown in figure 12, when carrier wave exists frequency shift (FS), Phase Tracking value becomes linear function linear change, and tracking frequency changes.4 level baseband homophases, orthogonal signalling are obtained after carrier auxiliary.

(3) carrier wave frequency deviation 3KHz, skew 45 ° as shown in figure 13.

As shown in figure 14, the planisphere recovery level of the known 16QAM baseband signal obtained after carrier synchronization, can carry out sampling judgement to planisphere after carrier synchronization.

3, bit synchronization test

As shown in figure 15, wherein Figure 15 (a) is overview to bit synchronization FPGA test result, and Figure 15 (b) is detailed view.Test condition: carrier wave frequency deviation 3KHz, skew 45 °, bit synchronization clock phase skew 40% (relative to code-element period).

First via signal is the bit synchronization clock recovered, and second, third road is respectively the output signal after baseband inphase, quadrature component matched filtering, and the 4th, the 5th tunnel is respectively homophase, orthogonal 4 level signals after sampling judgement.As can be seen from the figure to have sampled comparatively accurately the peak value moment after matched filtering based on the bit synchronization clock that door algorithm recovers sooner or later, shown that the bit synchronization circuit work in FPGA is good.

4, differential decoding, parallel-serial conversion test

As shown in figure 16, wherein Figure 16 (a) is overview for differential decoding, parallel-serial conversion FPGA test result, and Figure 16 (b) is detailed view.Test condition: carrier wave frequency deviation 3KHz, skew 45 °, bit synchronization clock phase skew 40% (relative to code-element period).

By level conversion, carry out the inverse process of planisphere mapping, 4bit parallel data can be obtained, then carry out differential decoding and parallel-serial conversion, finally recover binary code stream.

The first via be input binary code flow through string turn and after 4bit parallel data; Second tunnel is the 4bit parallel data recovered after carrier auxiliary and bit synchronization restoration, level conversion, i.e. the inverse process that maps of planisphere, and because demodulation exists phase ambiguity, therefore the second circuit-switched data may not be identical with first via data; 3rd tunnel is the output after differential decoding, and now data are identical with first via data; 4th tunnel is input binary code stream, and the 5th tunnel is the binary code stream recovered after differential decoding data parallel-serial conversion.After about postponing 500 sampled points as seen from the figure, signal obtains correct demodulation result.

The above results shows, adding differential encoding in 16QAM can solve phase fuzzy problem well.In the module of carrier synchronization, power detection techniques is introduced on the basis of traditional Costas loop, ensure the linear convergent rate of phase discriminator, improve tracking accuracy and speed, overcome the harmful effect of 16QAM to phase discriminator in demodulation is synchronous, significantly improve systematic function.Synchronization module in place, the algorithm of door sooner or later based on self-synchronizing method that the present invention adopts, is applicable to the system of high power sample rate, can "ball-park" estimate clock skew, is simple for structurely easy to FPGA hardware implementing.

By verifying that the present invention is carried algorithm performance further, Figure 17 provides the theoretical error rate and the Simulated BER of 16QAM, adopts the 16QAM error rate of this algorithm very close to theoretical value.

Embody rule approach of the present invention is a lot, and the above is only the preferred embodiment of the present invention, should be understood that; for those skilled in the art; under the premise without departing from the principles of the invention, can also make some improvement, these improvement also should be considered as protection scope of the present invention.

Claims (2)

1. a 16QAM demodulation synchronous method, is characterized in that comprising the following steps:

1) carrier synchronization: suppose that n reception is to signal y (n), obtains signal q (n) after demodulation, τ is power detection thresholding, when | q (n) | ²during < τ, phase discriminator exports is 0, | q (n) | ²during > τ, phase discriminator exports phase error e (n) of this time-ofday signals point, and phase error control NCO after loop filter is level and smooth eliminates frequency deviation, skew gradually, reaches carrier synchronization; Choose suitable power detection thresholding τ, the phase error detection planisphere of 16QAM is converted to the planisphere of QPSK, then adopt COSTAS loop to carry out demodulation;

2) respectively matched filtering is carried out to inphase quadrature component signal;

3) by " sooner or later door ", bit timing recovery is carried out to inphase quadrature signal, makes τ=T/2, the model of Timing Error Detector can be derived:

$\begin{array}{c}e\left(n\right)=u_I(n+\mathrm{\&tau;}\left(n\right))[u_I(n+\frac{1}{2}+\mathrm{\&tau;}\left(n\right))-u_I(n-\frac{1}{2}+\mathrm{\&tau;}(n-1))]\\ +u_Q(n+\mathrm{\&tau;}\left(n\right))[u_Q(n+\frac{1}{2}+\mathrm{\&tau;}\left(n\right))-u_Q(n-\frac{1}{2}+\mathrm{\&tau;}(n-1))]\end{array}$

In formula, τ (n) is the sampling clock compensated, represent the transition value of the (n+1)th and n-th code element, represent the transition value of n-th and (n-1)th code element.Can obtain NCO output by formula (6) is:

τ(n+1)＝τ(n)+γ·e(n)；

4) arrange thresholding to two paths of signals carry out respectively sampling judgement and 4-2 level conversion obtain parallel signal;

5), after differential decoding and parallel-serial conversion being carried out to parallel signal, primary signal is recovered.

2. 16QAM demodulation synchronous method according to claim 1, is characterized in that: step 1) in phase error e (n) derive as follows, if Received signal strength r (k) is:

r(k)＝a(k)cos[(ω _c±ω _d)kT _s+θ]-b(k)sin[(ω _c±ω _d)kT _s+θ]+n(t),

ω in formula _dfor Doppler frequency shift, θ is carrier phase, and n (t) is receiving terminal Gaussian noise, the homophase that a (k), b (k) are base band symbol and quadrature component, T _sfor the sampling period; Signal obtains after quadrature downconvert, low-pass filtering removing high fdrequency component:

U _I(k)＝a(k)cos[(ω _c±ω _d-ω _o)kT _s+θ-θ _o]-b(k)sin[(ω _c±ω _d-ω _o)kT _s+θ-θ _o],

U _Q(k)＝b(k)cos[(ω _c±ω _d-ω _o)kT _s+θ-θ _o]+a(k)sin[(ω _c±ω _d-ω _o)kT _s+θ-θ _o],

Power detection value P (k) is:

P(k)＝(U _I(k)) ²+(U _Q(k)) ²

As P (k) < τ, phase detector error e (k)=0; As P (k) > τ, order , by U _i, U _qsend into phase discriminator, phase discriminator is based on hard decision algorithm herein, when time very little, can phase detector error e (k) be obtained: