CN105530213A - Mixed baseband system for high speed communication - Google Patents
Mixed baseband system for high speed communication Download PDFInfo
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- CN105530213A CN105530213A CN201510943869.4A CN201510943869A CN105530213A CN 105530213 A CN105530213 A CN 105530213A CN 201510943869 A CN201510943869 A CN 201510943869A CN 105530213 A CN105530213 A CN 105530213A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03343—Arrangements at the transmitter end
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/64—Hybrid switching systems
- H04L12/6418—Hybrid transport
Abstract
The invention discloses a mixed baseband system for high speed communication, comprising a modulus carrier recovering module which comprises a phase rotator, is connected to the output of a high speed communication system and is used for receiving signals demodulated by the high speed communication system and removing the influence of carrier deviation on the signals through recovering the phase of a sender; a data feedback equalizing module which is connected to the modulus carrier recovering module and is used for equalizing the signals output by the modulus carrier recovering module so as to reduce the influence of intersymbol interference and further increase the Signal to Noise Ratio; a clock and data covering module which is connected to the data feedback equalizing module and is used for recovering a clock and demodulating the signals output by the data feedback equalizing module so as to obtain and output finally demodulated signals. Compared with the prior art, the system of the invention simplifies the baseband design of a receiver and saves power consumption on the premise of ensuring signal transmission processing precision and accuracy.
Description
Technical field
The present invention relates to the communications field, relate to a kind of mixing baseband system for high-speed communication specifically.
Background technology
Along with the development of the communication technology, in prior art, propose 60GHz millimeter wave high-speed communication system.
The channel width that the standard of 60GHz millimeter wave high-speed communication system takies relative to traditional communication up to 7GHz or larger (frequency range exempting to permit is 57GHz to 64GHz by the such as U.S.), thus provides possibility for superfast traffic rate.The speed of current 60GHz millimetre-wave attenuator can reach Gbps, and 802.11n standard and the carrierfree communication technology (UltraWideband, UWB) can only realize 600Mbps and 480Mbps.
Relative to traditional communication standards, the communication system of 60GHz frequency range has many good qualities.First, because the directivity of 60GHz frequency range wireless signal is very strong, thus the signal of communication of 60GHz communication system on different directions disturbs very little mutually; In addition, the carrier wave of wireless communication standard known at present is all far smaller than 60GHz, disturbs also therefore very little, almost ignore between the communication system from other communication systems.Secondly, the loss of the signal on 60GHz on free space is very large, reaches 15dB/km, and barrier is also very large to the Attenuation of 60GHz, and therefore, the short-distance wireless communication on 60GHz has the inherent advantage on high security.Again, the communication system of the 60GHz of integrated circuit monolithic design is less relative to the component size of traditional communication standards mandate, thus can reduce costs.
Current 60GHz millimeter-wave communication system is in the middle of burning hot research, existing standard also disunity, comprises 802.11ad that ieee standardization tissue releases, WirelessHD1.1 that the WirlessHD working group that set up by LG and Panasonic etc. releases and the WiGig1.0 of WiGig Leagues enact that is made up of Intel and Nokia etc.Multiple skimble-scamble standard result between different system framework and is difficult to realize compatible coupling.
In addition, the framework that current more 60GHz millimeter-wave communication system design adopts remains traditional transceiver pattern, this pattern usually by the separately design of radio-frequency front-end, Analog Baseband and digital baseband, therefore causes between analog baseband circuitry and digital baseband circuit and needs an analog to digital converter ADC.Because the communication data rate of 60GHz millimetre-wave attenuator is very high, the ADC performance of corresponding requirement is very high, thus causes ADC design difficulty and power consumption often very large.In addition, due to the communication up to Gbps data transfer rate, the reversal rate of digital baseband circuit will be very fast, cause the power consumption of digital baseband circuit also very large.
Therefore, for 60GHz millimeter-wave communication system Problems existing in prior art, need a kind of mixing baseband system for high-speed communication newly.
Summary of the invention
For 60GHz millimeter-wave communication system Problems existing in prior art, the invention provides a kind of mixing baseband system for high-speed communication, described system comprises module carrier and recovers module, data feedback balance module and clock and data recovery module, wherein:
Described module carrier recovers module and comprises phase rotation device, it is connected to the output of high-speed communication system, described phase rotation device is for rotating the phase place of input signal, and described module carrier recovers module for the signal that receives high-speed communication system demodulation and get off and eliminates the impact of carrier deviation on described signal by the phase place recovering transmitter;
Described data feedback balance module is connected to described module carrier and recovers module, recovers the signal of module output thus the impact of reduction intersymbol interference, and then increase signal to noise ratio for the described module carrier of equilibrium;
Described clock and data recovery model calling is to described data feedback balance module, and the signal that data feedback balance module exports for recovered clock and described in demodulation is to obtain and to export last solution tonal signal.
In one embodiment, described module carrier recovers module and also comprises the first error detector and first ring path filter, wherein:
Described first error detector is connected in the output of described clock and data recovery module, for detecting described last solution tonal signal thus obtaining the first error signal;
Described first ring path filter is connected with described first error detector, and described first ring path filter exports the first control word for controlling described phase rotation device based on described error signal;
Described phase rotation device is connected with described first ring path filter, and described phase rotation device exports after input signal being rotated corresponding phase place under the control of described first control word.
In one embodiment, described data feedback balance module comprises the first amplifier for amplifying signal and the first signal path for signal transmission, wherein:
The output that input and the described module carrier of described first amplifier recover module is connected;
The input of described first signal path is connected with the output of described first amplifier, and the output of described first signal path is the output of described data feedback balance module.
In one embodiment, described data feedback balance module also comprises data feedback equalizer, and described data feedback equalizer comprises:
Second error detector, it is connected with the output of described clock and data recovery module, for detecting described last solution tonal signal thus obtaining the second error signal;
Data sampler, it is connected to described first signal path, for gathering analog signal that described first signal path transmits and the described analog signal collected being converted to digital sampled signal;
Second loop filter, it is connected with described second error detector and described data sampler, for exporting the second control word based on described second error signal and described digital sampled signal;
First euqalizing current source branch road, its be connected with described second loop filter and be connected to described data sampler access point and described first amplifier on described first signal path export between position, for the signal data described first signal path transmitted to the first branch current that described first signal path exports specific size and Orientation with equilibrium based on described second control word.
In one embodiment, described data feedback balance module also comprises tail equalizer, and described tail equalizer comprises:
3rd error detector, it is connected on the position after the access point of described first euqalizing current source branch road on described first signal path, for detecting signal thus acquisition the 3rd error signal that described first signal path transmits;
Three links theory filter, it is connected with described 3rd error detector, for exporting the 3rd control word based on described 3rd error signal;
Shift register array, it is connected with described clock and data recovery module, for carrying out time delay displacement to the data demodulated;
Second euqalizing current source branch road, it is connected with described Three links theory filter and described shift register array and is connected to the position on described first signal path between described 3rd error detector and described first euqalizing current source branch road access point, for the signal data described first signal path transmitted to the second branch current that described first signal path exports specific size and Orientation with equilibrium based on the output of described 3rd control word and described shift register array.
In one embodiment, described clock and data recovery module comprises:
Lead-lag phase discriminator, it is connected with the output of described clock and data recovery module, for analyzing described last solution tonal signal thus obtaining lead-lag signal;
Fourth Ring road filter, it is connected with described lead-lag phase discriminator, for exporting the 4th control word based on described lead-lag signal;
Phase interpolator, it is connected with described Fourth Ring road filter and is connected to described high-speed communication system, for obtaining the fractional frequency signal of described high-speed communication system and entering horizontal phasing control according to described 4th control word to described fractional frequency signal;
Clock shaping buffer, it is connected with described phase interpolator, for obtaining according to the described fractional frequency signal adjusted through phase place and exporting corresponding square wave clock;
Duty ratio adjuster, it is connected with described clock shaping buffer, for exporting corresponding sampling clock according to described square wave clock;
Sampling output unit, it comprises signal input part, signal output part and control end, wherein, described control end is connected with described duty ratio adjuster, described signal input part and described signal output part are respectively input and the output of described clock and data recovery module, and described sampling output unit is used for sampling to input signal based on described sampling clock thus obtaining described last solution tonal signal.
In one embodiment, described system also comprises modulus direct current and eliminates feedback module, described modulus direct current is eliminated feedback module and is arranged between described data feedback balance module and described clock and data recovery module, for eliminating the DC maladjustment of the signal that described data feedback balance module exports.
In one embodiment, described modulus direct current elimination feedback module comprises:
Second amplifier, its input is connected to the output of described data feedback balance module;
Secondary signal path, its input is connected to the output of described second amplifier, and output is connected to the input of described clock and data recovery module;
4th error detector, it is connected to the output of described secondary signal path, obtains the 4th error signal for the output signal based on described secondary signal path;
Fourth Ring road filter, it is connected with described 4th error detector, for exporting the 5th control word based on described 4th error signal;
Reference voltage generator, it is connected with described Fourth Ring road filter and accesses described secondary signal path, for based on described 5th control word to described secondary signal path output reference voltage to eliminate the DC maladjustment of the signal that described secondary signal path transmits.
In one embodiment, described modulus direct current is eliminated feedback module and is also comprised the 3rd amplifier, it is connected between described reference voltage generator and described secondary signal path, for amplifying the described reference voltage of the described reference voltage generator output of adjustment and the described reference voltage after amplifying adjustment being outputted to described secondary signal path to realize eliminating DC maladjustment.
In one embodiment, described modulus direct current is eliminated feedback module and is also comprised DC maladjustment detector, described DC maladjustment detector for detecting in described last solution tonal signal whether there is DC maladjustment, thus controls based on testing result the On/Off that described modulus direct current eliminates feedback module.
Compared with prior art, system of the present invention simplifies the baseband design of receiver and has saved power consumption under the prerequisite ensureing process of signal transmission precision and accuracy.
Further feature of the present invention or advantage will be set forth in the following description.Further, Partial Feature of the present invention or advantage will be become apparent by specification, or be understood by implementing the present invention.Object of the present invention and certain advantages realize by step specifically noted in specification, claims and accompanying drawing or obtain.
Accompanying drawing explanation
Accompanying drawing is used to provide a further understanding of the present invention, and forms a part for specification, with embodiments of the invention jointly for explaining the present invention, is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is according to one embodiment of the invention system configuration sketch.
Embodiment
Embodiments of the present invention are described in detail below with reference to drawings and Examples, enforcement personnel of the present invention whereby can fully understand how application technology means solve technical problem in the present invention, and reach the implementation procedure of technique effect and specifically implement the present invention according to above-mentioned implementation procedure.It should be noted that, only otherwise form conflict, each embodiment in the present invention and each feature in each embodiment can be combined with each other, and the technical scheme formed is all within protection scope of the present invention.
Current 60GHz millimeter-wave communication system is in the middle of burning hot research, existing standard also disunity, and multiple skimble-scamble standard result between different system framework and is difficult to realize compatible coupling.In addition, the framework that current more 60GHz millimeter-wave communication system design adopts remains traditional transceiver pattern, this pattern usually by the separately design of radio-frequency front-end, Analog Baseband and digital baseband, therefore causes between analog baseband circuitry and digital baseband circuit and needs an analog to digital converter ADC.Because the communication data rate of 60GHz millimetre-wave attenuator is very high, the ADC performance of corresponding requirement is very high, thus causes ADC design difficulty and power consumption often very large.In addition, due to the communication up to Gbps data transfer rate, the reversal rate of digital baseband circuit will be very fast, cause the power consumption of digital baseband circuit also very large.
For 60GHz millimeter-wave communication system Problems existing in prior art, the present invention proposes a kind of mixing baseband system for high-speed communication.As shown in Figure 1, in an embodiment of the present invention, system comprises module carrier recovery module 110, data feedback balance module 120 and clock and data recovery module 150.
Module carrier recovers module 110 and comprises phase rotation device 111.Module carrier recovers the output that module 110 is connected to high-speed communication system, and phase rotation device 111 is for rotating the phase place of input signal.Module carrier recovers module 110 for the signal that receives high-speed communication system demodulation and get off and eliminates the impact of carrier deviation on signal by the phase place recovering transmitter.
Data feedback balance module 120 is connected to module carrier and recovers module 110, the signal exported for balanced modulus carrier recovery block thus reduce the impact of intersymbol interference, and then increases signal to noise ratio.
Clock and data recovery module 150 is connected to data feedback balance module 120, for recovered clock and demodulating data feedback equalization module 120 export signal to obtain and to export last solution tonal signal.
Further, in the present embodiment, data feedback balance module 120, module carrier recovery module 110 and clock and data recovery module 150 are configurable adaptation module.Radiofrequency signal is through the Quadrature Phase Shift Keying (QuadraturePhaseShiftKeyin of high-speed communication system, QPSK) phase rotation device 111 in configurable module carrier recovery module 110 is input to after demodulator, phase rotation device 111 rotates the signal that input is come in, and makes its output signal no longer because carrier phase and the inconsistent and deterioration that brings of frequency.Phase rotation device 111 output signal gives data feedback balance module 120, and this part reduces the deterioration of the signal to noise ratio caused because of the intersymbol interference that causes of the reason such as channel or coding.Data feedback balance module 120 outputs signal to the sampling output of clock and data recovery module 150.
In the present embodiment, the employing of data feedback balance module 120 is because the time variation of channel and unpredictability.The adaptive equalization process of data feedback balance module 120 is exactly adjustment loop filter coefficient, balanced output signal is made to reach minimum with the mean square of error error between desirable output, and the mode adjusting filter coefficient carries out progressive alternate towards the steepest descent direction of mean square error sphere, finally reaches least mean-square error.And the step-length of adjustment namely also the same convergence rate of gain of loop filter, the stability of a system, input signal-to-noise ratio, final convergence error have much relations, can select flexibly to restrain step-length by the mode of configuration so originally state invention, thus select optimal result in above-mentioned compromise.
In order to reduce output error, in the present embodiment, module carrier recovers module 110 and also comprises the first error detector 112 and first ring path filter 113, wherein: the first error detector 112 is connected in the output (output that system is last) of clock and data recovery module 150, for detecting last solution tonal signal thus obtaining the first error signal; First ring path filter 113 is connected with the first error detector 112, and the error signal that first ring path filter 113 exports based on the first error detector 112 exports the first control word being used for control phase circulator 111; Phase rotation device 111 is connected with first ring path filter 113, and phase rotation device 111 exports after input signal being rotated corresponding phase place under the control of the first control word.
Module carrier recovers module 110 and mainly solves due to transmitter and receiver local oscillator because frequency drift and the inconsistent signal distortion caused of phase place.In the present embodiment, for be Quadrature Phase Shift Keying (QuadraturePhaseShiftKeyin, QPSK) modulation system on 60GHz.The signal that configurable module carrier recovery module 110 receives can represent with following formula:
In formula 1:
T is time variable;
X is the signal transient phase place being input to phase rotation device 111 after being interfered;
Δ f and
represent the frequency difference existed between Receiver And Transmitter and initial phase difference respectively;
I and Q is the input orthogonal signalling before being interfered;
I (in) and Q (in) is for being input to the signal of phase rotation device 111 after being interfered;
Amp represent be interfered after be input to the signal transient amplitude of phase rotation device 111.
Can be seen by formula 1, when input I/Q be subject to Δ f and
after interference, the input signal I (in) and the Q (in) that enter into phase rotation device 111 just there will be distortion in amplitude.Signal can represent with following formula after phase rotation device 111 rotates:
In formula 2:
The signal that I (out) and Q (out) exports for phase rotation device 111;
Y is the anglec of rotation of phase rotation device.
Can see from formula 2, after rotation, the phase place of orthogonal signalling compensates to some extent compared at original signal, when compensation rate is inconsistent with input difference, output signal distorts to some extent equally in amplitude, signal of this distortion the first error detector 112 can be made to detect error supply first ring path filter 113 uses, when the deviation that the amount compensated causes with local oscillator is identical, loop will enter lock-out state.Due to phase rotation device 111 change is phase mass, and containing frequency departure in the departure of local oscillator, follow the tracks of the difference that frequency difference causes, first ring path filter 113 is at least designed to second order.After loop enters tracking lock state, initial phase difference is repaired, the frequency difference existed is also tracked in second order digital first ring path filter 113, and the phase place that per clock cycle output control word makes phase rotation device 111 rotate is consistent with the phase place caused by frequency, thus recovers carrier wave.
In addition, because the lock speed of loop and the gain of stability same frequency path of integration have very large relation, and also there is direct relation in frequency integrator path with the frequency departure that can correct, so system of the present invention by the gain in the frequency departure scope configuration frequency path in reality, thus can functionally do optimum selection at lock speed and stability.
Data feedback balance module 120 solves the intersymbol interference caused because of channel, simply can be represented the sampling of the impulse response of bandwidth efficient channel by following formula.
h(t)＝H
1(t)+H(t-nT)(n＝1,2......)(3)
In formula 3: h (t) represents total impulse response of the bandwidth efficient channel when moment t.Wherein, H
1t () represents the response to the signal of current time t; H (t-nT) represents the response (interference) produced the signal after n sampling clock, and wherein n is integer, and T is the cycle of sampling clock.
Can see from formula 3, the signal that the signal of moment t can be sampled to next clock T produces interference.The data feedback balance module 120 of the present embodiment is exactly reduce even to eliminate this interference.
In the present embodiment, data feedback balance module 120 comprises for the first amplifier 121 of amplifying signal and the first signal path for signal transmission, wherein: the output (output of phase rotation device 111) that input and the module carrier of the first amplifier 121 recover module 110 is connected; The input of the first signal path is connected with the output of the first amplifier 121, and the output of the first signal path is the output of data feedback balance module.
Further, in the present embodiment, data feedback balance module 120 also comprises data feedback equalizer 122, and data feedback equalizer 122 compensates the loss that current data is introduced, and it comprises:
Second error detector 125, it is connected with the output of clock and data recovery module 150, for detecting last solution tonal signal thus obtaining the second error signal;
Data sampler 126, it is connected to the first signal path, for gathering analog signal that the first signal path transmits and the analog signal collected being converted to digital sampled signal;
Second loop filter 124, it is connected with the second error detector 125 and data sampler 126, for exporting the second control word based on the second error signal and digital sampled signal;
First euqalizing current source branch road 123, it is connected with the second loop filter 124 and is connected to the first signal path for exporting the first branch current of specific size and Orientation with the signal data that balanced first signal path transmits based on the second control word to the first signal path.First euqalizing current source branch road 123 is the position between data sampler 126 access point and the first amplifier 121 export in the on-position of the first signal path, the consequential signal that what such data sampler 126 was sampled is just after the first euqalizing current source branch road 123 equilibrium.
Further, in the present embodiment, data feedback balance module 120 also comprises tail equalizer 130.; Tail equalizer compensates the crosstalk that the data received above are introduced and eliminate, and it comprises:
3rd error detector 133, it is connected on the position after the access point of the first euqalizing current source branch road 123 on the first signal path, for detect signal that the first signal path transmits thus obtain the 3rd error signal (detection be the first euqalizing current source branch road 123 equilibrium after consequential signal);
Three links theory filter 132, it is connected with the 3rd error detector 133, for exporting the 3rd control word based on the 3rd error signal;
Shift register array 134, it is connected with clock and data recovery module 150, for carrying out time delay displacement to the data demodulated;
Second euqalizing current source branch road 131, it is connected with Three links theory filter 132 and shift register array 134 and is connected to the position on the first signal path between the 3rd error detector 133 and the first euqalizing current source branch road 123 access point, for exporting the second branch current of specific size and Orientation to the first signal path with the signal data that balanced first signal path transmits based on the output (signal that shift register array exports is the signal obtained after the data demodulated carry out time delay) of the 3rd control word and shift register array.
Concrete, the euqalizing current branch road on the output co-controlling correspondence position of the 3rd control word that Three links theory filter 132 exports and shift register array 134, controls its number opened and direction, thus balanced current data.
In the present embodiment, the effect of clock and data recovery module 150 from the data of input, recovers clock and complete final digital signal to export, and clock and data recovery module 150 has finally adjusted by clock shaping buffer the recovery that duty ratio realizes clock again mainly through regulating main phase-locked loop output signal of frequency divider phase place.And the phase-adjusted realization of output signal of frequency divider is realized by quadrature phase interpolation device, its principle can be explained by following formula.
In formula 4:
OUTI and OUTQ represents the output after adjustment;
CLKI and CLKQ represents that the quadrature divider of main phase-locked loop exports;
IA, IB, IC, ID are for the output control word of loop filter;
α 1=IA-IB, α 2=IC-ID represent the relative multiplication factor of CLKI with CLKQ signal respectively.
The phase place of output clock just can be changed by regulation output control word.Input signal is sampled respectively through the rising edge of CLKI and trailing edge clock and CLKQ rising edge and is sent lead-lag phase discriminator to and identify lead-lag information, again this information is sent to loop filter, control figure loop filter upgrades the size and Orientation exporting control word.
Consistent with carrier auxiliary, the recovery due to clock not only needs to recover moderate phase place also will recover difference on the frequency between clock and data, and the present embodiment have employed the drift of a second order digital loop filter tracking frequency.In addition, due to secondary loop filter the same lock speed of frequency integrator loop gain, locking deviation range and loop stability between there are much relations, so the present invention can carry out optimum manual configuration as required.The signal exported through phase interpolator becomes the output signal of the full amplitude of oscillation again by clock shaping buffer, finally by the sampling clock becoming 50% duty ratio after having adjusted duty ratio.
The principle of dutyfactor adjustment circuit is summarized as follows: the DC level that duty is less than the signal of 50% is less than full amplitude of oscillation level half, and the difference other end must be greater than full amplitude of oscillation level half, the DC terms of differential clocks is taken out by single order RC filter, both difference are compared by a comparator, then regulate the common mode electrical level of duty cycle adjustment device-inverter, thus finally make the duty ratio of output clock be 50%.
Concrete, clock and data recovery module 150 comprises lead-lag phase discriminator 152, Fourth Ring road filter 153, phase interpolator 154, clock shaping buffer 155, duty ratio adjuster 156 and sampling output unit 151.
Lead-lag phase discriminator 152 (lead-lag phase-shift discriminator (BangBangPD)) is connected with the output of clock and data recovery module 150, for analyzing last solution tonal signal thus obtaining lead-lag signal.
Fourth Ring road filter 153 is connected with lead-lag phase discriminator 152, for exporting the 4th control word based on lead-lag signal.
Phase interpolator 154 is connected with Fourth Ring road filter 153 and is connected to high-speed communication system, for obtaining the fractional frequency signal of high-speed communication system and entering horizontal phasing control according to the 4th control word to fractional frequency signal.
Clock shaping buffer 155 (current forms latch type clock is to complementary bipolar transistor type (CMOS) clock shaping buffer (buffer)) is connected with phase interpolator 154, for obtaining according to the fractional frequency signal adjusted through phase place and exporting corresponding square wave clock;
Duty ratio adjuster 156 is connected with clock shaping buffer 155, exports corresponding sampling clock for the square wave clock exported according to clock shaping buffer 155.
Sampling output unit 151 comprises signal input part, signal output part and control end, wherein, the control end of sampling output unit 151 is connected with duty ratio adjuster 156, signal input part and signal output part are respectively input and the output of clock and data recovery module 150, and sampling output unit 151 is for sample to input signal based on sampling clock thus obtain last solution tonal signal.
Concrete, duty cycle adjustment device 156 itself is made up of two identical inverter, capacitance, direct current biasing resistance, difference single order RC filter, error comparator and bias voltage generator and digital control module.The difference output of clock shaping buffer 155 delivers to the input of two identical inverters respectively through capacitance, the output of an inverter of duty cycle adjustment device 156 delivers to sampling output unit 151 as aforementioned on the one hand, delivers to difference single order RC filter respectively on the other hand.Difference flip-flop is separately retained after difference single order RC filter filtering high fdrequency component.Two flip-flop signals receive the two ends of comparator respectively, the output signal of comparator gives control module, control module exports control word and controls the bias voltage that bias voltage generator produces corresponding difference, and the input that differential bias voltage is added to both direction device respectively by biasing resistor regulates respective DC point.
Further, in the present embodiment, system also comprises modulus direct current elimination feedback module 140.Modulus direct current is eliminated feedback module 140 and is arranged between data feedback balance module 120 and clock and data recovery module 150, for eliminating the DC maladjustment of the signal that described data feedback balance module exports.
In the present embodiment, data feedback balance module 120 outputs signal to modulus direct current and eliminates feedback module 140.Modulus direct current is eliminated feedback module 140 and is eliminated by prime and the DC maladjustment caused at the corresponding levels, and the signal then after Drazin inverse is to clock and data recovery module 150.Clock sampling data that clock and data recovery module 150 utilizes this part to recover thus recover data.
The mode that modulus direct current elimination feedback module 140 solves DC maladjustment is by increasing auxiliary amplifying unit, and the output of the output of auxiliary amplifying unit with main amplifying unit is connected together.The DC error introduced of the prime Cumulate Sum corresponding levels can equivalence in the DC maladjustment of the output of main amplifier, when at the original input of base band not input signal, by the output of sampler samples main amplifier, by constantly adjusting the input difference bias voltage of booster amplifier, make the output convergence and zero of main amplifier, thus finally eliminate the prime Cumulate Sum corresponding levels and cause DC maladjustment.
Concrete, in the present embodiment, modulus direct current is eliminated feedback module 140 and is comprised:
Second amplifier 141, its input is connected to the output (output of the first signal path) of data feedback balance module 150;
Secondary signal path, its input is connected to the output of the second amplifier 141, and output is connected to the input of clock and data recovery module 150;
4th error detector 144, it is connected to the output of secondary signal path, obtains the 4th error signal for the output signal based on secondary signal path;
Fourth Ring road filter 145, it is connected with the 4th error detector 144, for exporting the 5th control word based on the 4th error signal;
Reference voltage generator 143, it is connected with Fourth Ring road filter and accesses secondary signal path, for based on the 5th control word to secondary signal path output reference voltage to eliminate the DC maladjustment of the signal that secondary signal path transmits.
Concrete reference voltage generator 143 accesses the position of secondary signal path between the on-position of the 4th error detector 144 and the output of the second amplifier 141.
Further, modulus direct current is eliminated feedback module 140 and is also comprised the 3rd amplifier 142, it is connected between reference voltage generator 143 and secondary signal path, for amplifying the reference voltage of adjustment reference voltage generator output and the reference voltage after amplifying adjustment being outputted to secondary signal path to realize eliminating DC maladjustment.
Further, in an alternative embodiment of the invention, modulus direct current is eliminated feedback module and is also comprised DC maladjustment detector, and DC maladjustment detector for detecting in last solution tonal signal whether there is DC maladjustment, thus controls based on testing result the On/Off that modulus direct current eliminates feedback module.
In order to control system of the present invention, in an embodiment of the present invention, system also comprises digital configuration module.Numeral configuration module is connected with other all controllable component in system, for the control variables of other all controllable component in control treatment system.Comprise: the frequency paths gain of the loop filter in configurable modulus mixed carrier restorer, the rotation control word of the configuration phase circulator under manual mode, the gain of the loop filter of configurable self-adapting data feedback equalizer, the configuration of the equalizer under manual mode, configure under configurable hybrid modulus DC maladjustment under manual mode eliminates feedback module, digital loop filter wave frequency in configurable clock and data recovery module and phase gain configuration, the configuration of the interpolation device under manual mode in configurable clock and data recovery module, the configuration of the duty cycle adjustment device under manual mode in configurable clock and data recovery module.
Further, digital configuration module comprises serial data interface (representing with SPI), register file and bias generation blocks.The direct current biasing that slave part comprises and SPI configure principle and are consistent with in basic receiver.
Serial data interface, for communicating with external digital processing section, control signal is write internal register stack, the input of described serial data interface is external clock CLK, external status upset clock sclk, outside chip selection signal SCS and external series input data SDI, and the first output of described serial data interface is serial data output terminal SDO.Second output of serial data interface is connected to the input of register file, for the numerical value that the register in control register heap stores.
Register file, the all configurable variablees of modulus mixing base band for 60GHz millimeter wave high-speed communication system provide control, comprise: the frequency paths gain of the loop filter in configurable modulus mixed carrier restorer, the rotation control word of the configuration phase circulator under manual mode, the gain of the loop filter of configurable self-adapting data feedback equalizer, the configuration of the equalizer under manual mode, configure under configurable hybrid modulus DC maladjustment under manual mode eliminates feedback module, digital loop filter wave frequency in configurable clock and data recovery module and phase gain configuration, the configuration of the interpolation device under manual mode in configurable clock and data recovery module, the configuration of the duty cycle adjustment device under manual mode in configurable clock and data recovery module.The input of described register file is connected with the output of serial data interface, and the output of described register file is connected with the control end of configurable variable.
Bias generation blocks, for the modulus mixing base band being applied to 60GHz millimeter wave high-speed communication system provides required bias voltage and bias current.
In order to reduce system bulk, in an embodiment of the present invention, system adopts circuit of single-chip integrated structure.
The present invention adopts circuit of single-chip integrated technology to realize being applied to the modulus mixing base band of 60GHz millimeter-wave communication system.Compared with prior art, owing to adopting circuit of single-chip integrated technology, the size of system of the present invention is little and cost is low; In addition, system of the present invention can be configured many system indexs wherein, and the DC maladjustment under the gain in the frequency integrator path of carrier auxiliary, manual mode under the loop gain of carrier wave recovery configuring, data feedback equalizer, manual mode under data feedback equalizer, manual mode is configured to and the frequency integrator path gain in clock and data recovery and the configuration of the clock and data recovery under manual mode; Meanwhile, owing to have employed hybrid baseband design way, system according to the present invention simplifies the baseband design of receiver and saves power consumption.
Although execution mode disclosed in this invention is as above, the execution mode that described content just adopts for the ease of understanding the present invention, and be not used to limit the present invention.Method of the present invention also can have other various embodiments.When not deviating from essence of the present invention, those of ordinary skill in the art are when making various corresponding change or distortion according to the present invention, but these change accordingly or are out of shape the protection range that all should belong to claim of the present invention.
Claims (10)
1. for a mixing baseband system for high-speed communication, it is characterized in that, described system comprises module carrier and recovers module, data feedback balance module and clock and data recovery module, wherein:
Described module carrier recovers module and comprises phase rotation device, it is connected to the output of high-speed communication system, described phase rotation device is for rotating the phase place of input signal, and described module carrier recovers module for the signal that receives high-speed communication system demodulation and get off and eliminates the impact of carrier deviation on described signal by the phase place recovering transmitter;
Described data feedback balance module is connected to described module carrier and recovers module, recovers the signal of module output thus the impact of reduction intersymbol interference, and then increase signal to noise ratio for the described module carrier of equilibrium;
Described clock and data recovery model calling is to described data feedback balance module, and the signal that data feedback balance module exports for recovered clock and described in demodulation is to obtain and to export last solution tonal signal.
2. the system as claimed in claim 1, is characterized in that, described module carrier recovers module and also comprises the first error detector and first ring path filter, wherein:
Described first error detector is connected in the output of described clock and data recovery module, for detecting described last solution tonal signal thus obtaining the first error signal;
Described first ring path filter is connected with described first error detector, and described first ring path filter exports the first control word for controlling described phase rotation device based on described error signal;
Described phase rotation device is connected with described first ring path filter, and described phase rotation device exports after input signal being rotated corresponding phase place under the control of described first control word.
3. system as claimed in claim 1 or 2, it is characterized in that, described data feedback balance module comprises the first amplifier for amplifying signal and the first signal path for signal transmission, wherein:
The output that input and the described module carrier of described first amplifier recover module is connected;
The input of described first signal path is connected with the output of described first amplifier, and the output of described first signal path is the output of described data feedback balance module.
4. system as claimed in claim 3, it is characterized in that, described data feedback balance module also comprises data feedback equalizer, and described data feedback equalizer comprises:
Second error detector, it is connected with the output of described clock and data recovery module, for detecting described last solution tonal signal thus obtaining the second error signal;
Data sampler, it is connected to described first signal path, for gathering analog signal that described first signal path transmits and the described analog signal collected being converted to digital sampled signal;
Second loop filter, it is connected with described second error detector and described data sampler, for exporting the second control word based on described second error signal and described digital sampled signal;
First euqalizing current source branch road, its be connected with described second loop filter and be connected to described data sampler access point and described first amplifier on described first signal path export between position, for the signal data described first signal path transmitted to the first branch current that described first signal path exports specific size and Orientation with equilibrium based on described second control word.
5. system as claimed in claim 4, it is characterized in that, described data feedback balance module also comprises tail equalizer, and described tail equalizer comprises:
3rd error detector, it is connected on the position after the access point of described first euqalizing current source branch road on described first signal path, for detecting signal thus acquisition the 3rd error signal that described first signal path transmits;
Three links theory filter, it is connected with described 3rd error detector, for exporting the 3rd control word based on described 3rd error signal;
Shift register array, it is connected with described clock and data recovery module, for carrying out time delay displacement to the data demodulated;
Second euqalizing current source branch road, it is connected with described Three links theory filter and described shift register array and is connected to the position on described first signal path between described 3rd error detector and described first euqalizing current source branch road access point, for the signal data described first signal path transmitted to the second branch current that described first signal path exports specific size and Orientation with equilibrium based on the output of described 3rd control word and described shift register array.
6. the system according to any one of claim 1-5, is characterized in that, described clock and data recovery module comprises:
Lead-lag phase discriminator, it is connected with the output of described clock and data recovery module, for analyzing described last solution tonal signal thus obtaining lead-lag signal;
Fourth Ring road filter, it is connected with described lead-lag phase discriminator, for exporting the 4th control word based on described lead-lag signal;
Phase interpolator, it is connected with described Fourth Ring road filter and is connected to described high-speed communication system, for obtaining the fractional frequency signal of described high-speed communication system and entering horizontal phasing control according to described 4th control word to described fractional frequency signal;
Clock shaping buffer, it is connected with described phase interpolator, for obtaining according to the described fractional frequency signal adjusted through phase place and exporting corresponding square wave clock;
Duty ratio adjuster, it is connected with described clock shaping buffer, for exporting corresponding sampling clock according to described square wave clock;
Sampling output unit, it comprises signal input part, signal output part and control end, wherein, described control end is connected with described duty ratio adjuster, described signal input part and described signal output part are respectively input and the output of described clock and data recovery module, and described sampling output unit is used for sampling to input signal based on described sampling clock thus obtaining described last solution tonal signal.
7. the system according to any one of claim 1-6, it is characterized in that, described system also comprises modulus direct current and eliminates feedback module, described modulus direct current is eliminated feedback module and is arranged between described data feedback balance module and described clock and data recovery module, for eliminating the DC maladjustment of the signal that described data feedback balance module exports.
8. system as claimed in claim 7, is characterized in that, described modulus direct current is eliminated feedback module and comprised:
Second amplifier, its input is connected to the output of described data feedback balance module;
Secondary signal path, its input is connected to the output of described second amplifier, and output is connected to the input of described clock and data recovery module;
4th error detector, it is connected to the output of described secondary signal path, obtains the 4th error signal for the output signal based on described secondary signal path;
Fourth Ring road filter, it is connected with described 4th error detector, for exporting the 5th control word based on described 4th error signal;
Reference voltage generator, it is connected with described Fourth Ring road filter and accesses described secondary signal path, for based on described 5th control word to described secondary signal path output reference voltage to eliminate the DC maladjustment of the signal that described secondary signal path transmits.
9. system as claimed in claim 8, it is characterized in that, described modulus direct current is eliminated feedback module and is also comprised the 3rd amplifier, it is connected between described reference voltage generator and described secondary signal path, for amplifying the described reference voltage of the described reference voltage generator output of adjustment and the described reference voltage after amplifying adjustment being outputted to described secondary signal path to realize eliminating DC maladjustment.
10. system as claimed in any one of claims 7-9, it is characterized in that, described modulus direct current is eliminated feedback module and is also comprised DC maladjustment detector, described DC maladjustment detector for detecting in described last solution tonal signal whether there is DC maladjustment, thus controls based on testing result the On/Off that described modulus direct current eliminates feedback module.
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