CN105530213B - A kind of mixing baseband system for high-speed communication - Google Patents
A kind of mixing baseband system for high-speed communication Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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Abstract
The invention discloses a kind of mixing baseband systems for high-speed communication, include: the module carrier recovery module comprising phase rotation device, its output for being connected to high-speed communication system, the module carrier recovery module are used to receive the signal that high-speed communication system demodulates and the phase by restoring transmitter to eliminate influence of the carrier deviation to the signal；Data feedback balance module is connected to the module carrier recovery module, and the signal for the balanced module carrier recovery module output increases signal-to-noise ratio to reduce the influence of intersymbol interference；Clock and data recovery module is connected to the data feedback balance module, for recovered clock and demodulate data feedback balance module output signal to obtain and export final demodulated signal.Compared with prior art, system of the invention simplifies the baseband design of receiver under the premise of guaranteeing process of signal transmission precision and accuracy and has saved power consumption.
Description
Technical field
The present invention relates to the communications fields, in particular relate to a kind of mixing baseband system for high-speed communication.
Background technique
With the continuous development of the communication technology, 60GHz millimeter wave high-speed communication system is proposed in the prior art.
The standard of 60GHz millimeter wave high-speed communication system relative to the channel width that traditional communication occupies be up to 7GHz or
Person is bigger (for example the frequency range for exempting from license is 57GHz to 64GHz by the U.S.), to provide for superfast traffic rate
Possibility.The rate of current 60GHz millimetre-wave attenuator can reach Gbps, and 802.11n standard and no-load communication techniques
(Ultra Wideband, UWB) can only realize 600Mbps and 480Mbps.
Relative to traditional communication standards, the communication system of 60GHz frequency range has many good qualities.Firstly, since 60GHz
The directionality of frequency range wireless signal is very strong, so that the signal of communication of the 60GHz communication system on different directions interferes with each other very little；
In addition to this, the carrier wave for the wireless communication standard being currently known all is far smaller than 60GHz, the communication system from other communication systems
Interfered between system also therefore very little, almost ignore.Secondly, loss of the signal on 60GHz on free space is very big, reach
15dB/km, and barrier is also very big to the Attenuation of 60GHz, and therefore, the short-distance wireless communication on 60GHz has
Inherent advantage on high security.Again, the communication system of the 60GHz of integrated circuit monolithic design is relative to traditional communication
The component size of standard requirements is smaller, so as to reduce cost.
60GHz millimeter-wave communication system is in burning hot research at present, existing standard also disunity, including
Ieee standard tissue release 802.11ad, by the establishments such as LG and Panasonic WirlessHD working group release
The WirelessHD1.1 and WiGig1.0 formulated by the WiGig alliance that Intel and Nokia etc. is formed.A variety of skimble-scamble systems
Formula standard is difficult to realize compatible matching between resulting in different system architectures.
In addition, the framework that more 60GHz millimeter-wave communication system design uses at present is still traditional transceiver mode,
This mode usually separately designs radio-frequency front-end, Analog Baseband and digital baseband, therefore causes analog baseband circuitry and number
An analog-digital converter ADC is needed between baseband circuit.Since the communication data rate of 60GHz millimetre-wave attenuator is very high, relatively
The ADC performance that should be required is very high, to cause ADC design difficulty and power consumption often very big.In addition to this, due to being up to Gbps number
According to the communication of rate, the reversal rate of digital baseband circuit will quickly, cause the power consumption of digital baseband circuit also very big.
Therefore, 60GHz millimeter-wave communication system in the prior art there are aiming at the problem that, need a kind of new for high speed
The mixing baseband system of communication.
Summary of the invention
60GHz millimeter-wave communication system in the prior art there are aiming at the problem that, the present invention provides one kind for high speed
The mixing baseband system of communication, the system include module carrier recovery module, data feedback balance module and clock sum number
According to recovery module, in which:
The module carrier recovery module includes phase rotation device, is connected to the output of high-speed communication system, the phase
Position rotator is used to rotate the phase of input signal, and the module carrier recovery module is for receiving under high-speed communication system demodulation
Next signal simultaneously eliminates influence of the carrier deviation to the signal by the phase of recovery transmitter；
The data feedback balance module is connected to the module carrier recovery module, extensive for the balanced module carrier
The signal of multiple module output increases signal-to-noise ratio to reduce the influence of intersymbol interference；
The clock and data recovery module is connected to the data feedback balance module, for recovered clock and demodulates institute
The signal of data feedback balance module output is stated to obtain and export final demodulated signal.
In one embodiment, the module carrier recovery module also includes first error detector and the first loop filtering
Device, in which:
The first error detector is connected in the output of the clock and data recovery module, for detect it is described most
Whole demodulated signal is to obtain first error signal；
First loop filter is connected with the first error detector, and first loop filter is based on described
Error signal exports the first control word for controlling the phase rotation device；
The phase rotation device is connected with first loop filter, and the phase rotation device is in first control word
Control under input signal is rotated into corresponding phase after export.
In one embodiment, the data feedback balance module includes the first amplifier for amplified signal and is used for
Transmit the first signal path of signal, in which:
The input of first amplifier is connected with the output of the module carrier recovery module；
The input of first signal path is connected with the output of first amplifier, first signal path it is defeated
It is out the output of the data feedback balance module.
In one embodiment, the data feedback balance module also includes data feedback balanced device, and the data feedback is equal
Weighing apparatus includes:
Second error detector is connected with the output of the clock and data recovery module, described final for detecting
Demodulated signal is to obtain the second error signal；
Data sampler is connected to first signal path, transmits on first signal path for acquiring
The collected analog signal is simultaneously converted to digital sampled signal by analog signal；
Second loop filter is connected, for being based on second error detector and the data sampler
Second error signal and the digital sampled signal export the second control word；
First euqalizing current source branch is connected with second loop filter and is connected to first signal path
Position between the upper data sampler access point and first amplifier output, for based on second control word to
The first branch electric current in the first signal path output particular size and direction on balanced first signal path to transmit
Signal data.
In one embodiment, the data feedback balance module also includes tail balanced device, and the tail balanced device includes:
Third error detector is connected to the access of first euqalizing current source branch on first signal path
On position after point, third error signal is obtained for detecting the signal transmitted on first signal path；
Third loop filter is connected with the third error detector, for defeated based on the third error signal
Third control word out；
Shift register array is connected with the clock and data recovery module, for carrying out to the data demodulated
Delay displacement；
Second euqalizing current source branch, is connected simultaneously with the third loop filter and the shift register array
It is connected on first signal path between the third error detector and first euqalizing current source branch access point
Position, it is defeated to first signal path for the output based on the third control word and the shift register array
Signal data of the second branch electric current in particular size and direction to be transmitted on balanced first signal path out.
In one embodiment, the clock and data recovery module includes:
Lead-lag phase discriminator is connected with the output of the clock and data recovery module, described final for analyzing
Demodulated signal is to obtain lead-lag signal；
Fourth Ring path filter is connected with the lead-lag phase discriminator, for defeated based on the lead-lag signal
4th control word out；
Phase interpolator is connected with Fourth Ring path filter and is connected to the high-speed communication system, for obtaining
It takes the fractional frequency signal of the high-speed communication system and phase adjustment is carried out to the fractional frequency signal according to the 4th control word；
Clock shaping buffer, is connected with the phase interpolator, for according to the frequency dividing Jing Guo phase adjustment
Signal acquisition simultaneously exports corresponding square wave clock；
Duty ratio adjuster is connected with the clock shaping buffer, for being answered according to the square wave clock output phase
Sampling clock；
Sample output unit, it includes signal input part, signal output end and control terminals, wherein the control terminal with
The duty ratio adjuster is connected, and the signal input part and the signal output end are respectively the clock and data recovery
The input and output of module, the sampling output unit be used for based on the sampling clock to input signal carry out sampling to
Obtain the final demodulated signal.
In one embodiment, the system also includes that modulus direct current eliminates feedback module, and the modulus direct current eliminates feedback
Module is mounted between the data feedback balance module and the clock and data recovery module, for eliminating the data
The DC maladjustment of the signal of feedback equalization module output.
In one embodiment, the modulus direct current elimination feedback module includes:
Second amplifier, input terminal are connected to the output of the data feedback balance module；
Second signal access, input terminal are connected to the output of second amplifier, and output end is connected to the clock
With the input of data recovery module；
4th error detector is connected to the output of the second signal access, for logical based on the second signal
The output signal on road obtains the 4th error signal；
Fourth Ring path filter is connected with the 4th error detector, for defeated based on the 4th error signal
5th control word out；
Reference voltage generator is connected with Fourth Ring path filter and accesses the second signal access, is used for
It is eliminated based on the 5th control word to the second signal access output reference voltage and is transmitted on the second signal access
Signal DC maladjustment.
In one embodiment, it further includes third amplifier that the modulus direct current, which eliminates feedback module, is connected to the ginseng
It examines between voltage generator and the second signal access, is adjusted described in the reference voltage generator output for amplifying
Reference voltage simultaneously will amplify the reference voltage output adjusted to the second signal access to realize elimination DC maladjustment.
In one embodiment, it further includes DC maladjustment detector that the modulus direct current, which eliminates feedback module, and the direct current loses
Adjust detector for detecting with the presence or absence of DC maladjustment in the final demodulated signal, to control the mould based on testing result
Number direct current eliminates unlatching/closing of feedback module.
Compared with prior art, system of the invention letter under the premise of guaranteeing process of signal transmission precision and accuracy
Change the baseband design of receiver and saves power consumption.
Other feature or advantage of the invention will illustrate in the following description.Also, Partial Feature of the invention or
Advantage will be become apparent by specification, or be appreciated that by implementing the present invention.The purpose of the present invention and part
Advantage can be realized or be obtained by step specifically noted in the specification, claims and drawings.
Detailed description of the invention
Attached drawing is used to provide further understanding of the present invention, and constitutes part of specification, with reality of the invention
It applies example and is used together to explain the present invention, be not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is an embodiment system structure schematic diagram according to the present invention.
Specific embodiment
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and examples, implementation personnel of the invention whereby
Can fully understand that how the invention applies technical means to solve technical problems, and reach technical effect realization process and according to
The present invention is embodied according to above-mentioned realization process.As long as each embodiment it should be noted that do not constitute conflict, in the present invention
And each feature in each embodiment can be combined with each other, be formed by technical solution protection scope of the present invention it
It is interior.
60GHz millimeter-wave communication system is in burning hot research at present, existing standard also disunity, it is a variety of not
Unified standard is difficult to realize compatible matching between resulting in different system architectures.In addition, current more 60GHz millimeter wave
The framework that Communication System Design uses is still traditional transceiver mode, and this mode is usually by radio-frequency front-end, Analog Baseband
It is separately designed with digital baseband, therefore causes to need an analog-digital converter between analog baseband circuitry and digital baseband circuit
ADC.Since the communication data rate of 60GHz millimetre-wave attenuator is very high, the ADC performance of corresponding requirement is very high, to cause ADC
Design difficulty and power consumption are often very big.In addition to this, due to being up to the communication of Gbps data transfer rate, the overturning speed of digital baseband circuit
Degree will quickly, cause the power consumption of digital baseband circuit also very big.
60GHz millimeter-wave communication system in the prior art there are aiming at the problem that, the invention proposes one kind for high speed
The mixing baseband system of communication.As shown in Figure 1, in an embodiment of the present invention, system include module carrier recovery module 110,
Data feedback balance module 120 and clock and data recovery module 150.
Module carrier recovery module 110 includes phase rotation device 111.It is logical that module carrier recovery module 110 is connected to high speed
The output of letter system, phase rotation device 111 are used to rotate the phase of input signal.Module carrier recovery module 110 is for receiving
Signal that high-speed communication system demodulates and the phase by restoring transmitter eliminate influence of the carrier deviation to signal.
Data feedback balance module 120 is connected to module carrier recovery module 110, for balanced modulus carrier recovery block
The signal of output increases signal-to-noise ratio to reduce the influence of intersymbol interference.
Clock and data recovery module 150 is connected to data feedback balance module 120, for recovered clock and solves adjusting data
The signal that feedback equalization module 120 exports is to obtain and export final demodulated signal.
Further, in the present embodiment, data feedback balance module 120, module carrier recovery module 110 and clock and
Data recovery module 150 is configurable adaptation module.Radiofrequency signal passes through the quadrature phase shift keying of high-speed communication system
It is input in configurable module carrier recovery module 110 after (Quadrature Phase Shift Keyin, QPSK) demodulator
Phase rotation device 111, the signal that the rotation input of phase rotation device 111 is come in, so that its output signal is no longer because of carrier wave phase
Position and frequency are inconsistent and bring deteriorates.111 output signal of phase rotation device gives data feedback balance module 120, the portion
Point reduce because intersymbol interference caused by the reasons such as channel or coding and caused by signal-to-noise ratio deterioration.Data feedback balance module
120 output signal to the sampling output par, c of clock and data recovery module 150.
In the present embodiment, the use of data feedback balance module 120 is time variation and unpredictability because of channel.
The adaptive equalization process of data feedback balance module 120 is exactly adjustment loop filter coefficient, so that balanced output signal is same
The mean square error of error between ideal output reaches minimum, and the mode for adjusting filter coefficient is towards mean square error spherical surface
Steepest descent direction carry out progressive alternate, finally reach least mean-square error.And the step-length namely loop filter adjusted
The same convergence rate of gain, system stability, input signal-to-noise ratio, final convergence error have much relations, so originally stating invention
Flexible choice step-length can be restrained by way of configuring, to select optimal result in above-mentioned compromise.
In order to reduce output error, in the present embodiment, module carrier recovery module 110 also includes first error detector
112 and first loop filter 113, in which: first error detector 112 is connected to clock and data recovery module 150
It exports in (the last output of system), obtains first error signal for detecting final demodulated signal；First loop filtering
Device 113 is connected with first error detector 112, the error that the first loop filter 113 is exported based on first error detector 112
Signal exports the first control word for controlling phase rotation device 111；Phase rotation device 111 and 113 phase of the first loop filter
Even, phase rotation device 111 exports after input signal is rotated corresponding phase under the control of the first control word.
Module carrier recovery module 110 mainly solve due to transmitter and receiver local oscillator because frequency drift and phase not
Signal distortion caused by consistent.In the present embodiment, the quadrature phase shift keying (Quadrature being directed on 60GHz
Phase Shift Keyin, QPSK) modulation system.The signal that configurable module carrier recovery module 110 receives can be used down
Formula indicates:
In formula 1:
T is time variable；
X is the signal transient phase that phase rotation device 111 is input to after being interfered；
Δ f andRespectively indicate existing frequency difference and initial phase difference between Receiver And Transmitter；
I and Q is the input orthogonal signalling before being interfered；
I (in) and Q (in) is the signal that phase rotation device 111 is input to after being interfered；
Amp indicates the signal transient amplitude that phase rotation device 111 is input to after being interfered.
By formula 1 it can be seen that, when input I/Q by Δ f andAfter interference, the input letter of phase rotation device 111 is entered
Number I (in) and Q (in) just will appear distortion in amplitude.Signal can use following formula table after rotating by phase rotation device 111
Show:
In formula 2:
I (out) and Q (out) is the signal that phase rotation device 111 exports；
Y is the rotation angle of phase rotation device.
From formula 2, it can be seen that, the phase of orthogonal signalling is compensated compared in original signal after rotation, when compensation rate is same
Output signal is equally distorted in amplitude when input difference is inconsistent, and the signal of this distortion can make first error detect
Device 112 detects that error supplies the first loop filter 113 and uses, the loop when the amount of compensation is identical with deviation caused by local oscillator
Lock state will be entered.What it is due to the change of phase rotation device 111 is phase mass, and inclined containing frequency in the departure of local oscillator
Difference will track difference, the first loop filter 113 caused by frequency difference and at least be designed as second order.When loop enters tracking lock shape
After state, initial phase difference is repaired, and existing frequency difference is also tracked in the first loop filter of second order digital 113, when per
The phase that clock period output control word rotates phase rotation device 111 is consistent with the phase as caused by frequency, to recover load
Wave.
In addition, since the gain of the lock speed and stability same frequency path of integration of loop has very big relationship, and frequently
Rate path of integration also has direct relation with the frequency departure that can be corrected, so system of the invention can pass through frequency in practice
Rate deviation range configures the gain of frequency paths, to do optimal selection in lock speed and stability function.
Data feedback balance module 120 solves simply indicate band limit by following formula because of intersymbol interference caused by channel
The sampling of the shock response of channel.
H (t)=H1(t) (t-nT) (n=1,2......) (3)+H
In formula 3: h (t) indicates total shock response of the bandwidth efficient channel in moment t.Wherein, H1(t) indicate to it is current when
Carve the response of the signal of t；H (t-nT) indicates the response (interference) generated to the signal after n sampling clock, and wherein n is integer,
T is the period of sampling clock.
It can be seen that, the signal of moment t can generate interference to the signal that next clock T is sampled from formula 3.The present embodiment
Data feedback balance module 120 be exactly to reduce or even eliminate this interference.
In the present embodiment, data feedback balance module 120 includes the first amplifier 121 for amplified signal and uses
In the first signal path of transmission signal, in which: the input of the first amplifier 121 and the output of module carrier recovery module 110
(output of phase rotation device 111) is connected；The input of first signal path is connected with the output of the first amplifier 121, the first letter
The output of number access is the output of data feedback balance module.
Further, in the present embodiment, data feedback balance module 120 also includes data feedback balanced device 122, data
Feedback equalizer 122 is that the loss introduced to current data compensates comprising:
Second error detector 125, is connected, for detecting last solution with the output of clock and data recovery module 150
Signal is adjusted to obtain the second error signal；
Data sampler 126 is connected to the first signal path, for acquiring the simulation transmitted on the first signal path letter
Number and collected analog signal is converted into digital sampled signal；
Second loop filter 124 is connected, for being based on the second error detector 125 and data sampler 126
Second error signal and digital sampled signal export the second control word；
First euqalizing current source branch 123 is connected with the second loop filter 124 and is connected to the first signal path use
In exporting the first branch electric current in particular size and direction to the first signal path based on the second control word with balanced first signal
The signal data transmitted on access.First euqalizing current source branch 123 is data sampling in the on-position of the first signal path
Position between 126 access point of device and the output of the first amplifier 121, such data sampler 126 sample just balanced for first
Consequential signal after 123 equilibrium of current source branch.
Further, in the present embodiment, data feedback balance module 120 also includes tail balanced device 130.；Tail is equal
Weighing apparatus is that the crosstalk that the data that front has been received introduce is compensated and eliminated comprising:
Third error detector 133 is connected to the access point of the first euqalizing current source branch 123 on the first signal path
On position later, for detecting the signal transmitted on the first signal path, to obtain third error signal, (detection is the
Consequential signal after one euqalizing current source branch, 123 equilibrium)；
Third loop filter 132 is connected with third error detector 133, for being exported based on third error signal
Third control word；
Shift register array 134 is connected with clock and data recovery module 150, for the data demodulated into
Line delay displacement；
Second euqalizing current source branch 131, is connected with third loop filter 132 and shift register array 134
And it is connected to the position on the first signal path between 123 access point of third error detector 133 and the first euqalizing current source branch
It sets, for the output based on third control word and shift register array, (signal of shift register array output is demodulation
The signal that data out obtain after being delayed) to the first signal path export the second branch electric current in particular size and direction with
The signal data transmitted on balanced first signal path.
Specifically, the output of third control word and shift register array 134 that third loop filter 132 exports is common
The euqalizing current branch on corresponding position is controlled, number and the direction of its opening are controlled, thus balanced current data.
In the present embodiment, the effect of clock and data recovery module 150 be recovered from the data of input clock and
Final digital signal output is completed, clock and data recovery module 150 is mainly by adjusting main phaselocked loop frequency divider output letter
Number phase has finally adjusted duty ratio by clock shaping buffer to realize the recovery of clock again.And to output signal of frequency divider
Phase-adjusted realization be to be realized by quadrature phase interpolation device, principle can be explained by following formula.
In formula 4:
OUTI and OUTQ indicates the output after adjusting；
CLKI and CLKQ indicates the quadrature divider output of main phaselocked loop；
The output control word of IA, IB, IC, ID for loop filter；
α 1=IA-IB, α 2=IC-ID respectively represent the opposite amplification factor of CLKI and CLKQ signal.
The phase of output clock can be changed by adjusting output control word.Input signal by CLKI rising edge and
Failing edge clock and CLKQ rising edge sample feeding lead-lag phase discriminator respectively and identify lead-lag information, then this
Information is sent into loop filter, and control digital loop filters update the size and Orientation of output control word.
It is consistent with carrier auxiliary, since the recovery of clock will also recover clock necessary not only for moderate phase is recovered
Difference on the frequency between data, the present embodiment use the drift of a second order digital loop filter tracking frequency.In addition, by
Exist between the same lock speed of frequency integrator loop gain of secondary loop filter, locking deviation range and loop stability
Much relations, so the present invention, which can according to need, carries out optimal manual configuration.Lead to again by the signal that phase interpolator exports
Oversampling clock shaping buffer becomes the output signal of the full amplitude of oscillation, finally by becoming adopting for 50% duty ratio after having adjusted duty ratio
Sample clock.
The principle of dutyfactor adjustment circuit is summarized as follows: the DC level of signal of the duty less than 50% is less than full amplitude of oscillation electricity
Flat half, and the difference other end is naturally larger than full amplitude of oscillation level half, and the direct current of differential clocks is taken out by single order RC filter
, the difference of the two is compared by a comparator, duty cycle adjustment device-phase inverter common mode electrical level is then adjusted, thus most
Making the duty ratio for exporting clock eventually is 50%.
Specifically, clock and data recovery module 150 include lead-lag phase discriminator 152, Fourth Ring path filter 153,
Phase interpolator 154, clock shaping buffer 155, duty ratio adjuster 156 and sampling output unit 151.
Lead-lag phase discriminator 152 (lead-lag phase-shift discriminator (Bang Bang PD)) and clock and data recovery mould
The output of block 150 is connected, and obtains lead-lag signal for analyzing final demodulated signal.
Fourth Ring path filter 153 is connected with lead-lag phase discriminator 152, for based on lead-lag signal output the
Four control words.
Phase interpolator 154 is connected with Fourth Ring path filter 153 and is connected to high-speed communication system, for obtaining high speed
The fractional frequency signal of communication system simultaneously carries out phase adjustment to fractional frequency signal according to the 4th control word.
Clock shaping buffer 155 is (when current forms latch type clock is to complementary bipolar transistor type (CMOS)
Clock shaping buffer (buffer)) it is connected with phase interpolator 154, for being obtained simultaneously according to the fractional frequency signal Jing Guo phase adjustment
Export corresponding square wave clock；
Duty ratio adjuster 156 is connected with clock shaping buffer 155, for being exported according to clock shaping buffer 155
Square wave clock export corresponding sampling clock.
Sampling output unit 151 includes signal input part, signal output end and control terminal, wherein sampling output unit
151 control terminal is connected with duty ratio adjuster 156, and signal input part and signal output end are respectively clock and data recovery
The input and output of module 150, sampling output unit 151 are used to sample obtaining to input signal based on sampling clock
Take final demodulated signal.
Specifically, duty cycle adjustment device 156 itself is by two identical phase inverters, capacitance, direct current biasing resistance, difference
Single order RC filter, error comparator and bias voltage generator and digital control module is divided to constitute.Clock shaping buffering
The difference output of device 155 passes through the input terminal that capacitance is sent to two identical phase inverters respectively, duty cycle adjustment device 156
On the one hand the output of one phase inverter is sent to sampling output unit 151 as aforementioned, be on the other hand sent to difference single order RC filter respectively
Wave device.Difference single order RC filter retains the respective flip-flop of difference after filtering out high fdrequency component.Two flip-flop signals point
It is not connected to the both ends of comparator, the output signal of comparator gives control module, and control module exports control word and controls biased electrical
Pressure generator generates the bias voltage of corresponding difference, and differential bias voltage passes through biasing resistor respectively and is added to both direction device
Input terminal adjusts respective dc point.
Further, in the present embodiment, system also includes that modulus direct current eliminates feedback module 140.Modulus direct current is eliminated
Feedback module 140 is mounted between data feedback balance module 120 and clock and data recovery module 150, for eliminating
State the DC maladjustment of the signal of data feedback balance module output.
In the present embodiment, data feedback balance module 120 outputs signal to modulus direct current and eliminates feedback module 140.Mould
Number direct currents eliminate feedback modules 140 eliminate the DC maladjustments as caused by prime and the same level, then export adjusting after signal to when
Clock and data recovery module 150.Clock and data recovery module 150 is using the clock sampling data that this part recovers to extensive
It appears again data.
It is to assist amplifying unit by increasing that modulus direct current, which eliminates feedback module 140 and solves the mode of DC maladjustment, auxiliary
The output of amplifying unit is helped to be connected together with the output of main amplifying unit.The DC error that prime accumulation and the same level introduce is ok
The DC maladjustment of the equivalent output in main amplifier passes through sampler samples master when being originally inputted end not input signal in base band
The output of amplifier approaches the output of main amplifier by constantly adjusting the input difference bias voltage of booster amplifier
With zero, to finally eliminate prime accumulation and the same level causes DC maladjustment.
Specifically, in the present embodiment, modulus direct current eliminates feedback module 140 and includes:
Second amplifier 141, input terminal be connected to data feedback balance module 150 output (the first signal path
Output end)；
Second signal access, input terminal are connected to the output of the second amplifier 141, and output end is connected to clock and data
The input of recovery module 150；
4th error detector 144 is connected to the output of second signal access, for based on the defeated of second signal access
The 4th error signal of signal acquisition out；
Fourth Ring path filter 145 is connected with the 4th error detector 144, for being exported based on the 4th error signal
5th control word；
Reference voltage generator 143 is connected with Fourth Ring path filter and accesses second signal access, for based on the
Five control words eliminate the DC maladjustment of the signal transmitted on second signal access to second signal access output reference voltage.
Specific reference voltage generator 143 accesses position the connecing in the 4th error detector 144 of second signal access
Enter between position and the output of the second amplifier 141.
Further, it further includes third amplifier 142 that modulus direct current, which eliminates feedback module 140, is connected to reference voltage
Between generator 143 and second signal access, for amplifying the reference voltage of adjustment reference voltage generator output and will put
Big reference voltage output adjusted realizes elimination DC maladjustment to second signal access.
Further, in an alternative embodiment of the invention, it further includes DC maladjustment detection that modulus direct current, which eliminates feedback module,
Device, DC maladjustment detector is for detecting with the presence or absence of DC maladjustment in final demodulated signal, to be controlled based on testing result
Unlatching/closing of modulus direct current elimination feedback module.
In order to control system of the invention, in an embodiment of the present invention, system further includes digital configuration module.Number is matched
It sets module to be connected with all controllable components of other in system, the control for controlling all controllable components of other in processing system becomes
Amount.It include: the configuration under the frequency paths gain of the loop filter in configurable modulus mixed carrier restorer, manual mode
The rotation control word of phase rotation device, the gain of the loop filter of configurable self-adapting data feedback equalizer, manual mode
Under the configuration of balanced device, the configurable hybrid modulus DC maladjustment under manual mode eliminate configuration under feedback module, configurable
The frequency of digital loop filtering in clock and data recovery module and phase gain configuration, can configure under manual mode clock and
It can configure the duty cycle adjustment in clock and data recovery module under the configuration of interpolation device in data recovery module, manual mode
The configuration of device.
Further, digital configuration module includes that serial data interface (being indicated with SPI), register file and biasing generate
Module.Direct current biasing and SPI that slave part includes configuration principle in basic receiver the same as being consistent.
For handling section communication with external digital internal register stack, institute is written in control signal by serial data interface
State serial data interface input terminal be external clock CLK, external status overturn clock sclk, external chip select signal SCS and
External series input data SDI, the first output end of the serial data interface are serial data output terminal SDO.Serial data
The second output terminal of interface is connected to the input of register file, for controlling the numerical value of the storage of the register in register file.
Register file, all configurable variables of modulus mixed base band for 60GHz millimeter wave high-speed communication system provide
Control, comprising: matching under the frequency paths gain of the loop filter in configurable modulus mixed carrier restorer, manual mode
Set the rotation control word of phase rotation device, the gain of the loop filter of configurable self-adapting data feedback equalizer, manual mould
Configurable hybrid modulus DC maladjustment under the configuration of balanced device under formula, manual mode is eliminated configuration under feedback module, can be matched
The frequency and phase gain for setting the digital loop filtering in clock and data recovery module configure, can configure clock under manual mode
It can configure the duty ratio tune in clock and data recovery module under configuration, manual mode with the interpolation device in data recovery module
Save the configuration of device.The input of the register file is connected with the output end of serial data interface, the output of the register file
End is connected with the control terminal of configurable variable.
Bias generation blocks provide required for the modulus mixed base band applied to 60GHz millimeter wave high-speed communication system
Bias voltage and bias current.
In order to reduce system bulk, in an embodiment of the present invention, system is constructed using circuit of single-chip integrated.
The present invention realizes the modulus mixed base for being applied to 60GHz millimeter-wave communication system using circuit of single-chip integrated technology
Band.Compared with prior art, due to using circuit of single-chip integrated technology, the size of system of the invention is small and at low cost；
In addition, system of the invention can configure many of these system indexs, the increasing in the frequency integrator path of carrier auxiliary
Benefit, data feedback balanced device under carrier wave recovery configuring, the loop gain of data feedback balanced device, manual mode under manual mode,
Under DC maladjustment configuration under manual mode and the frequency integrator path gain and manual mode in clock and data recovery
Clock and data recovery configuration；Simultaneously as using hybrid baseband design method, the system according to the present invention simplifies reception
The baseband design of machine simultaneously saves power consumption.
While it is disclosed that embodiment content as above but described only to facilitate understanding the present invention and adopting
Embodiment is not intended to limit the invention.Method of the present invention can also have other various embodiments.Without departing substantially from
In the case where essence of the present invention, those skilled in the art make various corresponding changes or change in accordance with the present invention
Shape, but these corresponding changes or deformation all should belong to scope of protection of the claims of the invention.
Claims (9)
1. a kind of mixing baseband system for high-speed communication, which is characterized in that the system include module carrier recovery module,
Data feedback balance module and clock and data recovery module, in which:
The module carrier recovery module includes phase rotation device, is connected to the output of high-speed communication system, the phase rotation
Turn device for rotating the phase of input signal, the module carrier recovery module is for receiving what high-speed communication system demodulated
Signal simultaneously eliminates influence of the carrier deviation to the signal by the phase of recovery transmitter；
The data feedback balance module is connected to the module carrier recovery module, restores mould for the balanced module carrier
The signal of block output increases signal-to-noise ratio to reduce the influence of intersymbol interference；
The clock and data recovery module is connected to the data feedback balance module, for recovered clock and demodulates the number
According to the signal of feedback equalization module output to obtain and export final demodulated signal；
Wherein, the system also includes that modulus direct current eliminates feedback module, and the modulus direct current eliminates feedback module and is mounted on institute
It states between data feedback balance module and the clock and data recovery module, for eliminating the data feedback balance module
The DC maladjustment of the signal of output.
2. the system as claimed in claim 1, which is characterized in that the module carrier recovery module also includes first error detection
Device and the first loop filter, in which:
The first error detector is connected in the output of the clock and data recovery module, for detecting the last solution
Adjust signal to obtain first error signal；
First loop filter is connected with the first error detector, and first loop filter is based on the error
Signal exports the first control word for controlling the phase rotation device；
The phase rotation device is connected with first loop filter, control of the phase rotation device in first control word
It is exported after input signal is rotated corresponding phase under system.
3. the system as claimed in claim 1, which is characterized in that the data feedback balance module includes for amplified signal
First amplifier and the first signal path for being used for transmission signal, in which:
The input of first amplifier is connected with the output of the module carrier recovery module；
The input of first signal path is connected with the output of first amplifier, and the output of first signal path is
The output of the data feedback balance module.
4. system as claimed in claim 3, which is characterized in that the data feedback balance module also includes data feedback equilibrium
Device, the data feedback balanced device include:
Second error detector is connected with the output of the clock and data recovery module, for detecting the final demodulation
Signal is to obtain the second error signal；
Data sampler is connected to first signal path, for acquiring the simulation transmitted on first signal path
The collected analog signal is simultaneously converted to digital sampled signal by signal；
Second loop filter is connected with second error detector and the data sampler, for based on described
Second error signal and the digital sampled signal export the second control word；
First euqalizing current source branch is connected with second loop filter and is connected to institute on first signal path
State the position between data sampler access point and first amplifier output, for based on second control word to described
Letter of the first branch electric current in the first signal path output particular size and direction to be transmitted on balanced first signal path
Number.
5. system as claimed in claim 4, which is characterized in that the data feedback balance module also includes tail balanced device,
The tail balanced device includes:
Third error detector, be connected to first euqalizing current source branch on first signal path access point it
On position afterwards, third error signal is obtained for detecting the signal transmitted on first signal path；
Third loop filter is connected with the third error detector, for based on third error signal output the
Three control words；
Shift register array is connected with the clock and data recovery module, for being delayed to the data demodulated
Displacement；
Second euqalizing current source branch is connected and connect with the third loop filter and the shift register array
Position on to first signal path between the third error detector and first euqalizing current source branch access point
It sets, exports spy to first signal path for the output based on the third control word and the shift register array
The signal data for determining the second branch electric current of size and Orientation to transmit on balanced first signal path.
6. system according to any one of claims 1 to 5, which is characterized in that the clock and data recovery module includes:
Lead-lag phase discriminator is connected with the output of the clock and data recovery module, for analyzing the final demodulation
Signal is to obtain lead-lag signal；
Fourth Ring path filter is connected with the lead-lag phase discriminator, for based on lead-lag signal output the
Four control words；
Phase interpolator is connected with Fourth Ring path filter and is connected to the high-speed communication system, for obtaining
It states the fractional frequency signal of high-speed communication system and phase adjustment is carried out to the fractional frequency signal according to the 4th control word；
Clock shaping buffer, is connected with the phase interpolator, for according to the fractional frequency signal Jing Guo phase adjustment
It obtains and exports corresponding square wave clock；
Duty ratio adjuster is connected with the clock shaping buffer, for being adopted accordingly according to square wave clock output
Sample clock；
Sample output unit, it includes signal input part, signal output end and control terminals, wherein the control terminal with it is described
Duty ratio adjuster is connected, and the signal input part and the signal output end are respectively the clock and data recovery module
Input and output, the sampling output unit is used to sample to obtaining input signal based on the sampling clock
The final demodulated signal.
7. the system as claimed in claim 1, which is characterized in that the modulus direct current eliminates feedback module and includes:
Second amplifier, input terminal are connected to the output of the data feedback balance module；
Second signal access, input terminal are connected to the output of second amplifier, and output end is connected to the clock sum number
According to the input of recovery module；
4th error detector is connected to the output of the second signal access, for based on the second signal access
Output signal obtains the 4th error signal；
Fourth Ring path filter is connected with the 4th error detector, for based on the 4th error signal output the
Five control words；
Reference voltage generator is connected with Fourth Ring path filter and accesses the second signal access, for being based on
5th control word eliminates the letter transmitted on the second signal access to the second signal access output reference voltage
Number DC maladjustment.
8. system as claimed in claim 7, which is characterized in that it further includes third amplification that the modulus direct current, which eliminates feedback module,
Device is connected between the reference voltage generator and the second signal access, described with reference to electricity for amplifying adjustment
The reference voltage of pressure generator output simultaneously will amplify the reference voltage output adjusted to the second signal access
DC maladjustment is eliminated to realize.
9. the system as claimed in claim 1, which is characterized in that it further includes DC maladjustment that the modulus direct current, which eliminates feedback module,
Detector, the DC maladjustment detector is for detecting with the presence or absence of DC maladjustment in the final demodulated signal, to be based on
Testing result controls unlatching/closing that the modulus direct current eliminates feedback module.
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| CN108282162B (en) * | 2017-01-06 | 2021-08-31 | 联咏科技股份有限公司 | Clock and data recovery circuit with improved jitter tolerance |
| CN112241384B (en) * | 2019-07-19 | 2022-07-01 | 上海复旦微电子集团股份有限公司 | Universal high-speed serial differential signal shunt circuit and method |
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| CN1992688A (en) * | 2005-12-29 | 2007-07-04 | 广州市广晟微电子有限公司 | Method for adjusting the unbalance of I/Q amplitude in wireless transceiver system |
| CN101562591A (en) * | 2009-05-12 | 2009-10-21 | 复旦大学 | I/Q mismatch estimating and compensating method of training sequence based on phase rotation |
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| CN101146071A (en) * | 2006-09-12 | 2008-03-19 | Thomson宽带研发（北京）有限公司 | Bidirectional signal transmission device and method |
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| CN1992688A (en) * | 2005-12-29 | 2007-07-04 | 广州市广晟微电子有限公司 | Method for adjusting the unbalance of I/Q amplitude in wireless transceiver system |
| CN101562591A (en) * | 2009-05-12 | 2009-10-21 | 复旦大学 | I/Q mismatch estimating and compensating method of training sequence based on phase rotation |
| CN102726013A (en) * | 2011-03-14 | 2012-10-10 | 苏州全波通信技术有限公司 | Echo cancelling system and method for on channel repeater used for coverage gap filling |
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