CN104821871B - A kind of 16QAM demodulates synchronous method - Google Patents
A kind of 16QAM demodulates synchronous method Download PDFInfo
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Abstract
The invention provides a kind of 16QAM to demodulate synchronous method, comprises the following steps：（1）Increase power detection techniques on traditional QPSK Costas loop road, complete carrier auxiliary；（2）Carry out matched filtering respectively to inphase quadrature component signal, reduce influence of noise, prepared for bit synchronization；（3）Bit timing recovery is carried out by " door sooner or later " to inphase quadrature signal；（4）Setting thresholding is sampled judgement respectively to two paths of signals and 42 level conversions obtain parallel signal；（5）After carrying out differential decoding and parallel-serial conversion to parallel signal, primary signal is recovered.Present invention introduces Novel carrier wave simultaneous techniques, using phaselocked loop complete carrier auxiliary, on the basis of traditional Costas loop, increase power detection techniques, ensure the linear convergent rate of phase discriminator, improve tracking accuracy and speed, and verified by FPGA hardware.
Description
Technical field
The present invention relates to the communications field, specifically a kind of 16QAM demodulation synchronous method.
Background technology
In multi-system keying system, all advantageous in terms of the bandwidth and power occupancy of phase keying, i.e., bandwidth occupancy is small,
Bit signal to noise ratio requires low.MPSK(Multiple Phase Shift Keying)、MDPSK(Multiple
Differential Phase Shift Keying) there is the characteristics of permanent envelope, power efficiency is high, but secondary lobe is higher, frequency spectrum is let out
Leak larger, be also easy to produce spread spectrum, and as M increase, the distance of adjacent phase are gradually reduced, noise margin subtracts therewith
It is small, the bit error rate it is difficult to ensure that.Quadrature amplitude modulation (QAM, Quadrature Amplitude Modulation) is modern communicationses
Frequently with a kind of modulation technique in the modulation of two quadrature carriers enterprising line amplitude, it improves noises of the MPSK when M is big
Tolerance limit.16QAM is the representative signal of QAM modulation, and it has that the bit error rate is low, transmission rate is high and that band efficiency is high is excellent
Point, it can be applied to HSDPA (High Speed Downlink Packet Access), satellite communication and broadband wireless access
Deng in communication field.But because 16QAM is non-constant envelope signal, if section using traditional QPSK during carrier auxiliary
Stas ring, easily cause the defects of precision is low, tracking velocity is slow.It is in addition, soft as the FPGA instruments of core using DSP Builder
Part develops QAM modulation demodulator, though simple and easy, its stability, portability are poor, big using limitation.Because 16QAM is deposited
In 90 ° of phase fuzzy problems, if carrier wave caused by carrier auxiliary is non-with the same phase of frequency with carrier wave during modulation, decoding can be produced
Mistake.
This patent carries out 16QAM modulation using quadrature amplitude modulation method, and carries out differential coding to baseband signal before modulation,
Differential decoding is carried out after bit synchronization, the influence of phase ambiguity can be overcome.In carrier synchronization module, this patent is in traditional QPSK
COSTAS loops on the basis of, increase power detection judgement, to overcome influence of the non-permanent envelopes of 16QAM to phase discriminator.It is in place fixed
When recovery module, because the clock of transmitter and receiver can have certain phase offset and clock skew so as to cause to miss
Code, therefore the present invention uses and is based on self synchronous door algorithm sooner or later, being capable of "ball-park" estimate suitable for the system of high power sample rate
Clock skew, it is simple for structure, it is easy to FPGA hardware realization.By making rational planning for, it is well-designed, one completely comprising this new
The 16QAM modulation demodulation systems of demodulation simultaneous techniques are achieved in the large-scale F PGA chips of monolithic ALTERA companies,
And detailed test checking is carried out on development board.
The content of the invention
The present invention is improved on the basis of traditional QPSK COSTAS loops, carried to solve problem of the prior art
A kind of 16QAM demodulation synchronous method has been supplied, influence of the non-permanent envelopes of 16QAM to phase discriminator has been overcome, improves systematic function.
The invention provides a kind of 16QAM to demodulate synchronous method, comprises the following steps：
1) carrier synchronization：Assuming that n receptions obtain signal q (n), τ is power detection door to signal y (n) after demodulation
Limit, when | q (n) |2Phase discriminator output is 0 during ＜ τ, | q (n) |2Phase discriminator exports the phase error e of the time-ofday signals point during ＞ τ
(n), phase error controls NCO gradually to eliminate frequency deviation, skew after loop filter is smooth, reaches carrier synchronization；Choose and close
Suitable power detection thresholding τ, 16QAM phase error detection planisphere is converted into QPSK planisphere, then used
COSTAS loops are demodulated；For 16QAM after power detection is adjudicated, a (k), the b (k) that are calculated into phase discriminator only have one kind
Amplitude, therefore | a (k) |+| b (k) | it is constant, it is residual that error amount controls NCO gradually to eliminate frequency deviation after loop filter is smooth
Difference and phase error, reach carrier synchronization.
2) matched filtering is carried out respectively to inphase quadrature component signal；
3) because the clock of transmitter and receiver can have certain phase offset and clock skew, with skew by
Gradually accumulate, error code can be caused, have a strong impact on systematic function.The present invention uses the door algorithm sooner or later based on self-synchronizing method, is applied to
The system of high power sample rate, can "ball-park" estimate clock skew, it is simple for structure be easy to hardware realization.Inphase quadrature signal is led to
Cross " door sooner or later " and carry out bit timing recovery, make τ=T/2, the model of Timing Error Detector can be derived：
τ (n) is the sampling clock of compensation in formula,The transition value of (n+1)th and n-th of symbol is represented,Represent the transition value of n-th and (n-1)th symbol.Can obtain NCO outputs by formula (6) is：
τ (n+1)=τ (n)+γ e (n)；
4) setting thresholding is sampled judgement respectively to two paths of signals and 4-2 level conversions obtain parallel signal；
5) after carrying out differential decoding and parallel-serial conversion to parallel signal, primary signal is recovered.
Phase error e (n) is derived as follows in step 1), if reception signal r (k) is：
R (k)=a (k) cos [(ωc±ωd)kTs+θ]-b(k)sin[(ωc±ωd)kTs+θ]+n(t),
ω in formuladFor Doppler frequency shift, θ is carrier phase, and n (t) is receiving terminal Gaussian noise, and a (k), b (k) are base band
The same phase and quadrature component of symbol, TsFor the sampling period；Signal obtains after orthogonal mixing, LPF remove high fdrequency component
Arrive：
UI(k)=a (k) cos [(ωc±ωd-ωo)kTs+θ-θo]-b(k)sin[(ωc±ωd-ωo)kTs+θ-θo],
UQ(k)=b (k) cos [(ωc±ωd-ωo)kTs+θ-θo]+a(k)sin[(ωc±ωd-ωo)kTs+θ-θo],
Power detection value P (k) is：
P(k)=(UI(k))2+(UQ(k))2
When P (k) ＜ τ, phase detector error e (k)=0；As P (k) ＞ τ, Δ φ=(ω is madec±ωd-ωo)ksT+θ-oθ, will
UI、UQPhase discriminator is sent into, phase discriminator is based on hard decision algorithm herein, whenDuring very little,
Phase detector error e (k) can be obtained：
Beneficial effect of the present invention is：
1st, Novel carrier wave simultaneous techniques is introduced, carrier auxiliary is completed using phaselocked loop, and in traditional Costas loop
On the basis of, increase power detection techniques, ensure the linear convergent rate of phase discriminator, improve tracking accuracy and speed.
2nd, the algorithm of door sooner or later that carrier synchronization uses is easy to FPGA realizations.
3rd, harmful effects of the 16QAM to phase discriminator in synchronization is demodulated is overcome, significantly improves systematic function.
Brief description of the drawings
Fig. 1 is 16QAM signal constellation and mappings.
Fig. 2 is that 16QAM modulation FPGA realizes block diagram.
Fig. 3 is 16QAM power spectrum charts.
Fig. 4 is that 16QAM demodulation FPGA realizes block diagram.
Fig. 5 is carrier synchronization ring theory diagram.
Fig. 6 is Timing Synchronization ring theory diagram.
Fig. 7 (a) is rectangular pulse signal schematic diagram.
Fig. 7 (b) is that door algorithm carries out synchronous of bit timing using symmetry of the signal after matched filter sooner or later
Schematic diagram is exported with filtering.
Fig. 8 is total system FPGA schematic diagrames.
Fig. 9 is modulated signal of the transmitting terminal after differential coding.
Figure 10 (a) is that Matlab reads FPGA output waveform data figures
Figure 10 (b) is that Matlab reads the planisphere that FPGA output waveforms calculate.
Figure 11 be carrier wave without frequency deviation, the FPGA test results of carrier auxiliary during 22.5 ° of phase offset.
Figure 12 is carrier wave frequency deviation 3KHz, the FPGA test results of carrier auxiliary during no skew.
Figure 13 is carrier wave frequency deviation 3KHz, the FPGA test results of carrier auxiliary during 45 ° of skew.
Figure 14 is the planisphere after carrier synchronization.
Figure 15 (a) is bit synchronization FPGA test result overviews.
Figure 15 (b) is bit synchronization FPGA test result detailed views.
Figure 16 (a) is differential decoding, parallel-serial conversion FPGA test result overviews.
Figure 16 (b) is differential decoding, parallel-serial conversion FPGA test result detailed views.
The theoretical bit error rate and Simulated BER contrast schematic diagram that Figure 17 is 16QAM.
Embodiment
The modulation and demodulation process of 16QAM signal integrities is illustrated below in conjunction with the accompanying drawings, and entered by FPGA hardware
Row checking.
First, modulation principle
1st, differential coding
In view of 16QAM phase fuzzy problem, send signal and use Partial Differential coded system, i.e., it is only parallel to 4bit
The first two bit of data carries out differential coding.The coded system reduces the bit of differential coding relative to fully differential coding
Number, therefore reduce error code diffusion, there is preferable error performance.
In Partial Differential coding, with the first two bit a1a2Quadrant residing for specified signal, and difference volume is carried out to it
Code；Remaining two bit b1b2For providing the configuration of signal phasor in each quadrant, and configuration is set to show the rotation of pi/2
Symmetry, as shown in Figure 1.
Coding rule：
If [ab] is absolute code, that is, information code element is sent, [cd] is relocatable code, i.e. symbol after differential coding.
IfThenIfThen
Note：Add for mould 2, i is Symbol times.
2nd, modulation principle
16QAM modulation of the present invention uses quadrature amplitude modulation method, using the orthogonal four level magnitudes keying signals superposition of two-way
Into modulation FPGA realizes that block diagram is as shown in Figure 2.Input binary sequence is changed into 4bit parallel datas by serioparallel exchange
a1a2b1b2, to a1a2A ' is obtained as differential coding1a′2, b1b2Keep constant, then to a '1a′2、b1b22-4 level conversions are carried out respectively,
The PAM signals of four level are produced, the PAM signals have 2 kinds of amplitudes and 2 kinds of phases.Two PAM signals modulate respectively with mutually and
Quadrature carrier, per 4 kinds of possible outputs are modulated with all the way, merge through adder and produce 16QAM signals, its formula is described as：
S (k)=a (k) cos [ωckTs+θ1]-b(k)sin[ωckTs+θ1]
W in formulacFor carrier swing, θ1For initial phase, a (k), b (k) are the same phase and quadrature component of base band symbol, TsFor
Sampling period.
The power spectrum of 16QAM signals is as shown in Figure 3.It can be seen that 16QAM power spectrum signals are more compact, the availability of frequency spectrum is high,
The rate of information throughput is fast, can meet the needs of satellite communication.
2nd, 16QAM signals demodulation synchronization principles
Satellite received signal after Gaussian channel is transmitted is represented by：
R (k)=a (k) cos [(ωc±ωd)kTs+θ]-b(k)sin[(ωc±ωd)kTs+θ]+n(t)
In formula, θ is carrier phase, ωdFor Doppler frequency shift, n (t) is receiving terminal Gaussian noise.Reception signal r (t) is passed through
Same phase, orthogonal component signal are obtained after crossing carrier auxiliary, LPF (LPF), by bit timing recovery and sets thresholding to carry out 4
Level is adjudicated, and finally obtains parallel 4bit data, the i.e. inverse process of constellation mapping by level conversion.To the 4bit numbers after demodulation
Decoded according to Partial Differential corresponding to progress, original information data can be recovered by parallel-serial conversion.Demodulate synchronous FPGA principles
Block diagram is as shown in Figure 4.
3rd, 16QAM signals demodulating process
1st, carrier synchronization ring
Because 16QAM is non-constant envelope signal, loop bandwidth must be set using traditional QPSK COSTAS loops demodulation
The very little put just can guarantee that the linear of phase discriminator output, and precision is not high, and tracking velocity is slow.The present invention is traditional QPSK's
On the basis of COSTAS loops, the method for increase power detection judgement.Method is summarized as follows：Assuming that n receptions are to signal y (n),
Signal q (n) is obtained after demodulation.Then power detection is carried out to signal q (n), i.e., by judging q (n)2(τ is examined ＞ τ for power
Survey thresholding) whether select to need the received signal points of phase demodulation into Rob Roy.|q(n)|2Phase discriminator output is 0 during ＜ τ, | q (n) |2＞ τ
When phase discriminator export the phase error e (n) of the time-ofday signals point.Phase error controls after loop filter (LF) is smooth
NCO gradually eliminates frequency deviation, skew, reaches carrier synchronization., then can be by 16QAM's by choosing suitable power detection thresholding τ
Phase error detection planisphere is converted to QPSK planisphere, then is demodulated using classical COSTAS loops, overcomes
The influence to phase discriminator of the non-permanent envelopes of 16QAM.Its FPGA realization principle block diagram is as shown in Figure 5.
Loop algorithm derives as follows.If reception signal r (k) is：
R (k)=a (k) cos [(ωc±ωd)kTs+θ]-b(k)sin[(ωc±ωd)kTs+θ]+n(t)
ω in formuladFor Doppler frequency shift, θ is carrier phase, and n (t) is receiving terminal Gaussian noise, and a (k), b (k) are base band
The same phase and quadrature component of symbol, TsFor the sampling period.Signal obtains after orthogonal mixing, LPF remove high fdrequency component
Arrive：
UI(k)=a (k) cos [(ωc±ωd-ωo)kTs+θ-θo]-b(k)sin[(ωc±ωd-ωo)kTs+θ-θo]
UQ(k)=b (k) cos [(ωc±ωd-ωo)kTs+θ-θo]+a(k)sin[(ωc±ωd-ωo)kTs+θ-θo]
Power detection value P (k)：
P (k)=(UI(k))2+(UQ(k))2
When P (k) ＜ τ, phase detector error e (k)=0；As P (k) ＞ τ, Δ φ=(ω is madec±ωd-ωo)kTs+θ-θo, will
UI、UQPhase discriminator is sent into, phase discriminator is based on hard decision algorithm herein.WhenDuring very little,
Phase detector error e (k) can be obtained：
16QAM is after power detection is adjudicated, and a (k), the b (k) that are calculated into phase discriminator only have a kind of amplitude, therefore | a
(k) |+| b (k) | it is constant, error amount controls NCO gradually to eliminate frequency deviation residual error and phase mistake after loop filter is smooth
Difference, reach carrier synchronization.
2nd, bit timing synchronization ring
It is gradual with skew because the clock of transmitter and receiver can have certain phase offset and clock skew
Accumulation can then cause error code, have a strong impact on systematic function.The present invention uses the door algorithm sooner or later based on self-synchronizing method, suitable for height
The system of sampling rate, can "ball-park" estimate clock skew, it is simple for structure be easy to hardware realization.Its FPGA realizes block diagram as schemed
Shown in 6.
Door algorithm carries out bit timing synchronization using symmetry of the signal after matched filter sooner or later, as shown in fig. 7, its
Middle Fig. 7 (a) is rectangular pulse signal schematic diagram, and Fig. 7 (b) is that matched filtering exports schematic diagram..
Signal optimum sampling moment after matched filter is t=nT, but because noise, clock skew are likely to result in
Sampling can not be at the symbol signal to noise ratio maximum moment.When the sample value at transition value t=nT- τ and t '=nT+ τ moment is equal, most preferably
Sampling instant is just in the center time point of two sampling instants.If sampling, the difference of adjacent transition value late, which occurs, can be detected, pass through
Feedback loop control sampling clock, occur as the same during early sampling.Based on this principle, using two neighboring symbol transition value whether
It is equal, along with this information of the amplitude and polarity of optimum sampling point, τ=T/2 is made, the mould of Timing Error Detector can be derived
Type：
τ (n) is the sampling clock of compensation in formula,The transition value of (n+1)th and n-th of symbol is represented,The transition value of n-th and (n-1)th symbol is represented, NCO outputs as available from the above equation are：
τ (n+1)=τ (n)+γ e (n)
γ is step parameter in formula, and τ (n) is the sampling clock of compensation.After more level sample judgements through over level conversion most
4bit parallel datas after being demodulated afterwards, original binary system can just be restored by now also needing to differential decoding and parallel-serial conversion
Code stream.
3rd, differential decoding
Differential coding is corresponding, if [ab] is absolute code, that is, the information code element restored, [cd] is relocatable code, that is, after demodulating
Symbol.
IfThenIfThen
Note：Add for mould 2, i is Symbol times.
4th, the FPGA checkings of total system
The FPGA schematic diagrames of total system are as shown in figure 8, transmitter module generation 16QAM modulated signals, are converted to by D/A
Analog signal；A/D samples signal caused by transmitter module by SMA cables, and the receiving module in chip enters to sampled signal again
Row demodulation, data are interacted by JTAG mouths with PC.
1st, modulated signal produces
Test condition：Sample rate fs=100MHz, information rate Rb=100M/16=6.25Mbps, carrier frequency fc=
100M/8=12.5MHz.
Modulated signal of the transmitting terminal after differential coding is as shown in Figure 9.
Read using MATLAB shown in FPGA output waveforms such as Figure 10 (a) of QUARTUS-II software grabs, calculate 16QAM
Shown in the planisphere of modulated signal such as Figure 10 (b).
From time domain waveform and planisphere, the 16QAM signals that FPGA internal modulations go out meet the requirements.Due to FPGA internal modulations
There is frequency difference with local carrier caused by MATLAB software demodulations, differ in carrier wave, therefore square constellations have inclination, need to pass through
Carrier synchronization, correct planisphere can be just obtained, and then demodulate signal.
2nd, carrier auxiliary is tested
The FPGA test results of carrier auxiliary are as follows：
(1) carrier wave is without frequency deviation, and as shown in figure 11, first via signal is Phase Tracking curve to 22.5 ° of phase offset, due to phase
Fix partially and without frequency deviation, therefore pursuit gain perseverance is constant, shows to successfully track skew.Second, third road signal is respectively carrier wave
Baseband inphase, quadrature component after recovery, it is 4 level signals after recovery.
(2) carrier wave frequency deviation 3KHz, no skew is as shown in figure 12, and when carrier wave has frequency shift (FS), Phase Tracking value is into one
Secondary function linear change, tracking frequency change.The same phase of 4 level basebands, orthogonal signalling are obtained after carrier auxiliary.
(3) carrier wave frequency deviation 3KHz, 45 ° of skew is as shown in figure 13.
Planisphere after carrier synchronization is as shown in figure 14, it is known that the 16QAM baseband signals obtained after carrier synchronization
Planisphere has recovered horizontal, can be sampled judgement.
3rd, bit synchronization is tested
Bit synchronization FPGA test results are as shown in figure 15, and wherein Figure 15 (a) is overview, and Figure 15 (b) is detailed view.
Test condition：Carrier wave frequency deviation 3KHz, 45 ° of skew, bit synchronization clock phase offset 40% (relative to code-element period).
First via signal is the bit synchronization clock recovered, and second, third road is respectively baseband inphase, quadrature component matching
Filtered output signal, the four, the 5th tunnels are respectively the sample same phase after adjudicating, orthogonal 4 level signal.Can from figure
Go out the bit synchronization clock recovered based on door algorithm sooner or later accurately to have sampled the peak value moment after matched filtering, show
Bit synchronization circuit work in FPGA is good.
4th, differential decoding, parallel-serial conversion test
Differential decoding, parallel-serial conversion FPGA test results are as shown in figure 16, and wherein Figure 16 (a) is overview, Figure 16 (b)
For detailed view.Test condition：Carrier wave frequency deviation 3KHz, 45 ° of skew, bit synchronization clock phase skew 40% is (relative to symbol week
Phase).
Pass through level conversion, the inverse process of progress planisphere mapping, you can obtain 4bit parallel datas, then carry out difference
Decoding and parallel-serial conversion, finally recover binary code stream.
4bit parallel data of the first via for input binary code stream after string turns simultaneously；Second tunnel is by carrier auxiliary
With the inverse process of the 4bit parallel datas recovered after bit synchronization restoration, level conversion, i.e. planisphere mapping, phase be present due to demodulating
Position is fuzzy, therefore the second circuit-switched data may differ with the first circuit-switched data；3rd tunnel is the output after differential decoding, now data
It is identical with the first circuit-switched data；4th tunnel is input binary code stream, and the 5th tunnel is extensive after differential decoding data parallel-serial conversion
Multiple binary code stream.Signal obtains correct demodulation result after about postponing 500 sampled points as seen from the figure.
The above results show that differential encoding is added in 16QAM can solve phase fuzzy problem well.In carrier wave
Synchronous module, introduce power detection techniques on the basis of traditional Costas loop, ensure the linear convergent rate of phase discriminator, improve with
Track accuracy and speed, harmful effects of the 16QAM to phase discriminator in synchronization is demodulated is overcome, significantly improves systematic function.
Bit sync module, the door algorithm sooner or later based on self-synchronizing method that the present invention uses, can be thick suitable for the system of high power sample rate
Estimation clock skew slightly, it is simple for structure to be easy to FPGA hardware realization.
Algorithm performance is carried by the further checking present invention, Figure 17 provides the 16QAM theoretical bit error rate and Simulated BER,
Theoretical value is sufficiently close to using the 16QAM bit error rates of this algorithm.
Concrete application approach of the present invention is a lot, and described above is only the preferred embodiment of the present invention, it is noted that for
For those skilled in the art, under the premise without departing from the principles of the invention, some improvement can also be made, this
A little improve also should be regarded as protection scope of the present invention.
Claims (2)
1. a kind of 16QAM demodulates synchronous method, it is characterised in that comprises the following steps：
1) carrier synchronization：Assuming that n receptions obtain signal q (n) afterwards to signal y (n), demodulation, τ is power detection thresholding,
When | q (n) |2Phase discriminator output is 0 during ＜ τ, | q (n) |2Phase discriminator exports the phase error e of the time-ofday signals point during ＞ τ
(n), phase error controls NCO gradually to eliminate frequency deviation, skew after loop filter is smooth, reaches carrier synchronization；Choose work(
Rate detection threshold τ, 16QAM phase error detection planisphere is converted into QPSK planisphere, then using COSTAS loops
It is demodulated；
2) matched filtering is carried out respectively to inphase quadrature component signal；
3) bit timing recovery is carried out by " door sooner or later " to inphase quadrature signal, makes τ=T/2, Timing Error Detection can be derived
The model of device：
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τ (n) is the sampling clock of compensation in formula,The transition value of (n+1)th and n-th of symbol is represented,The transition value of n-th and (n-1)th symbol is represented, NCO outputs as available from the above equation are：
τ (n+1)=τ (n)+γ e (n), γ is step parameter in formula；
4) setting thresholding is sampled judgement respectively to two paths of signals and 4-2 level conversions obtain parallel signal；
5) after carrying out differential decoding and parallel-serial conversion to parallel signal, primary signal is recovered.
2. 16QAM according to claim 1 demodulates synchronous method, it is characterised in that：Phase error e (n) in step 1)
Derivation is as follows, if reception signal r (k) is：
R (k)=a (k) cos [(ωc±ωd)kTs+θ]-b(k)sin[(ωc±ωd)kTs+θ]+n(t),
ω in formuladFor Doppler frequency shift, θ is carrier phase, and n (t) is receiving terminal Gaussian noise, and a (k), b (k) are base band symbol
With phase and quadrature component, TsFor the sampling period；Signal obtains after orthogonal mixing, LPF remove high fdrequency component：
UI(k)=a (k) cos [(ωc±ωd-ωo)kTs+θ-θo]-b(k)sin[(ωc±ωd-ωo)kTs+θ-θo],
UQ(k)=b (k) cos [(ωc±ωd-ωo)kTs+θ-θo]+a(k)sin[(ωc±ωd-ωo)kTs+θ-θo],
Power detection value P (k) is：
P (k)=(UI(k))2+(UQ(k))2
When P (k) ＜ τ, phase detector error e (k)=0；As P (k) ＞ τ, Δ φ=(ω is madec±ωd-ωo)ksT+θ-oθ, by UI、UQ
Phase discriminator is sent into, phase discriminator is based on hard decision algorithm herein, whenDuring very little,It must can reflect
Phase device error e (k)：
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