CN104820182A - Signal integrity test method of SAS 12-G RX link - Google Patents
Signal integrity test method of SAS 12-G RX link Download PDFInfo
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- CN104820182A CN104820182A CN201510223211.6A CN201510223211A CN104820182A CN 104820182 A CN104820182 A CN 104820182A CN 201510223211 A CN201510223211 A CN 201510223211A CN 104820182 A CN104820182 A CN 104820182A
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Abstract
The invention, which belongs to the technical field of the computer testing, discloses a signal integrity test method of a serial-attached-SCSI (SAS) 12-G RX link. The method comprises the following steps that: a TX port and an RX port of an SAS controller are in signal connection by an SAS signal test clamp, thereby forming a loop; a code pattern generator controls the TX port to send a specific data code pattern out and the RX port receives the specific data code pattern; after certain bit data are received, error code existence of the RX port is checked; if not, the signal of the RX link is in an integrity mode and the RX link does not need optimization; and if so, a signal integrity problem exists in the RX link and optimization is carried out until no error code is generated based on testing. According to the invention, an error caused by manual operation can be substantially reduced and the test accuracy is improved.
Description
Technical field
The present invention discloses a kind of measuring signal integrality method, belongs to computer testing design field, specifically a kind of measuring signal integrality method of SAS 12G RX link.
Background technology
SAS (Serial Attached SCSI) i.e. serial SCSI technology is a kind of novel disk interconnection technique.It combines the advantage of existing parallel SCSI and technology connected in series, take serial communication as protocol basis framework, and adopting SCSI expansion instruction set and compatible SATA equipment, is multi-level memory device connection protocol stack.SAS decreases the deceleration of address conflict and daisy chain link; For each device provides special signal path to ensure maximum bandwidth, there is better extendability, more disk unit can be connected.
Along with the fast development of computer technology, the transfer rate of data is more and more higher, the transfer rate of SAS reaches 12Gbps, but along with the raising of message transmission rate, the integrity demands of signal also increases thereupon, the integrality task of test signal is following, SAS 12G system can stable operation, except the measuring signal integrality of common TX link, the signal integrity of RX link also needs to test, but the integrality of method testing SA S RX link signal also not easier at present.The present invention is in order to the signal quality of full test SAS 12G RX link, a kind of measuring signal integrality method of SAS 12G RX link is proposed, this method of testing does not rely on oscillograph, only just test can be completed with use SAS test fixture and testing software, relative to the RX link signal test carried out with oscillograph, greatly reduce the error that manual operation brings, improve the accuracy of test.
Summary of the invention
In order to the signal quality of full test SAS 12G RX link, ensure that SAS 12G system can stable operation, the invention provides a kind of measuring signal integrality method of SAS 12G RX link, relative to the RX link signal test carried out with oscillograph, greatly reduce the error that manual operation brings, improve the accuracy of test.
The concrete scheme that the present invention proposes is:
A kind of measuring signal integrality method of SAS 12G RX link:
The TX port of SAS controller is carried out signal with RX port by SAS signal testing fixture be connected, form a loop;
Pattern generator control TX end sends particular data code shape, and RX termination receives this particular data code shape;
The error code that RX holds is checked after receiving certain bit data; If do not have error code, the signal integrity of RX link is without the need to optimizing; If there is error code to produce, there is problems of Signal Integrity in RX link, is optimized, until test does not have error code to produce.
By SAS signal testing fixture, described TX port and RX port are undertaken that signal is connected is utilize SMA cable to be drawn by the TX port of SAS controller, connect the SAS female of SAS signal testing fixture, then drawn the RX port being connected to SAS controller by TX signal wire by SMA male.
TX described in PRBS generator controls holds and sends PRBS5 numeric data code shape, and RX termination receives this PRBS5 numeric data code shape.
Described reception 10
10-10
15check the error code that RX holds after bit data, the bit error rate is no more than 10
-10.
A measuring signal integrality system for SAS 12G RX link, comprises SAS controller, SAS test fixture, pattern generator;
SAS controller comprises TX port and RX port, and TX port carries out signal with RX port by SAS signal testing fixture and is connected, and forms a loop;
Pattern generator is connected with SAS controller, and control TX end sends particular data code shape, and RX termination receives this particular data code shape.
In system, by SAS signal testing fixture, described TX port and RX port are undertaken that signal is connected is utilize SMA cable to be drawn by the TX port of SAS controller, connect the SAS female of SAS signal testing fixture, then drawn the RX port being connected to SAS controller by TX signal wire by SMA male.
Described pattern generator is PRBS generator, is made up of shift register and XOR gate.
Usefulness of the present invention is: the present invention uses SAS signal testing fixture that the TX signal of tested SAS port is connected to RX, forms a loop.Control TX end sends particular data code shape, and RX receiving end receives identical data code shape, after receiving certain bit data, check the error code that RX holds.If there is no error code, illustrate that the signal integrity of RX link is no problem; If there is error code to produce, illustrate that RX link exists problems of Signal Integrity, need to carry out design optimization, until test does not have error code to produce.Method of testing of the present invention relies on oscillograph unlike traditional method of testing, only just test can be completed with a SAS test fixture and testing software, test relative to oscillograph, this method reduces the error that manual operation brings greatly, improves accuracy and the testing efficiency of test.
Accompanying drawing explanation
Fig. 1 test macro composition schematic diagram;
Fig. 2 test philosophy schematic diagram of the present invention.
Embodiment
The present invention will be further described by reference to the accompanying drawings.
As shown in Figure 1, a kind of measuring signal integrality system of SAS 12G RX link, comprises SAS controller, SAS test fixture, pattern generator;
SAS controller comprises TX port and RX port, and TX port carries out signal with RX port by SAS signal testing fixture and is connected, and forms a loop; In system, by SAS signal testing fixture, described TX port and RX port are undertaken that signal is connected is utilize SMA cable to be drawn by the TX port of SAS controller, connect the SAS female of SAS signal testing fixture, then drawn the RX port being connected to SAS controller by TX signal wire by SMA male;
Pattern generator is connected with SAS controller, and control TX end sends particular data code shape, and RX termination receives this particular data code shape.Pattern generator can be PRBS generator, is made up of shift register and XOR gate.
At test macro substantially, use a kind of measuring signal integrality method of SAS12G RX link, use SAS signal testing fixture that TX (Transmitter) signal of tested SAS port is connected to RX (Receiver), form a loop (Loop back) like this.PRBS generator control TX end sends particular data code shape, such as: PRBS5, RX receiving end receives identical data code shape, in reception 10
10-10
15check the error code (BER) that RX holds after bit data, if do not have error code, namely the bit error rate is less than 10
-10, illustrate that the signal integrity of RX link is no problem; If there is error code to produce, namely the bit error rate is greater than 10
-10, illustrate that RX link exists problems of Signal Integrity, need to be optimized, until test does not have error code to produce.
Specific operation process is as follows:
Build test platform, use SMA cable that the TX on SAS test fixture is connected to RX, SAS test fixture can be inserted tested SAS port or use SMA cable to connect;
Use PRBS generator to control tested SAS port TX and hold transmission PRBS5 numeric data code shape;
PRBS generator control RX termination receives PRBS5 numeric data code shape, and observes the error condition received;
10 are received in RX termination
12after bit data, check the error condition of RX end, result is as follows:
Except technology disclosed by the invention, the other technologies used in the present invention are all prior art that those skilled in the art can understand.
Claims (7)
1. a measuring signal integrality method for SAS 12G RX link, is characterized in that:
The TX port of SAS controller is carried out signal with RX port by SAS signal testing fixture be connected, form a loop;
Pattern generator control TX end sends particular data code shape, and RX termination receives this particular data code shape;
The error code that RX holds is checked after receiving certain bit data; If do not have error code, the signal integrity of RX link is without the need to optimizing; If there is error code to produce, there is problems of Signal Integrity in RX link, is optimized, until test does not have error code to produce.
2. the measuring signal integrality method of a kind of SAS 12G RX link according to claim 1, it is characterized in that by SAS signal testing fixture, described TX port and RX port are undertaken that signal is connected is utilize SMA cable to be drawn by the TX port of SAS controller, connect the SAS female of SAS signal testing fixture, then drawn the RX port being connected to SAS controller by TX signal wire by SMA male.
3. the measuring signal integrality method of a kind of SAS 12G RX link according to claim 1 and 2, it is characterized in that the TX end described in PRBS generator controls sends PRBS5 numeric data code shape, RX termination receives this PRBS5 numeric data code shape.
4. the measuring signal integrality method of a kind of SAS 12G RX link according to claim 3, is characterized in that described reception 10
10-10
15check the error code that RX holds after bit data, the bit error rate is less than 10
-10.
5. a measuring signal integrality system for SAS 12G RX link, is characterized in that comprising SAS controller, SAS test fixture, pattern generator;
SAS controller comprises TX port and RX port, and TX port carries out signal with RX port by SAS signal testing fixture and is connected, and forms a loop;
Pattern generator is connected with SAS controller, and control TX end sends particular data code shape, and RX termination receives this particular data code shape.
6. the measuring signal integrality system of a kind of SAS 12G RX link according to claim 5, it is characterized in that by SAS signal testing fixture, described TX port and RX port are undertaken that signal is connected is utilize SMA cable to be drawn by the TX port of SAS controller, connect the SAS female of SAS signal testing fixture, then drawn the RX port being connected to SAS controller by TX signal wire by SMA male.
7. the measuring signal integrality system of a kind of SAS 12G RX link according to claim 5 or 6, is characterized in that described pattern generator is PRBS generator, is made up of shift register and XOR gate.
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| CN201510223211.6A CN104820182A (en) | 2015-05-05 | 2015-05-05 | Signal integrity test method of SAS 12-G RX link |
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| CN201510223211.6A CN104820182A (en) | 2015-05-05 | 2015-05-05 | Signal integrity test method of SAS 12-G RX link |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106294055A (en) * | 2016-08-04 | 2017-01-04 | 浪潮电子信息产业股份有限公司 | The measuring signal integrality equipment of a kind of USB link, system and method |
| CN111948512A (en) * | 2020-06-19 | 2020-11-17 | 浪潮(北京)电子信息产业有限公司 | Cable signal integrity testing method and device and storage medium |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201185424Y (en) * | 2008-04-23 | 2009-01-21 | 青岛海信宽带多媒体技术股份有限公司 | Error code detector |
| CN101359307A (en) * | 2007-08-03 | 2009-02-04 | 英业达股份有限公司 | Test device of SAS channel and test method thereof |
| CN101645030A (en) * | 2009-09-04 | 2010-02-10 | 浪潮电子信息产业股份有限公司 | Method for measuring signal integrality based on SAS storage system |
| CN101819550A (en) * | 2009-02-26 | 2010-09-01 | 鸿富锦精密工业（深圳）有限公司 | Interface testing system for serial connecting small computer system |
| CN102123060A (en) * | 2011-03-24 | 2011-07-13 | 索尔思光电（成都）有限公司 | FPGA (Field Programmable Gate Array) based error code testing method |
| US20120290889A1 (en) * | 2011-05-11 | 2012-11-15 | Craig Anthony Klein | High-speed serial interface bridge adapter for signal integrity verification |
| CN102866308A (en) * | 2011-07-07 | 2013-01-09 | 鸿富锦精密工业（深圳）有限公司 | SAS signal integrity analysis system and method |
| CN104267221A (en) * | 2014-10-20 | 2015-01-07 | 浪潮电子信息产业股份有限公司 | SAS/SATA signal test fixture |
-
2015
- 2015-05-05 CN CN201510223211.6A patent/CN104820182A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101359307A (en) * | 2007-08-03 | 2009-02-04 | 英业达股份有限公司 | Test device of SAS channel and test method thereof |
| CN201185424Y (en) * | 2008-04-23 | 2009-01-21 | 青岛海信宽带多媒体技术股份有限公司 | Error code detector |
| CN101819550A (en) * | 2009-02-26 | 2010-09-01 | 鸿富锦精密工业（深圳）有限公司 | Interface testing system for serial connecting small computer system |
| CN101645030A (en) * | 2009-09-04 | 2010-02-10 | 浪潮电子信息产业股份有限公司 | Method for measuring signal integrality based on SAS storage system |
| CN102123060A (en) * | 2011-03-24 | 2011-07-13 | 索尔思光电（成都）有限公司 | FPGA (Field Programmable Gate Array) based error code testing method |
| US20120290889A1 (en) * | 2011-05-11 | 2012-11-15 | Craig Anthony Klein | High-speed serial interface bridge adapter for signal integrity verification |
| CN102866308A (en) * | 2011-07-07 | 2013-01-09 | 鸿富锦精密工业（深圳）有限公司 | SAS signal integrity analysis system and method |
| CN104267221A (en) * | 2014-10-20 | 2015-01-07 | 浪潮电子信息产业股份有限公司 | SAS/SATA signal test fixture |
Non-Patent Citations (1)
| Title |
|---|
| 陈昀等: "第三代信号完整性测试分析", 《江西通信科技》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106294055A (en) * | 2016-08-04 | 2017-01-04 | 浪潮电子信息产业股份有限公司 | The measuring signal integrality equipment of a kind of USB link, system and method |
| CN111948512A (en) * | 2020-06-19 | 2020-11-17 | 浪潮(北京)电子信息产业有限公司 | Cable signal integrity testing method and device and storage medium |
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