CN104281548A - Method, device and system for data transmission based on AXI bus - Google Patents
Method, device and system for data transmission based on AXI bus Download PDFInfo
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- CN104281548A CN104281548A CN201310277499.6A CN201310277499A CN104281548A CN 104281548 A CN104281548 A CN 104281548A CN 201310277499 A CN201310277499 A CN 201310277499A CN 104281548 A CN104281548 A CN 104281548A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
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Abstract
The invention discloses a method, device and system for data transmission based on an advanced extensible interface (AXI) bus. During data transmission based on the AXI bus, data supported by the AXI bus are transmitted through a PCIe bus, in other words, data supported by the AXI bus are converted into transmitted data supported by the PCIe bus in a device, and then the transmitted data supported by the PCIe data are converted into data supported by the AXI bus after the data are transmitted between devices through the PCIe bus. Due to the fact that ready signals of the AXI bus are transmitted only by four ac-coupled interconnected wires and other totally independent five dc-coupled interconnected wires during data transmission between devices through the PCIe bus, the number of interconnected wires used for data transmission through the AXI bus is reduced. Due to the fact that the PCIe bus is a high-speed serial point-to-point double-channel high-bandwidth bus, data transmission efficiency is not lower than that of the AXI bus, and the efficiency of data transmission through the AXI bus is not affected.
Description
Technical field
The present invention relates to SOC (system on a chip) (SoC) field, particularly one is based on method, the Apparatus and system of Advanced extensible Interface (AXI, Advanced eXtensible Interface) bus transfer data.
Background technology
AXI bus is the On-chip bus of a kind of high-performance, high bandwidth and low delay.Its address/control information and data are transmitted the transmission channel adopted and are separated, support the data transmission do not lined up, simultaneously in burst transfer, only need the first address of data just can transmit data, be separated read-write data transmission channel simultaneously and support significantly transmission access and out of order access.
When transmitting data between devices, AXI bus can be adopted to realize.Fig. 1 is the schematic diagram based on 64 AXI bus transfer datas between prior art equipment, as shown in the figure, during based on AXI bus transfer data, carry out at main equipment with between equipment, set up dissimilar transmission channel respectively at main equipment with from equipment, realize read data and write data.Particularly, write address transmission channel is set up at main equipment with between equipment, write data transmission channel and write response transmission channel, write address transmission channel is by 56 interconnection lines connection main equipments with from equipment, for main equipment by write data message write address information transmission give from equipment, write data transmission channel by 151 interconnection lines connection main equipments with from equipment, for main equipment will write data information transfer give from equipment, from equipment, by writing of receiving, data message writes corresponding write address, write response transmission channel is by 8 interconnection lines connection main equipments with from equipment, for will write after data message writes corresponding write address from equipment, feedback write state responds to main equipment.Address transfer passage and read data transmission passage is read at main equipment with from setting up between equipment, read address transfer passage by 56 interconnection lines connection main equipments with from equipment, the address information of reading that will read data for main equipment sends to from equipment, read data transmission passage connects main equipments by 137 interconnection lines and from equipment, for sending to main equipment from equipment according to by the data reading address information corresponding.
In FIG, for each transmission channel, have preparation (ready) signal of interconnection line transmission data respectively, for when each transmission channel will send or receive data, receiving equipment inform transmitting apparatus its all set.
AXI bus transfer data is adopted to have 3 deficiencies:
First: adopt AXI bus transfer data achieve address/control information institute adopt transmission channel and data to transmit adopt being separated of transmission channel, but result in main equipment and very large from the interconnection line quantity between equipment.As described in Figure 1, for the AXI of 128, its interconnection line quantity is more than 400, and this gives the encapsulation of chip and causes difficulty in the wiring of printed-wiring board (PWB) (PCB), and engineering is not easily implemented.
Second: adopt AXI bus transfer data to there are data and transmit situation about not lining up.When transmitting data, due to the restriction of clock frequency, require that the time interval (skew) that between interconnection line, data do not line up is very little, such as, when clock frequency is 1Ghz, then the clock period of interconnection line transmission data is 1ns, then the time interval do not lined up between interconnection line will be far smaller than 1ns, just can make read data transmission passage or the many interconnection lines write in data transmission channel all correctly transmit data within a clock period.Interconnection line as shown in Figure 2 transmit the time interval time diagram do not lined up of data, for large numbers of interconnection line when realizing data transmission, engineering is difficult to meet.
3rd: adopt during AXI bus transfer data and do not have error-detection mechanism, if because sequential or other reasons cause data transmission fault in transmitting procedure, then receiving equipment cannot confirm.
Can find out, the main reason causing employing AXI bus transfer data not easily to implement is exactly that the interconnection line quantity adopted is large, and when printing board PCB connected up and carry out data transmission within a clock period, in engineering, enforcement is just very difficult.In order to address this problem, just need interconnection line quantity to reduce.Realize main equipment and be exactly on the sending device parallel-serial conversion is carried out to data from the mode that the interconnection line quantity between equipment is few, on the receiving device serioparallel exchange is carried out to data again, as shown in Figure 3, Fig. 3 is the schematic diagram of transmission channel transmission data between prior art transmitting apparatus and receiving equipment, comprise: by main equipment to when writing data message from equipment by writing data transmission channel, by from equipment, this is write data encasement (ready) signal of transmission channel through also turning the ready signal obtaining serial after string is changed, after the ready signal of serial is sent to main equipment by universal serial bus, after obtaining the ready signal resolution walked abreast after carrying out serioparallel exchange again, send according to this parallel ready signal and write parallel data effectively (data VALID) signal of each interconnection line of data transmission channel based on this, the data valid signal for transmitting that this dataVALID signal carries, this parallel data VALID signal obtains the data VALID signal of serial through parallel-serial conversion, send to from equipment by universal serial bus, after serioparallel exchange, obtain the data VALID signal walked abreast, under being written to corresponding write address.Like this, owing to going here and there and the introducing of data conversion technique and universal serial bus, just the interconnection line writing data transmission channel can significantly be reduced.According to the method, the interconnection line of read data transmission passage can also significantly be reduced.But, due to when transmitting data, the transmission writing data transmission channel ready signal and data VALID signal in a parallel cycle and a serial cycles all will complete, this parallel-serial conversion writing the ready signal of all interconnection lines of data transmission channel and serioparallel exchange will be completed in this parallel cycle, the parallel-serial conversion of data VALID signal and serioparallel exchange, and ready signal and data VALID signal are not also live signals, this just makes, and the parallel clock cycle of setting is very long just can satisfy the demand, the frequency of AXI bus parallel clock is finally caused to reduce, transmission data efficiency step-down, reduce the efficiency of AXI bus transfer data.
Summary of the invention
In view of this, the invention provides a kind of method based on AXI bus transfer data, the method can under the prerequisite not affecting AXI bus transfer data efficiency, reduce main equipment and from the interconnection line quantity between equipment.
The present invention also provides a kind of device based on AXI bus transfer data, and this device can under the prerequisite not affecting AXI bus transfer data efficiency, reduces main equipment and from the interconnection line quantity between equipment.
The present invention also provides a kind of system based on AXI bus transfer data, and this system can under the prerequisite not affecting AXI bus transfer data efficiency, reduces main equipment and from the interconnection line quantity between equipment.
In order to reach foregoing invention object, technical scheme of the invention process is achieved in that
Based on a method for Advanced extensible Interface AXI bus transfer data, the method comprises:
The data of AXI bus support are transferred to the transmission data that PCIe bus is supported by transmitting apparatus;
The transmission data of PCIe bus support are transferred to receiving equipment by PCIe bus by transmitting apparatus between devices;
Receiving equipment receives the transmission data that PCIe bus is supported, is converted to the data that AXI bus is supported.
The method also comprises: receiving equipment adopts the interconnection line of five DC coupling that the ready signal of AXI bus is sent to transmitting apparatus.
The transmission data that the described data by the support of AXI bus are converted to the support of PCIe bus are:
Multiple asynchronous fifo fifo passage, application layer state machine and outlet RP are set in transmitting apparatus, the dissimilar data that set asynchronous FIFO channel reception AXI bus is supported, the data of AXI bus support are after the internal data that asynchronous FIFO Channel-shifted is serial, this internal data is carried out PCIe bus protocol layer TLP and is packed by the application layer state machine arranged, and this PCIe bus TLP bag carries the dissimilar data of described AXI support and the address information of these data.
Describedly the transmission data of PCIe bus support be transferred to receiving equipment between devices by PCIe bus be:
PCIe bus has four interconnection lines, be respectively two difference output interconnection lines, TxN and TxP, and two Differential Input interconnection lines, RxN and RxP, adopt to export and distinguish AC coupling between two with input, PCIe bus TLP wraps through TxN and TxP by the outlet RP of transmitting apparatus, be ac-coupled to RxN and RxP, be transferred to the entrance EP that receiving equipment is arranged.
The transmission data that described reception PCIe bus is supported, the process being converted to the data of AXI bus support is:
The PCIe bus TLP of reception is wrapped the application layer state machine sending to receiving equipment to arrange by the EP of receiving equipment, this application layer state machine wraps the address information of mark according to PCIe bus TLP, PCIe bus TLP is wrapped the asynchronous FIFO passage that the different types of data carried is transferred to set correspondence respectively, the data of AXI bus support is converted to by the asynchronous FIFO passage of correspondence the data that AXI bus supports.
Described transmitting apparatus is main equipment, and receiving equipment is from equipment, and the dissimilar data of described AXI bus comprise: write address information, write data message and read address information, accesses different asynchronous FIFO passages respectively;
Or described transmitting apparatus is from equipment, receiving equipment is main equipment, and the dissimilar data of described AXI bus comprise: write response information and read data information, accesses different asynchronous FIFO passages respectively.
Based on a system for Advanced extensible Interface AXI bus transfer data, comprise transmitting apparatus and receiving equipment, wherein,
Transmitting apparatus, for transferring the transmission data that PCIe bus is supported to by the data of AXI bus support; The transmission data of PCIe bus support are transferred to receiving equipment between devices by PCIe bus;
Receiving equipment, for receiving the transmission data that PCIe bus is supported, is converted to the data that AXI bus is supported.
Receiving equipment is also for adopting the interconnection line of five DC coupling that the ready signal of AXI bus is sent to transmitting apparatus.
Described transmitting apparatus, specifically for arranging multiple asynchronous fifo fifo passage, application layer state machine and outlet RP, the data of AXI bus support are transferred to the transmission data that PCIe bus is supported, the dissimilar data of set FIFO channel reception AXI bus, the data of AXI bus support through asynchronous FIFO Channel-shifted be after serial internal data, after this internal data is carried out PCIe bus protocol layer TLP packing by the application layer state machine arranged, this PCIe bus TLP bag carries the dissimilar data of described AXI support and the address information of these data.
Described transmitting apparatus, specifically for the transmission data of PCIe bus support are transferred to receiving equipment between devices by PCIe bus, PCIe bus has four interconnection lines, is respectively two difference output interconnection lines, TxN and TxP, and two Differential Input interconnection lines, RxN and RxP, adopt to export and distinguish AC coupling between two with input, PCIe bus TLP wraps through TxN and TxP by RP, export and be ac-coupled to RxN and RxP respectively between two with input, be transferred to the EP that receiving equipment is arranged.
Described receiving equipment, specifically for receiving the transmission data that PCIe bus is supported, be converted to the data that AXI bus is supported, the PCIe bus TLP of reception bag is sent to the application layer state machine of setting by EP, this application layer state machine wraps the address information of mark according to PCIe bus TLP, PCIe bus TLP is wrapped the asynchronous FIFO passage that the different types of data carried is transferred to set correspondence respectively, the data of AXI bus support is converted to by the asynchronous FIFO passage of correspondence the data that AXI bus supports.
Described transmitting apparatus is main equipment, and receiving equipment is from equipment, and the dissimilar data of described AXI bus comprise: write address information, write data message and read address information, accesses different asynchronous FIFO passages respectively;
Or described transmitting apparatus is from equipment, receiving equipment is main equipment, and the dissimilar data of described AXI bus comprise: write response information and read data information, accesses different asynchronous FIFO passages respectively.
Based on a device for Advanced extensible Interface AXI bus transfer data, comprising: many asynchronous fifo fifo passages, the first application layer state machine, the second application layer state machine and gateway, wherein,
Many asynchronous FIFO passages, for receiving the different types of data of AXI bus respectively, being converted to serial internal data, sending the first application layer state machine, or after receiving corresponding different types of data from the second application layer state machine, be converted to the data that AXI bus is supported;
First application layer state machine, after the serial internal data from many asynchronous FIFO channel reception being carried out PCIe bus TLP packing, this PCIe bus protocol layer TLP bag carries dissimilar data and the address information of these data, is transferred to gateway;
Second application layer state machine, wraps for the PCIe bus TLP will received from gateway, according to the address information that this PCIe bus TLP wraps mark, PCIe bus TLP is wrapped the asynchronous FIFO passage that the different types of data carried is transferred to set correspondence respectively;
Gateway, the PCIe bus TLP for receiving from the first application layer state machine wraps and sends; Received PCIe bus TLP bag is sent to the second application layer state machine.
Also comprising AXI bus module, for adopting the interconnection line of five DC coupling, the ready signal of AXI bus being sent.
Described gateway middle outlet is RP, and entrance is EP.
As can be seen from the above scheme, the present invention is when based on AXI bus transfer data, data AXI bus supported are by PCIe bus transfer, namely in a device, the transmission data that standard (PCIe) bus data of AXI bus support being transferred to local bus is at a high speed supported, after being transmitted between devices by PCIe bus, then the transmission data of PCIe bus support are converted to the data of AXI bus support.Due to PCIe bus transmit data between devices time, only have four by the ready signal of the interconnection line of AC coupling and the completely independently interconnection line transmission AXI bus of other five DC coupling, so decrease the interconnection line quantity of AXI bus transfer data.Be again the bus of the point-to-point binary channels high bandwidth of high speed serialization due to PCIe bus, its transmission data efficiency is not less than AXI bus, thus can not affect AXI bus transmit the transfer efficiency of data.
Accompanying drawing explanation
Fig. 1 is the schematic diagram based on 64 AXI bus transfer datas between prior art equipment;
The interconnection line that Fig. 2 is prior art transmit the time interval time diagram not lining up data of data;
Fig. 3 is the schematic diagram of transmission channel transmission data between prior art transmitting apparatus and receiving equipment;
The method flow diagram based on AXI bus transfer data that Fig. 4 provides for the embodiment of the present invention;
The system architecture schematic diagram based on AXI bus transfer data that Fig. 5 provides for the embodiment of the present invention;
The apparatus structure schematic diagram based on AXI bus transfer data that Fig. 6 provides for the embodiment of the present invention;
Fig. 7 adopts main equipment of the present invention and from the structural representation transmitting data between equipment;
The state transfer flow of the first application layer state machine that Fig. 8 provides for the embodiment of the present invention;
The different types of data of the asynchronous FIFO passage reading AIX bus that Fig. 9 provides for the embodiment of the present invention, and be converted to the method flow diagram of internal data.
Embodiment
For making object of the present invention, technical scheme and advantage clearly understand, to develop simultaneously embodiment referring to accompanying drawing, the present invention is described in further detail.
The present invention is in order under the prerequisite not affecting AXI bus transfer data efficiency, reduce main equipment and from the interconnection line quantity between equipment, make to adopt AXI bus transfer data easy to implement, when based on AXI bus transfer data, data AXI bus supported are by PCIe bus transfer, namely in a device, the data of AXI bus support are transferred to the transmission data that PCIe bus is supported, after being transmitted between devices by PCIe bus, then the transmission data of PCIe bus support are converted to the data of AXI bus support.Due to PCIe bus transmit data between devices time, only have four by the ready signal of the interconnection line of AC coupling and completely independently other five interconnection lines transmission AXI bus, so decrease the interconnection line quantity of AXI bus transfer data.Be again the bus of the point-to-point binary channels high bandwidth of high speed serialization due to PCIe bus, its transmission data efficiency is not less than AXI bus, thus can not affect AXI bus transmit the transfer efficiency of data.
The method flow diagram based on AXI bus transfer data that Fig. 4 provides for the embodiment of the present invention, its concrete steps are:
The data of AXI bus support are transferred to the transmission data that PCIe bus is supported by step 401, transmitting apparatus;
The transmission data of PCIe bus support are transferred to receiving equipment by PCIe bus by step 402, transmitting apparatus between devices;
Step 403, receiving equipment receive the transmission data that PCIe bus is supported, are converted to the data that AXI bus is supported.
Before Fig. 4 performs step 401, the method also comprises: the interconnection line being provided with five DC coupling between the AXI bus of transmitting apparatus and receiving equipment, receiving equipment adopts the interconnection line of five DC coupling that the ready signal of AXI bus is sent to transmitting apparatus, and it prepares to receive data to inform transmitting apparatus.The write address transmission channel of AXI bus that the interconnection line of five DC coupling is corresponding respectively, write data transmission channel, write response transmission channel, read address transfer passage and read data transmission passage, respectively as the ready signal of each data transmission channel.
In the step 401 described in Fig. 4, the process that the data of AXI bus support are converted to the transmission data of PCIe bus support by transmitting apparatus is:
Multiple asynchronous first in first out (FIFO) passage is set in transmitting apparatus, application layer state machine and outlet (RP are set, Root Port), the dissimilar data of set FIFO channel reception AXI bus, the data of AXI bus support through asynchronous FIFO Channel-shifted be after serial internal data, after this serial internal data is carried out PCIe bus processing layer agreement (TLP) packing by the application layer state machine arranged, this PCIe bus TLP bag carries dissimilar data and the address information of these data, and the RP being transferred to transmitting apparatus sends.
In the step 402 described in Fig. 4, the process that the transmission data of PCIe bus support are transferred to receiving equipment between devices by PCIe bus is by transmitting apparatus:
PCIe bus has four interconnection lines, be respectively two difference output interconnection lines (TxN and TxP) and two Differential Input interconnection lines (RxN and RxP), AC coupling mode is interconnected respectively between two to adopt output and input, PCIe bus TLP wraps through TxN and TxP by the RP of transmitting apparatus, be ac-coupled to RxN and RxP, be transferred to the entrance (EP, End Port) that receiving equipment is arranged.
In the step 403 described in Fig. 4, receiving equipment receives the transmission data that PCIe bus is supported, the process being converted to the data of AXI bus support is:
The PCIe bus TLP of reception bag is sent to the application layer state machine of setting by the EP of receiving equipment, this application layer state machine wraps the address information of mark according to PCIe TLP, PCIe bus TLP is wrapped the asynchronous FIFO passage that the different types of data carried is transferred to set correspondence respectively, is converted data to the data of AXI bus support by the asynchronous FIFO passage of correspondence.
In embodiments of the present invention, transmitting apparatus can be main equipment or from equipment, wherein, when transmitting apparatus is main equipment, the dissimilar data of its AXI bus comprise: write address information, write data message and read address information, access different asynchronous FIFO passages respectively; When transmitting apparatus is from equipment, the dissimilar data of its AXI bus comprise: write response information and read data information, access different asynchronous FIFO passages respectively.
The system architecture schematic diagram based on AXI bus transfer data that Fig. 5 provides for the embodiment of the present invention, comprises transmitting apparatus and receiving equipment, wherein,
Transmitting apparatus, for transferring the transmission data that PCIe bus is supported to by the data of AXI bus support; The transmission data of PCIe bus support are transferred to receiving equipment between devices by PCIe bus;
Receiving equipment, for receiving the transmission data that PCIe bus is supported, is converted to the data that AXI bus is supported.
Within the system, transmitting apparatus, specifically for arranging multiple asynchronous fifo fifo passage, application layer state machine and outlet RP, the data of AXI bus support are transferred to the transmission data that PCIe bus is supported, the dissimilar data of set FIFO channel reception AXI bus, the data of AXI bus support through asynchronous FIFO Channel-shifted be after serial internal data, after this internal data is carried out PCIe bus TLP packing by the application layer state machine arranged, this PCIe bus TLP bag carries dissimilar data and the address information of these data, the RP being transferred to transmitting apparatus sends.
Within the system, receiving equipment, specifically for adopting the interconnection line of five DC coupling that the ready signal of AXI bus is sent to transmitting apparatus, in figure 6, is designated the straight line of 5 band arrows.
Within the system, transmitting apparatus, specifically for the transmission data of PCIe bus support are transferred to receiving equipment between devices by PCIe bus, PCIe bus has four interconnection lines, be respectively two difference output interconnection lines, TxN and TxP, and two Differential Input interconnection lines, RxN and RxP, adopt to export and distinguish AC coupling between two with input, PCIe bus TLP is wrapped TxN and TxP through transmitting apparatus by RP, exports RxN and RxP being ac-coupled to receiving equipment with input between two respectively, is transferred to the EP that receiving equipment is arranged.
Within the system, receiving equipment, specifically for receiving the transmission data that PCIe bus is supported, be converted to the data that AXI bus is supported, the PCIe bus TLP of reception bag is sent to the application layer state machine of setting by EP, this application layer state machine wraps the address information of mark according to PCIe bus TLP, and PCIe bus TLP is wrapped the asynchronous FIFO passage that the different types of data carried is transferred to set correspondence respectively, is converted data to the data of AXI bus support by the asynchronous FIFO passage of correspondence.
Within the system, described transmitting apparatus is main equipment or from equipment, wherein, when transmitting apparatus is main equipment, the dissimilar data of its AXI bus comprise: write address information, write data message and read address information, access different asynchronous FIFO passages respectively; When transmitting apparatus is from equipment, the dissimilar data of its AXI bus comprise: write response information and read data information, access different asynchronous FIFO passages respectively.
The apparatus structure schematic diagram based on AXI bus transfer data that Fig. 6 provides for the embodiment of the present invention, this device both can also can as receiving equipment as transmitting apparatus, comprise: many asynchronous FIFO passages, the first application layer state machine, the second application layer state machine and gateway, wherein
Many asynchronous FIFO passages, AXI bus data outside the ready signal of only process AXI bus, for receiving the different types of data of AXI bus respectively, be converted to serial internal data, send the first application layer state machine, or after receiving corresponding different types of data from the second application layer state machine, be converted to the data that AXI bus is supported;
First application layer state machine, after the serial internal data from many asynchronous FIFO channel reception being carried out PCIe bus TLP packing, this PCIe bus TLP bag carries dissimilar data and the address information of these data, is transferred to gateway;
Second application layer state machine, wraps for the PCIe bus TLP will received from gateway, according to the address information that this PCIe bus TLP wraps mark, PCIe bus TLP is wrapped the asynchronous FIFO passage that the different types of data carried is transferred to set correspondence respectively;
Gateway, the PCIe bus TLP for receiving from the first application layer state machine wraps and sends; Received PCIe bus TLP bag is sent to the second application layer state machine.
In a device, also comprising AXI bus module, for adopting the interconnection line of five DC coupling, the ready signal of AXI bus being sent.
In the apparatus, export as RP, entrance is EP.
In the present invention, relate to state machine, for main equipment, when it is as transmitting apparatus, there is the first application layer state machine of RP, when it is as receiving equipment, there is the second application layer state machine of RP, for from equipment, when it is as transmitting apparatus, there is the first application layer state machine of EP, when it is as receiving equipment, there is the second application layer state machine of EP.Adopt main equipment of the present invention particularly and transmit the structural representation of data as shown in Figure 7 between equipment.
In the present invention, state machine, when processing the different types of data of AXI bus, carries out different state transfers.For the first application layer state machine of main equipment and the second application layer state machine, carry out the state transfer instruction of state machine.
The state transfer flow of the first application layer state machine that Fig. 8 provides for the embodiment of the present invention.Its concrete steps are:
Step 801, to main equipment with from the PCIe bus reset between equipment;
Step 802, main equipment and connect from the PCIe bus between equipment;
Step 803, the RP of the PCIe bus of main equipment to be configured;
Step 804, the EP of the PCIe bus from equipment to be configured;
Step 805, main equipment determine whether that configuration completes, and if so, perform step 806; If not, then return step 804 to continue to perform;
The RP of step 806, main equipment adopts the storer of PCIe to write action, notify to send read data information and write response information from the EP of equipment, received read data information and write response information are deposited and sends to two asynchronous FIFO passages respectively afterwards, be converted to the data of AIX bus;
The RP of step 807, main equipment reads respectively and writes data message, write address information and read address information from three asynchronous FIFO passages, sends to the EP from equipment;
The RP of step 808, main equipment judges whether that transmission is normal, if not, and process ends; If so, then return step 807 to continue to perform.
The different types of data of the asynchronous FIFO passage reading AIX bus that Fig. 9 provides for the embodiment of the present invention, and be converted to the method flow diagram of serial internal data, its concrete steps are:
Step 901, main equipment read the empty zone bit of a FIFO passage of the write address information of AIX bus;
Whether step 902, the empty zone bit judging a FIFO passage are non-NULL, if so, then perform step 907; If not, then step 903 is performed;
Step 903, main equipment read the empty zone bit writing the 2nd FIFO passage of data message of AIX bus;
Whether step 904, the empty zone bit judging the 2nd FIFO passage are non-NULL, if so, then perform step 907; If not, then step 905 is performed;
Step 905, main equipment read the empty zone bit reading the 3rd FIFO passage of address information of AIX bus;
Whether step 906, the empty zone bit judging the 3rd FIFO passage are non-NULL, if so, then perform step 907; If not, execution step 901 is returned;
In this step, the Ergodic judgement of three FIFO passages is realized;
In step 907, the write address information extracted in a FIFO passage, the 2nd FIFO passage write in data message or the 3rd FIFO passage read address information after, be converted to PCIe bus TLP and wrap;
Step 908, transmit this PCIe bus TLP and wrap;
Step 909, main equipment judge whether that transmission is normal, if not, then terminate, and if so, then perform step 910;
Step 910, main equipment judge whether the data of next AIX bus to be processed are write data channel, if so, perform step 903; If not, then execution step 911 is proceeded to;
Step 911, main equipment judge that whether the data of next AIX bus to be processed are for reading address tunnel, if so, perform step 905; If not, then execution step 912 is proceeded to;
Step 912, main equipment judge whether the data of next AIX bus to be processed are write address passage, if so, perform step 901; If not, then execution step 913 is proceeded to;
After step 913, main equipment report an error, process ends.
Adopt the present invention, main equipment and only have 9 from the interconnection line between equipment, i.e. TxP, TxN, RxP and RxN, the interconnection line between equipment is interconnected by AC coupling mode, and the ready signal of the completely independently interconnection line transmission AXI bus of other five DC coupling.Can finding out, needing compared with 400 interconnection lines, to greatly reduce interconnection line quantity, overcome first deficiency of AXI bus transfer data at main equipment with from transmitting data between equipment with based on AIX bus.Simultaneously, owing to only having the ready signal of four AC coupling interconnection lines and the completely independently interconnection line transmission AXI bus of other five DC coupling, on pcb board, wiring is simple, and reduce costs and connect up difficulty, and the second point overcoming AXI bus transfer data is not enough.Adopt PCIe bus transfer data between devices, because PCIe bus itself is containing Cyclic Redundancy Check function, if transmit data between equipment to can be implemented in equipment connection layer because strong jamming causes makeing mistakes and automatically to report an error re-transmission, overcome the thirdly not enough of AXI bus transfer data.
Further, have employed asynchronous FIFO Channel-shifted AXI bus in a device, achieve the useful signal of data and the ready signal isolation of data, the clock frequency of AXI bus can not be reduced.
More than lift preferred embodiment; the object, technical solutions and advantages of the present invention are further described; be understood that; the foregoing is only preferred embodiment of the present invention; not in order to limit the present invention; within the spirit and principles in the present invention all, any amendment done, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (14)
1. based on a method for Advanced extensible Interface AXI bus transfer data, it is characterized in that, the method comprises:
The transmission data that the Standard PC Ie bus that the data of AXI bus support are transferred to local bus at a high speed by transmitting apparatus is supported;
The transmission data of PCIe bus support are transferred to receiving equipment by PCIe bus by transmitting apparatus between devices;
Receiving equipment receives the transmission data that PCIe bus is supported, is converted to the data that AXI bus is supported.
2. the method for claim 1, is characterized in that, the method also comprises: receiving equipment adopts the interconnection line of five DC coupling that the ready signal of AXI bus is sent to transmitting apparatus.
3. the method for claim 1, is characterized in that, the transmission data that the described data by the support of AXI bus are converted to the support of PCIe bus are:
Multiple asynchronous fifo fifo passage, application layer state machine and outlet RP are set in transmitting apparatus, the dissimilar data that set asynchronous FIFO channel reception AXI bus is supported, the data of AXI bus support are after the internal data that asynchronous FIFO Channel-shifted is serial, this internal data is carried out PCIe bus protocol layer TLP and is packed by the application layer state machine arranged, and this PCIe bus TLP bag carries the dissimilar data of described AXI support and the address information of these data.
4. the method as described in claim 1,2 or 3, is characterized in that, describedly the transmission data of PCIe bus support are transferred to receiving equipment between devices by PCIe bus are:
PCIe bus has four interconnection lines, be respectively two difference output interconnection lines, TxN and TxP, and two Differential Input interconnection lines, RxN and RxP, adopt to export and distinguish AC coupling between two with input, PCIe bus TLP wraps through TxN and TxP by the outlet RP of transmitting apparatus, be ac-coupled to RxN and RxP, be transferred to the entrance EP that receiving equipment is arranged.
5. method as claimed in claim 3, is characterized in that, the transmission data that described reception PCIe bus is supported, the process being converted to the data of AXI bus support is:
The PCIe bus TLP of reception is wrapped the application layer state machine sending to receiving equipment to arrange by the EP of receiving equipment, this application layer state machine wraps the address information of mark according to PCIe bus TLP, PCIe bus TLP is wrapped the asynchronous FIFO passage that the different types of data carried is transferred to set correspondence respectively, the data of AXI bus support is converted to by the asynchronous FIFO passage of correspondence the data that AXI bus supports.
6. method as claimed in claim 5, it is characterized in that, described transmitting apparatus is main equipment, and receiving equipment is from equipment, the dissimilar data of described AXI bus comprise: write address information, write data message and read address information, access different asynchronous FIFO passages respectively;
Or described transmitting apparatus is from equipment, receiving equipment is main equipment, and the dissimilar data of described AXI bus comprise: write response information and read data information, accesses different asynchronous FIFO passages respectively.
7. based on a system for Advanced extensible Interface AXI bus transfer data, it is characterized in that, comprise transmitting apparatus and receiving equipment, wherein,
Transmitting apparatus, the transmission data that the Standard PC Ie bus for the data of AXI bus support being transferred to local bus is at a high speed supported; The transmission data of PCIe bus support are transferred to receiving equipment between devices by PCIe bus;
Receiving equipment, for receiving the transmission data that PCIe bus is supported, is converted to the data that AXI bus is supported.
8. system as claimed in claim 7, it is characterized in that, receiving equipment is also for adopting the interconnection line of five DC coupling that the ready signal of AXI bus is sent to transmitting apparatus.
9. system as claimed in claim 7, it is characterized in that, described transmitting apparatus, specifically for arranging multiple asynchronous fifo fifo passage, application layer state machine and outlet RP, the data of AXI bus support are transferred to the transmission data that PCIe bus is supported, the dissimilar data of set asynchronous FIFO channel reception AXI bus, the data of AXI bus support through asynchronous FIFO Channel-shifted be after serial internal data, after this internal data is carried out PCIe bus protocol layer TLP packing by the application layer state machine arranged, this PCIe bus TLP bag carries the dissimilar data of described AXI support and the address information of these data.
10. the system as described in claim 7,8 or 9, it is characterized in that, described transmitting apparatus, specifically for the transmission data of PCIe bus support are transferred to receiving equipment between devices by PCIe bus, PCIe bus has four interconnection lines, be respectively two difference output interconnection lines, TxN and TxP, and two Differential Input interconnection lines, RxN and RxP, adopt to export and distinguish AC coupling between two with input, PCIe bus TLP wraps through TxN and TxP by RP, export and be ac-coupled to RxN and RxP respectively between two with input, be transferred to the entrance EP that receiving equipment is arranged.
11. systems as claimed in claim 10, it is characterized in that, described receiving equipment, specifically for receiving the transmission data that PCIe bus is supported, be converted to the data that AXI bus is supported, the PCIe bus TLP of reception bag is sent to the application layer state machine of setting by EP, this application layer state machine wraps the address information of mark according to PCIe bus TLP, PCIe bus TLP is wrapped the asynchronous FIFO passage that the different types of data carried is transferred to set correspondence respectively, the data of AXI bus support is converted to by the asynchronous FIFO passage of correspondence the data that AXI bus supports.
12. systems as claimed in claim 11, it is characterized in that, described transmitting apparatus is main equipment, and receiving equipment is from equipment, the dissimilar data of described AXI bus comprise: write address information, write data message and read address information, access different asynchronous FIFO passages respectively;
Or described transmitting apparatus is from equipment, receiving equipment is main equipment, and the dissimilar data of described AXI bus comprise: write response information and read data information, accesses different asynchronous FIFO passages respectively.
13. 1 kinds based on the device of Advanced extensible Interface AXI bus transfer data, is characterized in that, comprising: many asynchronous fifo fifo passages, the first application layer state machine, the second application layer state machine and gateway, wherein,
Many asynchronous FIFO passages, for receiving the different types of data of AXI bus respectively, being converted to serial internal data, sending the first application layer state machine, or after receiving corresponding different types of data from the second application layer state machine, be converted to the data that AXI bus is supported;
First application layer state machine, after Standard PC Ie bus protocol layer TLP for the serial internal data from many asynchronous FIFO channel reception being carried out local bus at a high speed packs, this PCIe bus TLP bag carries dissimilar data and the address information of these data, is transferred to gateway;
Second application layer state machine, wraps for the PCIe bus TLP will received from gateway, according to the address information that this PCIe bus TLP wraps mark, PCIe bus TLP is wrapped the asynchronous FIFO passage that the different types of data carried is transferred to set correspondence respectively;
Gateway, the PCIe bus TLP for receiving from the first application layer state machine wraps and sends; Received PCIe bus TLP bag is sent to the second application layer state machine.
14. devices as claimed in claim 13, is characterized in that, also comprise AXI bus module, are sent by the ready signal of AXI bus for adopting the interconnection line of five DC coupling.
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| CN108595350A (en) * | 2018-01-04 | 2018-09-28 | 深圳开阳电子股份有限公司 | A kind of data transmission method and device based on AXI |
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| CN111338996A (en) * | 2020-02-20 | 2020-06-26 | 山东华芯半导体有限公司 | Composite bus controller supporting multiple protocols |
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| CN104901859A (en) * | 2015-06-11 | 2015-09-09 | 东南大学 | AXI/PCIE bus converting device |
| CN105005546A (en) * | 2015-06-23 | 2015-10-28 | 中国兵器工业集团第二一四研究所苏州研发中心 | Asynchronous AXI bus structure with built-in cross point queue |
| CN105005546B (en) * | 2015-06-23 | 2018-01-30 | 中国兵器工业集团第二一四研究所苏州研发中心 | A kind of asynchronous AXI bus structures of built-in intersection point queue |
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| CN108595350A (en) * | 2018-01-04 | 2018-09-28 | 深圳开阳电子股份有限公司 | A kind of data transmission method and device based on AXI |
| CN108769282B (en) * | 2018-04-28 | 2021-02-05 | 北京航天发射技术研究所 | PDU management control method based on automatic addressing |
| CN108769282A (en) * | 2018-04-28 | 2018-11-06 | 北京航天发射技术研究所 | A kind of PDU management control methods based on automatic addressing |
| CN108924459A (en) * | 2018-08-06 | 2018-11-30 | 上海顺久电子科技有限公司 | A kind of output interface circuit and device |
| CN108924459B (en) * | 2018-08-06 | 2021-04-13 | 上海顺久电子科技有限公司 | Output interface circuit and device |
| CN109471824B (en) * | 2018-11-22 | 2021-02-05 | 青岛方寸微电子科技有限公司 | AXI bus-based data transmission system and method |
| CN109471824A (en) * | 2018-11-22 | 2019-03-15 | 青岛方寸微电子科技有限公司 | Data transmission system and method based on AXI bus |
| CN111338996A (en) * | 2020-02-20 | 2020-06-26 | 山东华芯半导体有限公司 | Composite bus controller supporting multiple protocols |
| CN111338996B (en) * | 2020-02-20 | 2022-04-22 | 山东华芯半导体有限公司 | Composite bus controller supporting multiple protocols |
| CN111752881A (en) * | 2020-06-22 | 2020-10-09 | 深圳鲲云信息科技有限公司 | Inter-module communication method and system |
| CN112732611A (en) * | 2021-01-18 | 2021-04-30 | 上海国微思尔芯技术股份有限公司 | AXI-based chip interconnection system |
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| CN114546924B (en) * | 2022-01-28 | 2024-05-03 | 山东云海国创云计算装备产业创新中心有限公司 | AXI-based bidirectional data transmission method, AXI-based bidirectional data transmission system, AXI-based bidirectional data transmission storage medium and AXI-based bidirectional data transmission equipment |
| CN114546924A (en) * | 2022-01-28 | 2022-05-27 | 山东云海国创云计算装备产业创新中心有限公司 | AXI-based bidirectional data transmission method, system, storage medium and equipment |
| CN115550104A (en) * | 2022-12-06 | 2022-12-30 | 北京华环电子股份有限公司 | AXI bus expansion method, device, electronic equipment and storage medium |
| CN115550104B (en) * | 2022-12-06 | 2023-08-15 | 北京华环电子股份有限公司 | AXI bus expansion method, device, electronic equipment and storage medium |
| CN117009276A (en) * | 2023-06-27 | 2023-11-07 | 进迭时空(珠海)科技有限公司 | Method, device and system for signal compression transmission based on AXI bus |
| CN117009276B (en) * | 2023-06-27 | 2024-06-25 | 进迭时空(珠海)科技有限公司 | Method, device and system for signal compression transmission based on AXI bus |
| CN117234995A (en) * | 2023-07-24 | 2023-12-15 | 进迭时空(珠海)科技有限公司 | AHB bus-based signal compression transmission method, system and device |
| CN117234995B (en) * | 2023-07-24 | 2024-07-02 | 进迭时空(珠海)科技有限公司 | AHB bus-based signal compression transmission method, system and device |
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