CN104810391A - Power device electrode and manufacture method thereof - Google Patents
Power device electrode and manufacture method thereof Download PDFInfo
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- CN104810391A CN104810391A CN201410042915.9A CN201410042915A CN104810391A CN 104810391 A CN104810391 A CN 104810391A CN 201410042915 A CN201410042915 A CN 201410042915A CN 104810391 A CN104810391 A CN 104810391A
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- layer
- titanium
- silicon chip
- silicon
- tungsten
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 56
- 239000010703 silicon Substances 0.000 claims abstract description 56
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 56
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 42
- 239000010936 titanium Substances 0.000 claims abstract description 42
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 42
- 229910001069 Ti alloy Inorganic materials 0.000 claims abstract description 30
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims abstract description 30
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 26
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 19
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000001257 hydrogen Substances 0.000 claims abstract description 7
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 7
- 238000000137 annealing Methods 0.000 claims abstract description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 6
- 239000004411 aluminium Substances 0.000 claims description 10
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 6
- 239000003595 mist Substances 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 150000002431 hydrogen Chemical class 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 3
- 238000003475 lamination Methods 0.000 claims description 2
- 239000007789 gas Substances 0.000 abstract description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 abstract 1
- 230000004888 barrier function Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- 239000007772 electrode material Substances 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 238000009826 distribution Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
Abstract
The invention provides a power device electrode and a manufacture method thereof. The method comprises the following steps: sequentially forming a first titanium layer, a tungsten titanium alloy layer and a second titanium layer on a silicon wafer; in a mixed gas of nitrogen and hydrogen, carrying out high-temperature annealing processing on the silicon wafer to enable the first titanium layer to form a titanium silicon compound layer arranged between the surface of the silicon wafer and the tungsten titanium alloy layer by reacting with the silicon wafer, and form a titanium nitride layer arranged on the surface of the second titanium layer; and laying a metal interconnection layer on the surface of the titanium nitride layer. According to the power device electrode and the manufacture method thereof, under a high-temperature heavy-current application scene, device performance and reliability of the device can be effectively guaranteed and improved.
Description
Technical field
The present invention relates to field of semiconductor technology, particularly relate to a kind of power device electrode manufacturing method.
Background technology
For high frequency, microwave power device, under being operated in larger current density and larger power condition, reducing of the current convergence effect that particularly uneven distribution on knot face causes due to electric current and hot-fluid and hot-fluid sectional area, add and be subject to the fast-changing impact of operating state, make high frequency, the thermal stability problems of microwave power device is more outstanding.
Concrete, the metallic electrode structure of device directly has influence on the thermal stability of device, has tremendous influence to the Performance And Reliability of device.At present, existing a kind of power device electrode is individual layer fine aluminium electrode.This electrode structure is under low current density and low working temperature, even the performance of device can be guaranteed.But under high frequency and high power work condition, this electrode structure but demonstrates larger limitation, such as, at relatively high temperatures, aluminium and silicon, silica effect is very violent, and silicon is also easy to be added in electrode material, causes the electrode structure of device to be destroyed, again such as, under high temperature big current condition of work, aluminium electrode there will be a kind of ELECTROMIGRATION PHENOMENON, makes metal electrode material surface produce cavity and projection.Therefore, above-mentioned existing scheme is only applicable to the application scenarios that operating frequency is lower and working current density is less, and cannot ensure the reliability of device under the application scenarios of high temperature big current.
Summary of the invention
The invention provides a kind of power device electrode and manufacture method thereof, the problem of device reliability cannot be ensured for solving existing device electrode structure under the application scenarios of high temperature big current.
First aspect of the present invention is to provide a kind of power device electrode manufacturing method, comprising:
Silicon chip generates the first titanium layer, tungsten-titanium alloy layer and the second titanium layer successively;
In the mist of nitrogen and hydrogen, the high temperature anneal is carried out to described silicon chip, forms the silicon-titanium compound layer between described silicon chip surface and described tungsten-titanium alloy layer to make described first titanium layer by described silicon chip reaction and form the titanium nitride layer being positioned at described second titanium layer surface;
Metal interconnection layer is laid on the surface of described titanium nitride layer.
Another aspect of the present invention is to provide a kind of power device electrode, comprising:
Be positioned at the silicon-titanium compound layer on silicon chip surface;
Be positioned at the tungsten-titanium alloy layer on described silicon-titanium compound layer surface;
Be positioned at the titanium layer on described tungsten-titanium alloy layer surface;
Be positioned at the titanium nitride layer on described titanium layer surface;
Be positioned at the metal interconnection layer on described titanium nitride layer surface.
Power device electrode provided by the invention and manufacture method thereof, the silicon-titanium compound layer with good deelectric transferred ability is formed at silicon face, described silicon-titanium compound layer directly contacts with tungsten-titanium alloy layer, contact resistance can be reduced, be positioned on described tungsten-titanium alloy layer surface, the titanium nitride layer that titanium layer is formed on the surface, has good barrier effect simultaneously, can under the application scenarios of high temperature big current, effectively ensure and improve device performance and the reliability of device.
Accompanying drawing explanation
The schematic flow sheet of a kind of power device electrode manufacturing method that Fig. 1 provides for the embodiment of the present invention one;
Fig. 2-Fig. 4 is the generalized section of power device electrode in embodiment one implementation.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described.For convenience of description, zoomed in or out the size of different layers and region, so size shown in figure and ratio might not represent actual size, also do not reflect the proportionate relationship of size.
The schematic flow sheet of a kind of power device electrode manufacturing method that Fig. 1 provides for the embodiment of the present invention one, in order to know the description of system to the method in the present embodiment, Fig. 2-Fig. 4 is the generalized section of power device electrode in embodiment one implementation, as shown in Figure 1, said method comprising the steps of:
101, on silicon chip, the first titanium layer, tungsten-titanium alloy layer and the second titanium layer is generated successively.
Particularly, the generalized section of the described power device electrode after 101 is performed as shown in Figure 2, wherein, described silicon chip label 11 represents, described first titanium layer label 12 represents, described tungsten-titanium alloy layer label 13 represents, described second titanium layer label 14 represents.Wherein, the type of described silicon chip can comprise N-type silicon substrate and P-type silicon substrate, and the type of described silicon chip can also comprise the epitaxial wafer that grown one or more layers silicon thin film on a silicon substrate.
In actual applications, before carrying out technological process, usually first can carry out clean to the surface of silicon chip, then, accordingly, before 101, described method can also comprise:
By dry etching and/or wet etching, clean described silicon chip.
Wherein, described dry etching can include but not limited to the lithographic method such as reactive ion etching, inductively coupled plasma.
Being appreciated that by performing above-mentioned steps, the sandwich construction of titanium/tungsten-titanium alloy/titanium can be formed on the surface of silicon chip.Concrete, the thickness of described each structure sheaf can according to actual process and device architecture need determine, such as, the thickness of described first titanium layer can be 0.01 μm ~ 1 μm, the thickness of described second titanium layer can be 0.1 μm ~ 20 μm, the thickness of described tungsten-titanium alloy layer can be 0.01 μm ~ 10 μm, and the present embodiment is not limited at this.
102, in the mist of nitrogen and hydrogen, the high temperature anneal is carried out to described silicon chip, forms the silicon-titanium compound layer between described silicon chip surface and described tungsten-titanium alloy layer to make described first titanium layer by described silicon chip reaction and form the titanium nitride layer being positioned at described second titanium layer surface.
Particularly, perform the generalized section of the described power device electrode after 102 as shown in Figure 3, wherein, described silicon chip label 11 represents, described silicon-titanium compound layer label 15 represents, described titanium nitride layer label 16 represents.
Wherein, can need to determine according to actual process in each process parameter of the process of described the high temperature anneal, such as, nitrogen in described mist: the volume ratio of hydrogen can be able to be 550 DEG C ~ 1000 DEG C for the annealing temperature of the high temperature anneal described in 100:1 ~ 1:1, annealing time can be 5 minutes ~ 60 minutes, and the present embodiment is not limited at this.
Be appreciated that, by performing above-mentioned steps, can by described silicon chip surface and the first titanium layer be positioned on described silicon chip surface, through the high temperature anneal, form the silicon-titanium compound layer between described silicon chip surface and described tungsten-titanium alloy layer, thus formation ohmic contact, effectively reduce contact resistance, improve device performance and reliability.
Further, in the present embodiment, described silicon-titanium compound layer directly contacts with described tungsten-titanium alloy layer, thus reduce contact resistance further, and, effectively can prevent described silicon-titanium compound layer projection, there is good deelectric transferred ability, and then ensure and improve device performance and reliability further.
In addition, in the present embodiment, the surf zone of described second titanium layer is through above-mentioned the high temperature anneal, form the titanium nitride layer being positioned at described second titanium layer surface, this titanium nitride layer has good barrier effect, can use as barrier layer, can not impact the preparation of follow-up metal interconnection layer and device package technique, and the reliability of device electrode can be improved, thus effectively ensure the reliability of device.
Be appreciated that described silicon-titanium compound layer in the present embodiment and titanium nitride layer can be formed in a high temperature anneal process simultaneously, thus simplify technological process, reduce the cost that device manufactures.Meanwhile, the hydrogen in described mist, as the protective gas in annealing process, can prevent the generation of oxide, thus reduce contact resistance further.
103, metal interconnection layer is laid on the surface of described titanium nitride layer.
Particularly, perform the generalized section of the described power device electrode after 103 as shown in Figure 4, wherein, described metal interconnection layer label 17 represents.
Wherein, the material of described metal interconnection layer can be gold, silver, aluminium, platinum or molybdenum, and the selection of concrete material can be determined according to actual conditions, such as, aluminium can be used as metal electrode material, then accordingly, 103 specifically can comprise: on the surface of described titanium nitride layer, prepare aluminium lamination.
In actual applications, before preparing metal interconnection layer, usually also can first clean the current silicon chip possessing sandwich construction, then, accordingly, before 103, described method can also comprise:
By dry etching and/or wet etching, clean described silicon chip.
Concrete, described dry etching can include but not limited to the lithographic method such as reactive ion etching, inductively coupled plasma.
The power device electrode manufacturing method that the present embodiment provides, the silicon-titanium compound layer with good deelectric transferred ability is formed at silicon face, described silicon-titanium compound layer directly contacts with tungsten-titanium alloy layer, contact resistance can be reduced, be positioned on described tungsten-titanium alloy layer surface, the titanium nitride layer that titanium layer is formed on the surface, has good barrier effect simultaneously, can under the application scenarios of high temperature big current, effectively ensure and improve device performance and the reliability of device.
The embodiment of the present invention two provides a kind of power device electrode, and as shown in Figure 4, described power device electrode comprises its generalized section:
Be positioned at the silicon-titanium compound layer 15 on silicon chip 11 surface;
Be positioned at the tungsten-titanium alloy layer 13 on silicon-titanium compound layer 15 surface;
Be positioned at the titanium layer 14 on tungsten-titanium alloy layer 13 surface;
Be positioned at the titanium nitride layer 16 on titanium layer 14 surface;
Be positioned at the metal interconnection layer 17 on titanium nitride layer 16 surface.
Wherein, described second titanium layer in embodiment one, is the titanium layer 14 in the present embodiment.The type of described silicon chip can comprise N-type silicon substrate and P-type silicon substrate, and the type of described silicon chip can also comprise the epitaxial wafer that grown one or more layers silicon thin film on a silicon substrate.
Concrete, the thickness of described each structure sheaf can according to actual process and device architecture need determine, such as, the thickness of described first titanium layer can be 0.01 μm ~ 1 μm, the thickness of the second titanium layer 14 can be 0.1 μm ~ 20 μm, the thickness of tungsten-titanium alloy layer 13 can be 0.01 μm ~ 10 μm, and the present embodiment is not limited at this.
Be appreciated that the silicon-titanium compound layer 15 between silicon chip 11 surface and tungsten-titanium alloy layer 13, the ohmic contact of formation, effectively can reduce contact resistance, improves device performance and reliability.
Further, in the present embodiment, silicon-titanium compound layer 15 directly contacts with tungsten-titanium alloy layer 13, thus reduce contact resistance further, and, effectively can prevent silicon-titanium compound layer 15 projection, there is good deelectric transferred ability, and then ensure and improve device performance and reliability further.
In addition, in the present embodiment, titanium nitride layer 16 has good barrier effect, can use as barrier layer, can not impact the preparation of follow-up metal interconnection layer 17 and device package technique, and the reliability of device electrode can be improved, thus effectively ensure the reliability of device.
Wherein, the material of described metal interconnection layer can be gold, silver, aluminium, platinum or molybdenum, and the selection of concrete material can be determined according to actual conditions, and such as, aluminium can be used as metal electrode material, then accordingly, the material of metal interconnection layer 17 is specifically as follows aluminium.
The power device electrode that the present embodiment provides, the silicon-titanium compound layer with good deelectric transferred ability is formed at silicon face, described silicon-titanium compound layer directly contacts with tungsten-titanium alloy layer, contact resistance can be reduced, be positioned on described tungsten-titanium alloy layer surface, the titanium nitride layer that titanium layer is formed on the surface, has good barrier effect simultaneously, can under the application scenarios of high temperature big current, effectively ensure and improve device performance and the reliability of device.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (12)
1. a power device electrode manufacturing method, is characterized in that, comprising:
Silicon chip generates the first titanium layer, tungsten-titanium alloy layer and the second titanium layer successively;
In the mist of nitrogen and hydrogen, the high temperature anneal is carried out to described silicon chip, forms the silicon-titanium compound layer between described silicon chip surface and described tungsten-titanium alloy layer to make described first titanium layer by described silicon chip reaction and form the titanium nitride layer being positioned at described second titanium layer surface;
Metal interconnection layer is laid on the surface of described titanium nitride layer.
2. method according to claim 1, is characterized in that, the thickness of described first titanium layer is 0.01 μm ~ 1 μm.
3. method according to claim 1, is characterized in that, the thickness of described second titanium layer is 0.1 μm ~ 20 μm.
4. method according to claim 1, is characterized in that, the thickness of described tungsten-titanium alloy layer is 0.01 μm ~ 10 μm.
5. method according to claim 1, is characterized in that, nitrogen in described mist: the volume ratio of hydrogen is 100:1 ~ 1:1.
6. method according to claim 1, is characterized in that, the annealing temperature of described the high temperature anneal is 550 DEG C ~ 1000 DEG C, and annealing time is 5 minutes ~ 60 minutes.
7. the method according to any one of claim 1-6, is characterized in that, describedly on the surface of described titanium nitride layer, prepares metal interconnection layer, specifically comprises:
Aluminium lamination is laid on the surface of described titanium nitride layer.
8. the method according to any one of claim 1-6, is characterized in that, described on the surface of silicon chip, prepare the first titanium layer, tungsten-titanium alloy layer and the second titanium layer successively before, also comprise:
By dry etching and/or wet etching, clean described silicon chip.
9. the method according to any one of claim 1-6, is characterized in that, described on the surface of described titanium nitride layer, prepare metal interconnection layer before, also comprise:
By dry etching and/or wet etching, clean described silicon chip.
10. the method according to any one of claim 1-6, is characterized in that, the type of described silicon chip comprises N-type silicon substrate and P-type silicon substrate.
11. methods according to any one of claim 1-6, it is characterized in that, the type of described silicon chip comprises the epitaxial wafer that grown one or more layers silicon thin film on a silicon substrate.
12. 1 kinds of power device electrodes, is characterized in that, comprising:
Be positioned at the silicon-titanium compound layer on silicon chip surface;
Be positioned at the tungsten-titanium alloy layer on described silicon-titanium compound layer surface;
Be positioned at the titanium layer on described tungsten-titanium alloy layer surface;
Be positioned at the titanium nitride layer on described titanium layer surface;
Be positioned at the metal interconnection layer on described titanium nitride layer surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410042915.9A CN104810391A (en) | 2014-01-29 | 2014-01-29 | Power device electrode and manufacture method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410042915.9A CN104810391A (en) | 2014-01-29 | 2014-01-29 | Power device electrode and manufacture method thereof |
Publications (1)
| Publication Number | Publication Date |
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| CN104810391A true CN104810391A (en) | 2015-07-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201410042915.9A Pending CN104810391A (en) | 2014-01-29 | 2014-01-29 | Power device electrode and manufacture method thereof |
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| CN (1) | CN104810391A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5162262A (en) * | 1989-03-14 | 1992-11-10 | Mitsubishi Denki Kabushiki Kaisha | Multi-layered interconnection structure for a semiconductor device and manufactured method thereof |
| US7226858B2 (en) * | 2004-09-30 | 2007-06-05 | Microchip Technology Incorporated | Submicron contact fill using a CVD TiN barrier and high temperature PVD aluminum alloy deposition |
| CN101651118A (en) * | 2008-08-14 | 2010-02-17 | 旺宏电子股份有限公司 | A semiconductor device and method for manufacturing the same |
-
2014
- 2014-01-29 CN CN201410042915.9A patent/CN104810391A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5162262A (en) * | 1989-03-14 | 1992-11-10 | Mitsubishi Denki Kabushiki Kaisha | Multi-layered interconnection structure for a semiconductor device and manufactured method thereof |
| US7226858B2 (en) * | 2004-09-30 | 2007-06-05 | Microchip Technology Incorporated | Submicron contact fill using a CVD TiN barrier and high temperature PVD aluminum alloy deposition |
| CN101651118A (en) * | 2008-08-14 | 2010-02-17 | 旺宏电子股份有限公司 | A semiconductor device and method for manufacturing the same |
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Application publication date: 20150729 |