CN104810363A - Power integrated device and manufacture method thereof - Google Patents
Power integrated device and manufacture method thereof Download PDFInfo
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- CN104810363A CN104810363A CN201410037708.4A CN201410037708A CN104810363A CN 104810363 A CN104810363 A CN 104810363A CN 201410037708 A CN201410037708 A CN 201410037708A CN 104810363 A CN104810363 A CN 104810363A
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Abstract
The invention belongs to the semiconductor technical field and discloses a power integrated device and a manufacture method thereof. According to the power integrated device and the manufacture method thereof of the invention, doping ions of the substrate of the power integrated device are changed, so that contact between the doping ions and a metal layer on the back surface of the substrate can form low contact resistance, and therefore, back surface injection and annealing process of the substrate can be omitted, and the production cost of a CDMOS product can be decreased, and the production cycle of the CDMOS product can be shortened.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of power IC device and preparation method thereof.
Background technology
Along with the progress of science and technology, the high-tech intelligent integrated circuit speed of development is more and more faster, it is convenient that the power promoting this industry development is exactly the life wished of people, the a lot of tube core of script is integrated on a package module with regard to needing by this, so just can play small-sized object easily, being sub-divided into semiconductor applications is exactly so-called power IC device (CDMOS).Function logic module (CMOS) and high-voltage power module (DMOS) can be integrated on a package module by CDMOS, greatly increase the integrated level of device.
Traditional CDMOS product is all form CMOS and DMOS in a heavily doped substrate.Conductive ion due to N-type substrate is electronics, and facing conductive ion is the P type substrate in hole, and its conductive capability is stronger, is applied in CDMOS product more widely.In existing production technology, N-type substrate is generally antimony (Sb) doping, but the contact resistance of the metal level of antimony and backside of substrate (drain electrode as DMOS) is very large, in order to reduce contact resistance, and then minimizing conducting resistance, before making drain metal layer, need to increase the back side inject and annealing process, but but add the production cost of CDMOS product like this, extend the fabrication cycle of CDMOS product.
Shown in composition graphs 1-Fig. 3, in prior art, the concrete Making programme of CDMOS product is:
1, in Si semiconductor, antimony dopant forms heavily doped N-type substrate 10 ＇, and grows one deck initial epitaxial layer (not shown) in the front Doping Phosphorus of substrate 10 ＇;
2, substrate is placed on is full of dichlorosilane with in the low pressure boiler tube of ammonia, all grow one deck silicon nitride medium film 20 ＇ at the front and back of substrate by dichlorosilane with ammonia gas react; Because the stress of silicon nitride is very large, easy generation sliver, in order to improve the stress of silicon nitride, before substrate is formed silicon nitride medium film 20 ＇, can also all generate thin pad oxygen medium film 30 ＇ of one deck by thermal oxidation technology at the front and back of substrate 10 ＇;
3, the silicon nitride in graphical substrate 10 ＇ front and pad oxygen composite bed, form the pattern of composite bed, and with the pattern of described composite bed for mask, in basad 10 ＇, Doped ions forms p type buried layer 40 ＇ of CDMOS;
4, carry out wet etching with hot phosphoric acid, remove silicon nitride and the pad oxygen composite bed of substrate 10 ＇ front and back completely;
5, at epitaxial loayer 50 ＇ that front regrowth one deck of substrate 10 ＇ is thin, the making of CDMOS product buried regions is so far completed;
6, then start the making of active area, polycrystal layer, N-type source and drain, P type source and drain, contact hole etc., be in figure and illustrate;
7, do the back side to inject and annealing;
8, drain metal layer (not shown) is formed at the back side of substrate 10.
Summary of the invention
The invention provides a kind of power IC device and preparation method thereof, needed to increase back side injection and annealing process before solving making backside of substrate metal level, to reduce the contact resistance of substrate Doped ions and metal level, but but add the production cost of CDMOS product, extend the problem of the fabrication cycle of CDMOS product.
For solving the problems of the technologies described above, the invention provides a kind of manufacture method of power IC device, comprising:
Adulterate the first ion in semiconductor base, forms the heavy doped conduction substrate of the first conduction type;
Metal level is formed at the back side of described heavy type doping substrate;
Wherein, described first ion forms low contact resistance with contacting of metal level.
Meanwhile, the present invention also provides a kind of power IC device, comprising:
The heavy doped conduction substrate of the first conduction type, doped with the first ion in described heavy doped conduction substrate;
Metal level, is formed in the back side of described heavy type doping substrate;
Wherein, described first ion forms low contact resistance with contacting of metal level.
The beneficial effect of technique scheme of the present invention is as follows:
In technique scheme, by changing the Doped ions of power IC device substrate, making it form low contact resistance with the contacting of metal level of backside of substrate, thus eliminating backside of substrate injection and annealing process, reduce the production cost of CDMOS product, shorten the fabrication cycle of CDMOS product.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1-Fig. 3 represents the manufacturing process schematic diagram of power IC device in prior art;
Fig. 4 represents the Making programme figure of power IC device in the embodiment of the present invention;
Fig. 5-Fig. 7 represents the manufacturing process schematic diagram of power IC device in the embodiment of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples for illustration of the present invention, but are not used for limiting the scope of the invention.
For CDMOS product, it comprises and is integrated in suprabasil CMOS and DMOS.Drain electrode except VDMOS is formed in except the back side of substrate, and other structures (including source region, P type source and drain, N-type source and drain, polycrystal layer, contact hole etc.) of CDMOS are all formed in the front of substrate.
Wherein, according to the difference of Doped ions, substrate is divided into the substrate of P type and N-type substrate, and the conductive ion due to N-type substrate is electronics, and facing conductive ion is the P type substrate in hole, and its conductive capability is stronger, is widely used in CDMOS product.In existing production technology, N-type substrate is generally antimony (Sb) doping, but the contact resistance of the drain metal layer of antimony and backside of substrate is very large.In order to reduce contact resistance, and then reducing the conducting resistance of VDMOS, before making drain metal layer, needing to increase the back side inject and annealing process.But so but add the production cost of CDMOS product, extend the fabrication cycle of CDMOS product.
Embodiment one
As shown in Figure 4, in order to solve the problems of the technologies described above, a kind of manufacture method of power IC device is provided in the present embodiment, comprise:
Step S1, adulterate the first ion in semiconductor base, forms the heavy doped conduction substrate of the first conduction type;
Step S2, described heavy type doping substrate the back side formed metal level;
Wherein, described first ion forms low contact resistance with contacting of metal level.
In technique scheme, by changing the Doped ions of power IC device substrate, making it form low contact resistance with the contacting of metal level of backside of substrate, thus eliminating backside of substrate injection and annealing process, reduce the production cost of CDMOS product, shorten the fabrication cycle of CDMOS product.
Concrete, described heavy doped conduction substrate can select N type semiconductor substrate, can provide less conducting resistance for CDMOS product.
Further, when described semiconductor base is Si semiconductor substrate, described first ion can select arsenic (As) ion, because the contact resistance of arsenic ion and metal level is only 1/5 of the contact resistance of antimony (Sb) ion and metal level, form low contact resistance, thus the conducting resistance of VDMOS can be reduced, improve the performance of CDMOS product.Meanwhile, inject with annealing process to reduce conducting resistance owing to not needing to increase backside of substrate, thus reduce the production cost of CDMOS product, shorten the fabrication cycle of CDMOS product.
Because CDMOS product can comprise P type CMOS, N-type CMOS, P type DMOS and N-type DMOS simultaneously, in order to formation P type MOS and N-type MOS, CDMOS product also need the heavy doping buried regions comprising the second conduction type on the same base simultaneously.Further, in order to improve the puncture voltage of CDMOS, above the heavy doping buried regions of the second conduction type, form the light dope epitaxial loayer of the second conduction type.
For the N-type heavily doped silicon semiconductor base of arsenic doped ion, because the atomic weight of arsenic ion is lighter, in the forming process of the light dope epitaxial loayer of the second conduction type, hot environment can make arsenic ion be diffused in surrounding air, with the front of reacting gas fused deposition to heavy doped conduction substrate, affect resistivity value and the uniformity of light dope epitaxial loayer, produce autodoping effect.
In order to prevent the autodoping effect of arsenic ion from having an impact to light dope epitaxial loayer, preferably, heavy doping buried regions and the light dope epitaxial loayer of same conduction type is formed by following steps:
Between described heavy doped conduction substrate and described metal level, form the first barrier film, form the second barrier film in the front of described heavy doped conduction substrate;
Graphically described second barrier layer, forms the pattern on the second barrier layer;
With described second barrier layer pattern for mask, to adulterate the second ion to described heavy doped conduction substrate, form the heavy doping buried regions of the second conduction type;
Remove the second barrier layer.
Can form heavy doping buried regions in the front of heavy doped conduction substrate by above-mentioned steps, and the conduction type of heavy doping buried regions is different with the conduction type of heavy doped conduction substrate.Such as: for N-type heavy doped conduction substrate, it forms P type heavy doping buried regions, described second ion can select boron ion.
Then, above described heavy doping buried regions, form the light dope epitaxial loayer of the second conduction type, its conduction type is identical with the conduction type of heavy doping buried regions.Owing to being formed with the first barrier layer between heavy doped conduction substrate and metal level, in the light dope epitaxial loayer of formation second conduction type, first barrier layer can effectively prevent arsenic (AS) ion to be diffused in high temperature environments in surrounding environment, with reacting gas fused deposition to heavy doped conduction substrate front, affect the quality of the light dope epitaxial loayer of the second conduction type, thus prevent the autodoping effect of arsenic (AS) ion to have an impact to light dope epitaxial loayer.
Form the first barrier film and the second barrier film by one-time process in the present embodiment simultaneously, with process simplification, and in the technique on graphical described second barrier layer, the second barrier layer is removed by dry etching, thus first barrier layer at the heavy doped conduction substrate back side can be retained, prevent the autodoping effect of arsenic (AS) ion from having an impact to light dope epitaxial loayer.。
Wherein, the first barrier layer and the second barrier layer can be the composite bed of silicon nitride layer and oxygen pad layer, and oxygen pad layer is near the side of described heavy doped conduction substrate, for improving the stress of silicon nitride.Specifically heavy doped conduction substrate can be put into low pressure boiler tube, generate silicon nitride by dichlorosilane with ammonia gas react, form silicon nitride layer at the front and back of heavy doped conduction substrate.And before formation silicon nitride layer, form oxygen pad layer by thermal oxidation technology, physical deposition or chemical deposition process at the front and back of heavy doped conduction substrate.
The first barrier film and the second barrier film can certainly be formed by different process.Concrete, behind removal second barrier layer, then the first barrier layer can be formed at the back side of heavy doped conduction substrate, and then above heavy doping buried regions, form the light dope epitaxial loayer of same conduction type.
Shown in composition graphs 5-Fig. 7, the concrete manufacturing process of embodiment of the present invention power IC device is:
Step a, arsenic doped ion in Si semiconductor substrate, forms N-type heavy doped conduction substrate 10.N-type light dope epitaxial loayer (not shown) can also be formed, for improving the puncture voltage of CDMOS product in the front of heavy doped conduction substrate 10.
Step b, oxygen pad layer 30 is formed at the front and back of N-type heavy doped conduction substrate 10 by thermal oxidation technology, physical deposition or chemical deposition process, then N-type heavy doped conduction substrate 10 is put into low pressure boiler tube, generate silicon nitride by dichlorosilane with ammonia gas react, oxygen pad layer 30 is formed silicon nitride layer 20.
Step c, the silicon nitride layer 20 in N-type heavy doped conduction substrate 10 front applies photoresist, then expose, development, forms photoresist reserve area and photoresist not reserve area, wherein, the region at photoresist not corresponding P type heavy doping buried regions 40 place of reserve area, then with silicon nitride layer 20 for mask, to the front doped with boron ion of heavy doped conduction substrate 10, form P type heavy doping buried regions 40.The silicon nitride layer 20 in N-type heavy doped conduction substrate 10 front is removed finally by dry etching.
Steps d, at the front doped with boron ion of N-type heavy doped conduction substrate 10, forms P type light dope epitaxial loayer 50.
Step e, is formed with source region, polycrystalline, N-type source and drain, P type source and drain, contact hole etc. in the front of N-type heavy doped conduction substrate 10, manufacture method existing very ripe in prior art, is not described in detail in this.
Step f, forms the drain metal layer (not shown) of VDMOS at the back side of N-type heavy doped conduction substrate 10.
Embodiment two
Based on same inventive concept, provide a kind of power IC device in the present embodiment, it comprises heavy doped conduction substrate and the metal level of the first conduction type, and doped with the first ion in described heavy doped conduction substrate, described metal level is formed in the back side of described heavy doped conduction substrate.Wherein, described first ion forms low contact resistance with contacting of metal level.
Technical scheme of the present invention, by changing the Doped ions of power IC device substrate, it is made to form low contact resistance with the contacting of metal level of backside of substrate, thus eliminate backside of substrate injection and annealing process, reduce the production cost of CDMOS product, shorten the fabrication cycle of CDMOS product.
Concrete, described metal level can be the drain electrode of VDMOS, by reducing the contact resistance of the first ion and metal level, and then can reduce VDMOS conducting resistance, improves the performance of CDMOS product.
Wherein, described heavy doped conduction substrate can select N type semiconductor substrate, can provide less conducting resistance for CDMOS product.
Further, when described semiconductor base is Si semiconductor substrate, described first ion can select arsenic ion, because the contact resistance of arsenic ion and metal level is only 1/5 of the contact resistance of antimony (Sb) ion and metal level, form low contact resistance, thus the conducting resistance of VDMOS can be reduced, improve the performance of CDMOS product.Meanwhile, inject with annealing process to reduce conducting resistance owing to not needing to increase backside of substrate, thus reduce the production cost of CDMOS product, shorten the fabrication cycle of CDMOS product.
Because CDMOS product can comprise P type CMOS, N-type CMOS, P type DMOS and N-type DMOS simultaneously, in order to form P type MOS and N-type MOS on the same base simultaneously, CDMOS product also needs the heavy doping buried regions comprising the second conduction type, is formed in the front of heavy doped conduction substrate.Further, in order to improve the puncture voltage of CDMOS, above the heavy doping buried regions of the second conduction type, be also formed with the light dope epitaxial loayer of the second conduction type.
For the N-type heavily doped silicon semiconductor base of arsenic doped ion, have an impact to prevent the light dope epitaxial loayer of the autodoping effect of arsenic ion to the second conduction type, preferably, the first barrier layer is formed between described heavy doped conduction substrate and described metal level, in the process of the light dope epitaxial loayer of formation second conduction type, first barrier layer can effectively prevent arsenic (AS) ion to be diffused in high temperature environments in surrounding environment, with reacting gas fused deposition to heavy doped conduction substrate front, affect the quality of the light dope epitaxial loayer of the second conduction type, thus prevent the autodoping effect of arsenic (AS) ion to have an impact to light dope epitaxial loayer.
Concrete, described first barrier layer can be the composite bed comprising silicon nitride layer and oxygen pad layer, and described oxygen pad layer is near the side of described heavy doped conduction substrate, for improving the stress of silicon nitride.
As shown in Figure 7, the power IC device in the present embodiment comprises:
The N-type heavily doped silicon semiconductor base 10 of arsenic doped ion, is formed with N-type light dope epitaxial loayer (not shown) in the front of N-type heavily doped silicon semiconductor base 10;
Be formed in the P type heavy doping buried regions 40 in N-type heavily doped silicon semiconductor base 10 front;
Be formed in the P type light dope epitaxial loayer 50 above P type heavy doping buried regions 40;
Be formed in the active area above P type light dope epitaxial loayer 50, polycrystalline, N-type source and drain, P type source and drain, contact hole etc.;
Be formed in the oxygen pad layer 30 at N-type heavily doped silicon semiconductor base 10 back side, silicon nitride layer 20 and metal level (not shown) successively.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite not departing from the technology of the present invention principle; can also make some improvement and replacement, these improve and replace and also should be considered as protection scope of the present invention.
Claims (10)
1. a manufacture method for power IC device, is characterized in that, comprising:
Adulterate the first ion in semiconductor base, forms the heavy doped conduction substrate of the first conduction type;
Metal level is formed at the back side of described heavy type doping substrate;
Wherein, described first ion forms low contact resistance with contacting of metal level.
2. manufacture method according to claim 1, is characterized in that, described semiconductor base is Si semiconductor substrate; Described first ion is arsenic ion.
3. manufacture method according to claim 1 and 2, is characterized in that, also comprises:
Between described heavy doped conduction substrate and described metal level, form the first barrier film, form the second barrier film in the front of described heavy doped conduction substrate;
Graphically described second barrier layer, forms the pattern on the second barrier layer;
With described second barrier layer pattern for mask, to adulterate the second ion to described heavy doped conduction substrate, form the heavy doping buried regions of the second conduction type;
Remove the second barrier layer;
The light dope epitaxial loayer of the second conduction type is formed above described heavy doping buried regions.
4. manufacture method according to claim 3, is characterized in that, forms described first barrier film and the second barrier film by one-time process;
The second barrier layer is removed by dry etching.
5. manufacture method according to claim 4, is characterized in that, described first barrier layer and the second barrier layer comprise silicon nitride layer and oxygen pad layer, and described oxygen pad layer is near the side of described heavy doped conduction substrate.
6. manufacture method according to claim 5, is characterized in that, forms described first barrier film and the second barrier film comprises by one-time process:
Oxygen pad layer is formed at the front and back of described heavy doped conduction substrate by thermal oxidation technology;
Described heavy doped conduction substrate is put into low pressure boiler tube, generates silicon nitride by dichlorosilane and ammonia gas react, described oxygen pad layer forms silicon nitride layer.
7. a power IC device, is characterized in that, comprising:
The heavy doped conduction substrate of the first conduction type, doped with the first ion in described heavy doped conduction substrate;
Metal level, is formed in the back side of described heavy type doping substrate;
Wherein, described first ion forms low contact resistance with contacting of metal level.
8. power IC device according to claim 7, is characterized in that, described semiconductor base is Si semiconductor substrate; Described first ion is arsenic ion.
9. the power IC device according to claim 7 or 8, is characterized in that, also comprises:
The heavy doping buried regions pattern of the second conduction type, is formed in the front of described heavy doped conduction substrate;
The light dope epitaxial loayer of the second conduction type, is formed in above described heavy doping buried regions;
First barrier layer, between described heavy doped conduction substrate and described metal level.
10. power IC device according to claim 9, is characterized in that, described first barrier layer comprises silicon nitride layer and oxygen pad layer, and described oxygen pad layer is near the side of described heavy doped conduction substrate.
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