CN101217159A - A ballasting resistor structure and manufacturing method of microwave power transistor dynamic emitter electrode - Google Patents
A ballasting resistor structure and manufacturing method of microwave power transistor dynamic emitter electrode Download PDFInfo
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- CN101217159A CN101217159A CNA2007101919812A CN200710191981A CN101217159A CN 101217159 A CN101217159 A CN 101217159A CN A2007101919812 A CNA2007101919812 A CN A2007101919812A CN 200710191981 A CN200710191981 A CN 200710191981A CN 101217159 A CN101217159 A CN 101217159A
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Abstract
The invention relates to a microwave power transistor dynamic emitter ballast resistor structure and the production method, the structure is that an active area is divided into two adjacent areas, the emitter ballast resistor is arranged between the two active areas, the emitter and a base electrode adopt two layers of metal wiring for being led out, and the two active areas share one ballast resistor. The invention has the advantages that: the active area is divided into two adjacent areas, the emitter ballast resistor is arranged between the two active areas, the emitter and the base electrode adopt two layers of metal wiring for being led out. The two active areas have full thermal coupling to the same ballast resistor, the increasing amplitude of the value of the ballast resistor is increased along with the increase of the temperature, the additional ballasting effect is increased and dynamic ballasting is realized. The two active areas share one ballast resistor so as to reduce the parasitic capacitance and the chip area of the ballast resistor. The heat dissipation boundary of the active areas is increased and the thermal resistance is reduced. The peak junction temperature of the chips with the same power and the ballast resistor is reduced by 15 DEG C to 20 DEG C. The invention can meet the requirements on the microwave performance and the reliability of a microwave power transistor.
Description
Technical field
What the present invention relates to is a kind of microwave power transistor dynamic emitter ballast resistor structure and production method, belongs to semiconductor microactuator Electronic Design manufacturing technology field.
Background technology
Emphasis that microwave power transistor manufactures and designs and difficult point mainly contain following three aspects: 1. overcome the adverse effect of microwave parasitic parameter, improve the microwave gain performance.2. overcome the big injection effect in base, improve power capacity, keep the microwave property under the high-power condition; 3. overcome the thermal effect that high-power applications is brought, improve transistorized long-term reliability.
Microwave power device usually is operated under the high power density condition, and efficient is lower during high frequency, and making dissipates increases, and produces very high junction temperature.Even input power density is even, in the same chip, the temperature of chip planar central is also the highest.Heat distribution inhomogeneities and base resistance automatic bias, knot planar defect etc. all can cause CURRENT DISTRIBUTION inhomogeneous, the inhomogeneities of CURRENT DISTRIBUTION is aggravated the inhomogeneities of heat distribution again conversely, final this vicious circle makes current concentration arrive a certain very little scope, form heat spot, the instantaneous fusing point that surpasses silicon chip of temperature, and PN junction generation heat is burnt, promptly so-called thermal breakdown or forward bias second breakdown.Thermal breakdown is one of principal element of high power device inefficacy.
The major measure that prevents the device thermal breakdown comprises two aspects: the first, improve heat conduction via, reduce thermal resistance, the heat that is beneficial to be produced in the chip is to outdiffusion; The second, diffusion resistance that is in series with emitter junction of design, promptly emitter ballast resistance improves the Temperature Distribution in the chip, finally reduces Peak Junction Temperature in the chip, suppresses the generation of forward bias second breakdown.The resistance of emitter ballast resistance is big more, and then Temperature Distribution is even more in the chip.But the existence of emitter ballast resistance can reduce transistorized microwave power gain; Simultaneously the PN junction of diffusion resistance has increased the parasitic capacitance of collector electrode to emitter, stable unfavorable to device work.
Existing emitter diffusion steady resistance generally designs at the one-sided edge of chip active area, and active area is insufficient to the thermal coupling of steady resistance, has limited additional ballast effect, and the existence of steady resistance has simultaneously increased collector electrode to the parasitic capacitance between the emitter.When carrying out the multiple-active-region design, each active area all must design a steady resistance, has increased the parasitic capacitance and the chip area of steady resistance, and the existence of emitter ballast resistance is favourable to device reliability, but gain has loss to the device microwave power.
Summary of the invention
The objective of the invention is to overcome the defective that prior art exists, a kind of microwave power transistor dynamic emitter ballast resistor structure and production method are proposed, the zone that active area is divided into two neighbours, emitter ballast resistance is placed between two active areas, and emitter and base electrode adopt the double-level-metal wiring to draw.Making on the one hand has sufficient thermal coupling between active area and the steady resistance, the amplitude that the steady resistance value is increased along with the temperature rising becomes big, makes full use of the additional ballast effect of bringing because of the steady resistance increase.Two shared steady resistances of active area can reduce the parasitic capacitance and the chip area of steady resistance.Also increase active area heat radiation border simultaneously, reduced the chip thermal resistance.
Technical solution of the present invention: its structure is the zone that active area is divided into two neighbours, and emitter ballast resistance places between two active areas, and emitter and base electrode adopt the double-level-metal wiring to draw two shared steady resistances of active area.
The production method of microwave power transistor dynamic emitter ballast resistor structure, its processing step is divided into,
(1) selects to mix arsenic silicon substrate, resistivity≤0.003 Ω cm; Extension is mixed phosphorus n type silicon epitaxy layer on this substrate, resistivity 0.75-1.5 Ω cm, epitaxy layer thickness 3 μ m-14 μ m;
(2) silicon chip after the cleaning, 1000 ℃-1150 ℃ of furnace temperature, and under the condition of logical dried oxygen, constant temperature 15 minutes-30 minutes, logical then chloroform or trichloroethylene 30 minutes-60 minutes, dried oxygen 10 minutes-20 minutes generates 900 dusts-1500 dust () silicon dioxide;
(3) adopting low-pressure chemical vapor phase deposition (LPCVD) process, is the silicon nitride (Si of 1000 -1700 at silicon chip surface deposit one layer thickness
3N
4);
(4) utilize the rotary spraying method, coating one deck is to the organic thin film of ultraviolet light sensitivity on epitaxial wafer; See through the table top mask with ultraviolet light then photoresist is carried out the selectivity exposure; Again the epitaxial wafer after the exposure is sprayed burn into and develop, remove the photoresist of exposure region, form photoresist masking table top figure;
(5) the photoresist figure that forms with step (4) technology is a masking film, the Si of dry etching exposed region
3N
4, Si
3N
4After etching is clean, expose silicon face, remove photoresist at last, obtain with Si
3N
4Be the table top figure of sheltering;
(6) be that 40 ℃ ± 2 ℃ silicon materials corrosive liquid corrosion silicon forms table top, shoulder height 0.4 μ m-0.6 μ m with bath temperature;
(7) under 1050 ℃-1150 ℃ temperature, logical successively dried oxygen 10 minutes-20 minutes, logical wet oxygen 80 minutes-100 minutes, logical dried oxygen 15 minutes-25 minutes, logical chloroform or trichloroethylene 30 minutes-60 minutes, logical dried oxygen 10 minutes-60 minutes, logical N
280 minutes-100 minutes, at the grow SiO of 8000 -9000 of mesa edge
2
(8) use hot phosphoric acid corrosion Si
3N
4, and with hydrofluoric acid (HF) corrosion Si
3N
4Following SiO2 exposes silicon face;
(9) photoetching forms steady resistance and base stage ohmic contact graph window, injects B
+Or BF
2 +, implantation dosage 1 * 10
15Cm
-2-5 * 10
15Cm
-2, energy 80KeV-120KeV;
(10) 1000 ℃ of short annealings in 10 seconds form steady resistance and base stage ohmic contact p
+District (Fig. 4 .10); Inject BF
2 +, implantation dosage 4 * 10
13Cm
-2-8 * 10
13Cm
-2, energy 40KeV-80KeV, and carry out 1000 ℃ of annealing in 10 seconds, form the base;
(11) use LPCVD technology at silicon chip surface difference deposit 1000 -2000 SiO
2With 1000 -1700 Si
3N
4Passivation layer;
(12) photoetching, etching Si
3N
4/ SiO
2, open emitter region doping window;
(13) LPCVD polysilicon membrane, thickness are 2000 -6000 , and polysilicon is carried out arsenic or phosphorus doping;
(14) anti-carve emitter-polysilicon, annealing is 20 minutes under 920 ℃-1000 ℃ and nitrogen protection condition, forms the n+ emitter region;
(15) photoetching and dry etching Si
3N
4/ SiO
2Form the base stage contact window;
(16) sputtered with Ti 500 -1500 /WN 1000 -3000 /Au 500 -1500 ; The photoetching electroplating region is selected electrogilding, thickness of coating 1.2 μ m-2.5 μ m; Anti-carve and form ground floor metal electrode, i.e. emitter and base stage;
(17) adopt plasma-reinforced chemical vapor deposition (PECVD) technology at silicon chip surface deposit 5000 -10000 silicon oxynitrides (SixOyNz) blending agent film, form the electrode isolation dielectric layer;
(18) photoetching and dry etching Si
xO
yN
zForm the second layer metal contact window;
(19) sputtered with Ti 500 -1500 /W 1000 -2000 /Au 500 -1500 ;
(20) the photoetching second layer metal is electroplated graph window, and window gold layer is electroplated to the 2-3 micron;
(21) photoetching second layer metal electrode anti-carves figure, and anti-carves formation second layer metal electrode, i.e. emitter and base stage;
(22) adopt plasma-reinforced chemical vapor deposition (PECVD) technology at silicon chip surface deposit 2000 -5000 silicon oxynitrides (SixOyNz) blending agent film, form the electrode passivation dielectric layer;
(23). photoetching second layer metal electrode bonding graph window, and dry etching exposes second layer metal electrode bonding window;
(24) adopt surface grinding machine that silicon chip is carried out back side abrasive disc, with wafer thinning to 80 μ m-100 μ m; Silicon chip is carried out toluene successively soak heated wash and acetone immersion heated wash; Evaporation Ti 500 -1500 /Ni 3000 -5000 /Au 3000 -5000 is formed bottom electrode, i.e. collector electrode.
Beneficial effect of the present invention: active area is divided into two neighbours' zone, emitter ballast resistance is placed between two active areas, emitter and base electrode adopt the double-level-metal wiring to draw.Make two active areas to same steady resistance sufficient thermal coupling be arranged on the one hand, the amplitude that the steady resistance value is increased along with the temperature rising becomes big, increases and adds the ballast effect, realizes dynamic ballast.Two shared steady resistances of active area can reduce the parasitic capacitance and the chip area of steady resistance.Increase active area heat radiation border simultaneously, reduce thermal resistance.After adopting this technology, with the chip of constant power and steady resistance, under identical condition of work, Peak Junction Temperature descends 15 ℃-20 ℃.Satisfy the requirement of microwave power transistor preferably to microwave property and reliability.
Description of drawings
Accompanying drawing 1 is existing single active area transistor generalized section.
Accompanying drawing 2 is existing two active area transistor generalized sections,
Accompanying drawing 3 is dynamic emitter steady resistance transistor generalized sections of the present invention.
Accompanying drawing 4 is generalized sections of the silicon epitaxial wafer of (111) crystal face;
Accompanying drawing 6 is that ultraviolet light sees through the table top reticle is carried out the selectivity exposure to photoresist generalized section;
Accompanying drawing 7 be with photoresist figure for sheltering, to silicon nitride (Si
3N
4) generalized section of carrying out selective reaction ion etching;
Accompanying drawing 8 is etching Si
3N
4, and the silicon chip generalized section behind the removal photoresist masking figure;
Accompanying drawing 9 is with Si
3N
4Be mask, selective corrosion silicon, the generalized section of formation table top;
Accompanying drawing 10 is with Si
3N
4Be mask, silicon chip carried out selective oxidation generate silicon dioxide (SiO
2) generalized section;
Accompanying drawing 11 is wet etching Si
3N
4After generalized section;
Accompanying drawing 12 is for sheltering the generalized section that base stage contact zone and steady resistance regioselectivity ion inject with photoresist;
Accompanying drawing 13 is base stage contact zone P that annealing advances the back to form
+Mix and steady resistance district P
+The doping generalized section;
Accompanying drawing 14 is to inject BF
2 +And annealing forms the generalized section of p type base;
Accompanying drawing 15 is LPCVD SiO
2/ Si
3N
4Generalized section;
Accompanying drawing 16 is etching SiO
2/ Si
3N
4, form the launch hole generalized section; P is the base; n
++The expression silicon substrate; N is a silicon epitaxy layer;
Accompanying drawing 17 is generalized sections of LPCVD arsenic-doped polysilicon;
Accompanying drawing 19 is that chemical wet etching forms base stage contact window and steady resistance contact window generalized section;
Accompanying drawing 20 is ground floor electrode generalized sections;
Accompanying drawing 21 is metal electrode spacer medium film deposit generalized sections;
Accompanying drawing 22 is second layer metal electrode contact window generalized sections;
Accompanying drawing 23 is second layer metal electrode generalized sections;
Accompanying drawing 24 is metal electrode passivation window generalized sections;
Accompanying drawing 25 is thinning back side and collector electrode metal generalized section.
Embodiment
Among the figure 1 is the base metal pressure welding area; The 2nd, n+ doping emitter region, p type base that the emitter region is corresponding with it and n type collector region constitute the source region jointly; The 3rd, the passivation of metal surfaces deielectric-coating; The 4th, P
+The emitter ballast resistance district of mixing, thickness 1 μ m-2 μ m; The 5th, the emitter metal pressure welding area; The 6th, collector electrode; n
++Be silicon substrate.P district thickness is 0.3 μ m-0.4 μ m; n
+District's thickness is 0.1 μ m-0.2 μ m; N type silicon epitaxy layer thickness is 3 μ m-14 μ m; n
++Silicon substrate material thickness is 380 μ m-560 μ m.The 7th, the spacer medium film between the double-level-metal; The 8th, the passivation of metal surfaces layer.The 9th, the interconnecting metal of emitter window and steady resistance window; The 10th, n
+The emitter region, n
+P type base that the emitter region is corresponding with it and n type collector region constitute the source region jointly; n
++Silicon substrate material thickness is 380 μ m-560 μ m.The 11st, ultraviolet light, the 12nd, mask, the 13rd, photoresist, the 14th, reactive ion, the 15th, table top, the 16th, ion injects, the 17th, arsenic-doped polysilicon, the 18th, steady resistance, the 19th, launch hole, the 20th, base stage contact zone, the 21st, emitter-polysilicon, the 22nd, steady resistance contact hole, the 23rd, steady resistance contacting metal, the 24th, emitter and steady resistance interconnecting metal, the 25th, base metal, the 26th, spacer medium, the 27th, second layer emitter metal contact window; The 28th, second layer base metal contact window; The 29th, second layer emitter metal; The 30th, second layer base metal; The 31st, emitter bonding window; The 32nd, base metal bonding window.
Contrast accompanying drawing 1 comprises an active area and an emitter ballast resistance in the chip, steady resistance is positioned at active area one side.The heat that active area produces is diffused into steady resistance from a side of steady resistance, and active area is insufficient to the thermal coupling of steady resistance.
Contrast accompanying drawing 2 comprises two active areas and two emitter ballast resistances in the chip; Steady resistance is positioned at two active area outsides;
Contrast accompanying drawing 3, comprise two neighbours' active area in the chip, an emitter ballast resistance.Emitter ballast resistance is positioned in the middle of two active areas, two shared same emitter ballast resistances of active area.Emitter and base electrode adopt the double-level-metal wiring to draw.The heat of two active area generations is diffused into steady resistance from the both sides of steady resistance simultaneously, and active area is abundant to the thermal coupling of steady resistance, and the parasitic capacitance of steady resistance is less in the chip.
Contrast accompanying drawing 4, silicon substrate is mixed arsenic, and resistivity≤0.003 Ω cm is used n
++Expression, thickness is 380 μ m-560 μ m; Extension is mixed phosphorus n type silicon epitaxy layer on this substrate, and resistivity 0.75 Ω cm-1.5 Ω cm represents with n, epitaxy layer thickness 3 μ m-14 μ m; 1) selects to mix arsenic silicon substrate, resistivity≤0.003 Ω cm; Extension is mixed phosphorus n type silicon epitaxy layer on this substrate, resistivity 0.75 Ω cm-1.5 Ω cm, epitaxy layer thickness 3 μ m-14 μ m, the silicon chip after the cleaning is 1000 ℃-1150 ℃ of furnace temperature, and under the condition of logical dried oxygen, constant temperature 15 minutes-30 minutes, logical then chloroform or trichloroethylene 30 minutes-60 minutes, dried oxygen 10 minutes-20 minutes, generate 900 dusts-1500 dust () silicon dioxide
Contrast accompanying drawing 5, n
++The expression silicon substrate; N is a silicon epitaxy layer; 3) adopting low-pressure chemical vapor phase deposition (LPCVD) process, is the silicon nitride (Si of 1000 -1700 at silicon chip surface deposit one layer thickness
3N
4),
Contrast accompanying drawing 6, n
++The expression silicon substrate; N is a silicon epitaxy layer; Utilize the rotary spraying method, on epitaxial wafer coating one deck to the organic thin film of ultraviolet light sensitivity, i.e. photoresist, the about 2 μ m of thickness; See through the table top mask with ultraviolet light then photoresist is carried out the selectivity exposure; Again the epitaxial wafer after the exposure is sprayed burn into and develops, remove the photoresist of exposure region, form photoresist masking table top figure,
Contrast accompanying drawing 7, n
++The expression silicon substrate; N is a silicon epitaxy layer; 5) with processing step 4) the photoresist figure that forms is masking film, the Si of dry etching exposed region
3N
4
Contrast accompanying drawing 8, n
++The expression silicon substrate; N is a silicon epitaxy layer; Si
3N
4After etching is clean, expose silicon face, remove photoresist at last, obtain with Si
3N
4Be the table top figure of sheltering, contrast accompanying drawing 9, the table top degree of depth 0.4 μ m-0.6 μ m micron; n
++The expression silicon substrate; N is a silicon epitaxy layer;
Contrast accompanying drawing 10, n
++The expression silicon substrate; N is a silicon epitaxy layer; Under 1050 ℃-1150 ℃ temperature, logical successively dried oxygen 10 minutes-20 minutes, logical wet oxygen 80 minutes-100 minutes, logical dried oxygen 15 minutes-25 minutes, logical chloroform or trichloroethylene 30 minutes-60 minutes, logical dried oxygen 10 minutes-60 minutes, logical N
280 minutes-100 minutes, at the grow SiO of 8000 -8000 of mesa edge
2,
Contrast accompanying drawing 11, n
++The expression silicon substrate; N is a silicon epitaxy layer; 8) use hot phosphoric acid corrosion Si
3N
4, and with hydrofluoric acid (HF) corrosion Si
3N
4Following SiO
2, expose silicon face,
Contrast accompanying drawing 12, n
++The expression silicon substrate; N is a silicon epitaxy layer; 9) photoetching forms steady resistance and base stage ohmic contact graph window, injects B
+(or BF
2 +), implantation dosage 1 * 10
15Cm
-2-5 * 10
15Cm
-2, energy 80KeV-120KeV,
Contrast accompanying drawing 13, n
++The expression silicon substrate; N is a silicon epitaxy layer; 10) 1000 ℃ of short annealings in 10 seconds form steady resistance and base stage ohmic contact p
+The district;
Contrast accompanying drawing 14, n is a silicon epitaxy layer; Inject BF
2 +, implantation dosage 4 * 10
13Cm
-2-8 * 10
13Cm
-2, energy 40KeV-80KeV, and carry out 1000 ℃ of 10S annealing, form the base,
Contrast accompanying drawing 15, n
++The expression silicon substrate; N is a silicon epitaxy layer; Distinguish deposit 1000 -2000 SiO with LPCVD technology at silicon chip surface
2With 1000 -1700 Si
3N
4Passivation layer,
Contrast accompanying drawing 16, n is a silicon epitaxy layer; 12) photoetching, etching SiO
2/ Si
3N
4Open emitter region doping window,
Contrast accompanying drawing 17, n is a silicon epitaxy layer; 13) LPCVD polysilicon membrane, thickness are 2000 -6000 , and polysilicon is carried out arsenic or phosphorus doping,
Contrast accompanying drawing 18, p is the base; n
++The expression silicon substrate; N is a silicon epitaxy layer; 14) anti-carve emitter-polysilicon, annealing is 20 minutes under 920 ℃-1000 ℃ and nitrogen protection condition, forms n
+The emitter region, contrast accompanying drawing 19, n
+Be the emitter region; P is the base; n
++The expression silicon substrate; N is a silicon epitaxy layer; 15) photoetching and dry etching Si
3N
4/ SiO
2Form the base stage contact window,
Contrast accompanying drawing 20, n is a silicon epitaxy layer; 16) sputtered with Ti 500 -1500 /WN 1000 -3000 /Au500 -1500 ; The photoetching electroplating region is selected electrogilding, plated thickness 1.2 μ m-2.5 μ m; Anti-carve and form the ground floor metal electrode, i.e. emitter E and base stage B,
Contrast accompanying drawing 21, p is the base; n
++The expression silicon substrate; N is a silicon epitaxy layer; 17) adopt plasma-reinforced chemical vapor deposition (PECVD) technology at silicon chip surface deposit 5000 -10000 silicon oxynitride (Si
xO
yN
z) the blending agent film, form the electrode isolation dielectric layer,
Contrast accompanying drawing 22, n
+Be the emitter region; P is the base; n
++The expression silicon substrate; N is a silicon epitaxy layer; 18) photoetching and dry etching Si
xO
yN
zForm the second layer metal contact window,
Contrast accompanying drawing 23, p is the base; n
++The expression silicon substrate; N is a silicon epitaxy layer; 19) sputter second layer metal film; 21) photoetching second layer metal electrode anti-carves figure, and anti-carves and form the second layer metal electrode, i.e. emitter and base stage, 22) adopt plasma-reinforced chemical vapor deposition (PECVD) technology at silicon chip surface deposit 2000 -5000 silicon oxynitride (Si
xO
yN
z) the blending agent film, form the electrode passivation dielectric layer,
Contrast accompanying drawing 24, n
+Be the emitter region; P is the base; n
++The expression silicon substrate; N is a silicon epitaxy layer; 23) photoetching second layer metal electrode bonding graph window, and dry etching exposes second layer metal electrode bonding window,
Contrast accompanying drawing 25, n
+Be the emitter region; P is the base; n
++The expression silicon substrate; N is a silicon epitaxy layer; 24) adopt surface grinding machine that silicon chip is carried out back side abrasive disc, with wafer thinning to 80 μ m-100 μ m; Silicon chip is carried out toluene and acetone successively to be cleaned; Evaporation Ti 500 -1500 /Ni 3000 -5000 /Au3000 -5000 is formed bottom electrode, i.e. collector electrode.
Pure semi-conducting material is nonconducting insulator, and when mixing certain impurity element in the semi-conducting material, its conductive capability can increase several magnitude, show excellent conducting performance.For semiconductor silicon, when doped chemical is one or more elements in boron, the aluminium etc., show as movable positive charged particles conduction, this based semiconductor is called as P type (p type) semiconductor.When doped chemical is one or more elements in phosphorus, arsenic, the antimony etc., show as movable negative electrical charge particle conductive, this based semiconductor is called as N type semiconductor.Doped chemical concentration is high more, and then movable conducting particles concentration is high more, and conductive capability is strong more.Usually use P
-, P
-, P, P
+, P
++And N
--, N
-, N, N
+, N
++The height of doping content in the difference qualitative representation semiconductor.All show as electric neutrality on N type (n type) semiconductor and P type (p type) the semiconductor macroscopic view.
The metallurgical interface that P type semiconductor and N type semiconductor are closely linked is become PN junction.In certain zone, positive and negative movable conducting particles concentration is zero near the PN junction both sides, and this zone is called as depletion region.P type semiconductor one side depletion region presents is with immovable negative electrical charge, and N type semiconductor one side depletion region presents is with immovable positive charge.The side width of depletion region that PN junction both sides doping content is low is wide, and the high side width of depletion region of doping content is narrow.The not removable positive and negative charge number of PN junction both sides equates, still shows as electric neutrality on together the two kinds of semiconductor macroscopic views of combining.
In transistor when work,, emitter junction adds forward bias voltage, when this voltage during greater than the cut-in voltage of emitter junction, forms bigger forward conduction electric current; Collector junction adds reverse bias voltage, because base width is thinner, base resistance be can not ignore simultaneously, makes emitter junction overwhelming majority forward conduction electric current be collected away by collector junction, forms collector current.And the electric current that flows to base loop is very little.The ratio of collector current and base current is exactly transistorized dc amplification factor.Be added to the minor variations of the voltage on the emitter junction,, all can make emitter current that bigger variation takes place perhaps because the active area variation of temperature makes emitter junction cut-in voltage minor variations.Power transistor operating current temperature instability causes device to burn easily, must overcome, and prevents chip because electric current increases, power consumption increases and overheated burning.
Emitter ballast resistance is connected on the transistorized emitter junction by metal line, when the electric current by emitter junction increases, voltage drop on this series resistance increases, be added in the corresponding minimizing of forward voltage on the emitter junction, make emitter junction forward conduction electric current reduce, limit the rising of collector electrode operating current, thereby reached the purpose of steady operation electric current (ballast).
During the transistor operate as normal,, the difference of source heat-dissipating boundary condition is arranged even the electric current in the active area evenly distributes, high in the middle of the temperature in the active area presents, low all around distribution.Therefore wish that at Temperature Distribution, the design steady resistance closes CURRENT DISTRIBUTION, improves the uniformity of Temperature Distribution.
Claims (2)
1. microwave power transistor dynamic emitter ballast resistor structure, it is characterized in that active area is divided into two neighbours' zone, emitter ballast resistance places between two active areas, emitter and base electrode adopt the double-level-metal wiring to draw two shared steady resistances of active area.
2. the production method of microwave power transistor dynamic emitter ballast resistor structure is characterized in that the processing step of this method is divided into,
(1) selects to mix arsenic silicon substrate, resistivity≤0.003 Ω cm; Extension is mixed phosphorus n type silicon epitaxy layer on this substrate, resistivity 0.75-1.5 Ω cm, epitaxy layer thickness 3 μ m-14 μ m;
(2) silicon chip after the cleaning, 1000 ℃-1150 ℃ of furnace temperature, and under the condition of logical dried oxygen, constant temperature 15 minutes-30 minutes, logical then chloroform or trichloroethylene 30 minutes-60 minutes, dried oxygen 10 minutes-20 minutes generates 900 dusts-1500 dust () silicon dioxide;
(3) adopting the low-pressure chemical vapor phase deposition process, is the silicon nitride of 1000 -1700 at silicon chip surface deposit one layer thickness;
(4) utilize the rotary spraying method, coating one deck is to the organic thin film of ultraviolet light sensitivity on epitaxial wafer; See through the table top mask with ultraviolet light then photoresist is carried out the selectivity exposure; Again the epitaxial wafer after the exposure is sprayed burn into and develop, remove the photoresist of exposure region, form photoresist masking table top figure;
(5) the formed photoresist figure of processing step (4) is a masking film, the Si of dry etching exposed region
3N
4After etching is clean, expose silicon face, remove photoresist at last, obtain with Si
3N
4Be the table top figure of sheltering;
(6) be that 40 ℃ ± 2 ℃ silicon materials corrosive liquid corrosion silicon forms table top, shoulder height 0.4 μ m-0.6 μ m with bath temperature;
(7) under 1050 ℃-1150 ℃ temperature, logical successively dried oxygen 10 minutes-20 minutes, logical wet oxygen 80 minutes-100 minutes, logical dried oxygen 15 minutes-25 minutes, logical chloroform or trichloroethylene 30 minutes-60 minutes, logical dried oxygen 10 minutes-60 minutes, logical N
280 minutes-100 minutes, at the grow SiO of 8000 -9000 of mesa edge
2
(8) use hot phosphoric acid corrosion Si
3N
4, and the SiO2 below hydrofluoric acid corrosion Si3N4, expose silicon face;
(9) photoetching forms steady resistance and base stage ohmic contact graph window, injects B
+Or BF
2 +, implantation dosage 1 * 10
15Cm
-2-5 * 10
15Cm
-2, energy 80KeV-120KeV;
(10) temperature is 1000 ℃, and 10 seconds time, short annealing forms steady resistance and base stage ohmic contact p
+The district; Inject BF
2 +, implantation dosage 4 * 10
13Cm
-2-8 * 10
13Cm
-2, energy 40KeV-80KeV, and carry out 1000 ℃ of annealing in 10 seconds, form the base;
(11) use LPCVD technology at silicon chip surface difference deposit 1000 -2000 SiO
2With 1000 -1700 Si
3N
4Passivation layer;
(12) photoetching, etching SiO
2/ Si
3N
4Open emitter region doping window;
(13) LPCVD polysilicon membrane, thickness are 2000 -6000 , and polysilicon is carried out arsenic or phosphorus doping;
(14) anti-carve emitter-polysilicon, annealing is 20 minutes under 920 ℃-1000 ℃ and nitrogen protection condition, forms the n+ emitter region;
(15) photoetching and dry etching Si
3N
4/ SiO
2Form the base stage contact window;
(16) sputtered with Ti 500 -1500 /WN 1000 -3000 /Au 500 -1500 ; The photoetching electroplating region, electrogilding thickness of coating 1.2 μ m-2.5 μ m; Anti-carve and form ground floor metal electrode, i.e. emitter and base stage;
(17) adopt plasma-reinforced chemical vapor deposition process at silicon chip surface deposit 5000 -10000 silicon oxynitride blending agent film, form the electrode isolation dielectric layer;
(18) photoetching and dry etching Si
xO
yN
zForm the second layer metal contact window;
(19) sputtered with Ti 500 -1500 /W 1000 -2000 /Au 500 -1500 ;
(20) the photoetching second layer metal is electroplated graph window, and window gold layer is electroplated to the 2-3 micron;
(21) photoetching second layer metal electrode anti-carves figure, and anti-carves formation second layer metal electrode, i.e. emitter and base stage;
(22) adopt plasma-reinforced chemical vapor deposition process at silicon chip surface deposit 2000 -5000 silicon oxynitride blending agent film, form the electrode passivation dielectric layer;
(23). photoetching second layer metal electrode bonding graph window, and dry etching exposes second layer metal electrode bonding window;
(24) adopt surface grinding machine that silicon chip is carried out back side abrasive disc, with wafer thinning to 80 μ m-100 μ m; Silicon chip is carried out toluene successively soak heated wash, acetone immersion heated wash; Evaporation Ti 500 -1500 /Ni 3000 -5000 /Au 3000 -5000 is formed bottom electrode, i.e. collector electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101919812A CN100533761C (en) | 2007-12-28 | 2007-12-28 | A ballasting resistor structure of microwave power transistor dynamic emitter electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101919812A CN100533761C (en) | 2007-12-28 | 2007-12-28 | A ballasting resistor structure of microwave power transistor dynamic emitter electrode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101217159A true CN101217159A (en) | 2008-07-09 |
| CN100533761C CN100533761C (en) | 2009-08-26 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2007101919812A Expired - Fee Related CN100533761C (en) | 2007-12-28 | 2007-12-28 | A ballasting resistor structure of microwave power transistor dynamic emitter electrode |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103258848A (en) * | 2013-05-13 | 2013-08-21 | 电子科技大学 | Insulated gate bipolar transistor (IGBT) device with positive temperature coefficient emitter ballast resistance |
| CN104810363A (en) * | 2014-01-26 | 2015-07-29 | 北大方正集团有限公司 | Power integrated device and manufacture method thereof |
| CN105489640A (en) * | 2015-12-18 | 2016-04-13 | 中国电子科技集团公司第五十五研究所 | Structure and technique for emitter secondary ballasting and emitter crowding effect reduction |
| CN106920835A (en) * | 2017-03-31 | 2017-07-04 | 李思敏 | There is no the gate associated transistor of polysilicon emitter |
| CN111624710A (en) * | 2020-04-27 | 2020-09-04 | 联合微电子中心有限责任公司 | Waveguide device and method of forming the same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2743675C1 (en) * | 2020-06-22 | 2021-02-24 | федеральное государственное бюджетное образовательное учреждение высшего образования "Воронежский государственный университет" (ФГБОУ ВО "ВГУ") | Powerful hf- and microwave transistor structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3936863A (en) * | 1974-09-09 | 1976-02-03 | Rca Corporation | Integrated power transistor with ballasting resistance and breakdown protection |
-
2007
- 2007-12-28 CN CNB2007101919812A patent/CN100533761C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103258848A (en) * | 2013-05-13 | 2013-08-21 | 电子科技大学 | Insulated gate bipolar transistor (IGBT) device with positive temperature coefficient emitter ballast resistance |
| CN103258848B (en) * | 2013-05-13 | 2015-06-17 | 电子科技大学 | Insulated gate bipolar transistor (IGBT) device with positive temperature coefficient emitter ballast resistance |
| CN104810363A (en) * | 2014-01-26 | 2015-07-29 | 北大方正集团有限公司 | Power integrated device and manufacture method thereof |
| CN105489640A (en) * | 2015-12-18 | 2016-04-13 | 中国电子科技集团公司第五十五研究所 | Structure and technique for emitter secondary ballasting and emitter crowding effect reduction |
| CN105489640B (en) * | 2015-12-18 | 2018-05-04 | 中国电子科技集团公司第五十五研究所 | The structure and process of the secondary ballast of emitter and reduction emitter collection side effect |
| CN106920835A (en) * | 2017-03-31 | 2017-07-04 | 李思敏 | There is no the gate associated transistor of polysilicon emitter |
| CN111624710A (en) * | 2020-04-27 | 2020-09-04 | 联合微电子中心有限责任公司 | Waveguide device and method of forming the same |
| CN111624710B (en) * | 2020-04-27 | 2022-06-10 | 联合微电子中心有限责任公司 | Waveguide device and method of forming the same |
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| Publication number | Publication date |
|---|---|
| CN100533761C (en) | 2009-08-26 |
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Assignee: Nanjing GEC Electonics Co., Ltd. Assignor: No.55 Inst., China Electronic Science and Technology Group Corp. Contract record no.: 2011320000856 Denomination of invention: A ballasting resistor structure and manufacturing method of microwave power transistor dynamic emitter electrode Granted publication date: 20090826 License type: Exclusive License Open date: 20080709 Record date: 20110621 |
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