CN104810363B - Power IC device and preparation method thereof - Google Patents
Power IC device and preparation method thereof Download PDFInfo
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- CN104810363B CN104810363B CN201410037708.4A CN201410037708A CN104810363B CN 104810363 B CN104810363 B CN 104810363B CN 201410037708 A CN201410037708 A CN 201410037708A CN 104810363 B CN104810363 B CN 104810363B
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Abstract
The present invention relates to technical field of semiconductors, discloses a kind of power IC device and preparation method thereof.By varying the Doped ions of power IC device substrate, its contact with the metal layer of backside of substrate is set to form low contact resistance, so as to eliminate backside of substrate injection and annealing process, the production cost of CDMOS products is reduced, shortens the fabrication cycle of CDMOS products.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of power IC device and preparation method thereof.
Background technology
With the development of science and technology the high-tech intelligent integrated circuit speed of development is getting faster, this industry development is promoted
Power be exactly it is desirable to life it is convenient, this just needs many tube core originally being integrated on a package module, this
Sample can play small-sized easily purpose, and it is exactly so-called power IC device to be sub-divided into semiconductor applications（CDMOS）.
CDMOS can be by function logic module（CMOS）With high-voltage power module（DMOS）It is integrated on a package module, greatly
Improve the integrated level of device.
Traditional CDMOS products are all the formation CMOS and DMOS in the substrate of a heavy doping.Due to the conduction of N-type substrate
Ion is electronics, and facing conductive ion is the P-type substrate in hole, its conductive capability is stronger, and wide applying is produced in CDMOS
Product.In existing production technology, N-type substrate is generally antimony（Sb）Doping, but the metal layer of antimony and backside of substrate（As DMOS's
Drain electrode）Contact resistance it is very big, in order to reduce contact resistance, and then reduce conducting resistance, needed before drain metal layer is made
Increase back side injection and annealing process, but so but add the production cost of CDMOS products, extend CDMOS products
Fabrication cycle.
With reference to shown in Fig. 1-Fig. 3, the specific production process of CDMOS products is in the prior art：
1st, antimony dopant forms 10 ＇ of N-type substrate of heavy doping in silicon semiconductor, and is given birth in the front doping phosphorus of 10 ＇ of substrate
Long one layer of initial epitaxial layer（Not shown in figure）；
2nd, substrate is placed on full of dichlorosilane with the low pressure boiler tube of ammonia, being reacted by dichlorosilane with ammonia
The front and back of substrate grows one layer of 20 ＇ of silicon nitride medium film；Because the stress of silicon nitride is very big, sliver is easily produced,
In order to improve the stress of silicon nitride, formed in substrate before 20 ＇ of silicon nitride medium film, can also be by thermal oxidation technology in base
The front and back of 10 ＇ of bottom generates one layer thin of 30 ＇ of pad oxygen medium film；
3rd, the positive silicon nitrides of 10 ＇ of graphical substrate and pad oxygen composite bed, form the pattern of composite bed, and with described compound
The pattern of layer be mask, 40 ＇ of p type buried layer of Doped ions formation CDMOS in basad 10 ＇；
4th, wet etching is carried out with hot phosphoric acid, removes the silicon nitride and pad oxygen composite bed of 10 ＇ front and backs of substrate completely；
5th, in thin 50 ＇ of epitaxial layer of one layer of the positive regrowth of 10 ＇ of substrate, the making of CDMOS product buried regions is so far completed；
6 and then start the making of active area, polycrystal layer, N-type source and drain, p-type source and drain, contact hole etc., be to show in figure；
7th, back side injection and annealing are done；
8th, drain metal layer is formed at the back side of substrate 10（Not shown in figure）.
The content of the invention
The present invention provides a kind of power IC device and preparation method thereof, to before solving to make backside of substrate metal layer
Need to increase back side injection and annealing process, to reduce the contact resistance of substrate Doped ions and metal layer, but add
The production cost of CDMOS products, the problem of extending the fabrication cycle of CDMOS products.
In order to solve the above technical problems, the present invention provides a kind of production method of power IC device, including：
The first ion is adulterated into semiconductor base, forms the heavy doped conduction substrate of the first conduction type；
Metal layer is formed at the back side of the heavy doping substrate；
Wherein, contact of first ion with metal layer forms low contact resistance.
Meanwhile the present invention also provides a kind of power IC device, including：
The heavy doped conduction substrate of first conduction type, doped with the first ion in the heavy doped conduction substrate；
Metal layer, is formed in the back side of the heavy doping substrate；
Wherein, contact of first ion with metal layer forms low contact resistance.
The above-mentioned technical proposal of the present invention has the beneficial effect that：
In above-mentioned technical proposal, by varying the Doped ions of power IC device substrate, make the gold of itself and backside of substrate
The contact for belonging to layer forms low contact resistance, so as to eliminate backside of substrate injection and annealing process, reduces the life of CDMOS products
Cost is produced, shortens the fabrication cycle of CDMOS products.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is attached drawing needed in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, without having to pay creative labor, may be used also
To obtain other attached drawings according to these attached drawings.
Fig. 1-Fig. 3 represents the manufacturing process schematic diagram of power IC device in the prior art；
Fig. 4 represents the production process figure of power IC device in the embodiment of the present invention；
Fig. 5-Fig. 7 represents the manufacturing process schematic diagram of power IC device in the embodiment of the present invention.
Embodiment
Below in conjunction with drawings and examples, the embodiment of the present invention is described in further detail.Following reality
Apply example to be used to illustrate the present invention, but be not limited to the scope of the present invention.
For CDMOS products, it includes being integrated in CMOS and DMOS in substrate.Except the drain electrode of VDMOS is formed in base
Outside the back side at bottom, the other structures of CDMOS（Including active area, p-type source and drain, N-type source and drain, polycrystal layer, contact hole etc.）It is respectively formed
In the front of substrate.
Wherein, according to the difference of Doped ions, substrate is divided into P-type substrate and N-type substrate, due to N-type substrate it is conductive from
Son is electronics, and facing conductive ion is the P-type substrate in hole, its conductive capability is stronger, is widely used in CDMOS products.
In existing production technology, N-type substrate is generally antimony（Sb）Doping, but the contact resistance of the drain metal layer of antimony and backside of substrate
It is very big.In order to reduce contact resistance, and then reduce the conducting resistance of VDMOS, need increase to carry on the back before drain metal layer is made
Face is injected and annealing process.But the production cost of CDMOS products is so but added, extend the making week of CDMOS products
Phase.
Embodiment one
As shown in figure 4, in order to solve the above-mentioned technical problem, in the present embodiment provide a kind of making side of power IC device
Method, including：
Step S1, the first ion is adulterated into semiconductor base, forms the heavy doped conduction substrate of the first conduction type；
Step S2, metal layer is formed at the back side of the heavy doping substrate；
Wherein, contact of first ion with metal layer forms low contact resistance.
In above-mentioned technical proposal, by varying the Doped ions of power IC device substrate, make the gold of itself and backside of substrate
The contact for belonging to layer forms low contact resistance, so as to eliminate backside of substrate injection and annealing process, reduces the life of CDMOS products
Cost is produced, shortens the fabrication cycle of CDMOS products.
Specifically, the heavy doped conduction substrate can select N-type semiconductor substrate, smaller can be provided for CDMOS products
Conducting resistance.
Further, when the semiconductor base is silicon semiconductor substrate, first ion can select arsenic（As）
Ion, because the contact resistance of arsenic ion and metal layer is only antimony（Sb）The 1/5 of the contact resistance of ion and metal layer, forms low
Contact resistance, so as to reduce the conducting resistance of VDMOS, improves the performance of CDMOS products.Simultaneously as it need not increase
Backside of substrate is injected with annealing process to reduce conducting resistance, so as to reduce the production cost of CDMOS products, is shortened
The fabrication cycle of CDMOS products.
Since CDMOS products can include p-type CMOS, N-type CMOS, p-type DMOS and N-type DMOS at the same time, in order to same
P-type MOS is formed in substrate at the same time and N-type MOS, CDMOS product also needs to the heavy doping buried regions that includes the second conduction type.Into one
Step ground, in order to improve the breakdown voltage of CDMOS, the second conduction type is formed in the top of the heavy doping buried regions of the second conduction type
Lightly doped epitaxial layer.
N-type heavily doped silicon semiconductor base for adulterating arsenic ion, since the atomic weight of arsenic ion is lighter, leads second
In the forming process of the lightly doped epitaxial layer of electric type, hot environment can cause arsenic ion to be diffused into surrounding air, with reaction
Gas fused deposition influences the resistivity value and uniformity of lightly doped epitaxial layer, produces auto-dope to the front of heavy doped conduction substrate
Effect.
The autodoping effect of arsenic ion has an impact lightly doped epitaxial layer in order to prevent, it is preferred that passes through following steps
Form the heavy doping buried regions and lightly doped epitaxial layer with conduction type：
The first barrier film is formed between the heavy doped conduction substrate and the metal layer, in the heavy doped conduction substrate
Front forms the second barrier film；
Graphical second barrier layer, forms the pattern on the second barrier layer；
Using second barrier layer pattern as mask, the second ion is adulterated to the heavy doped conduction substrate, it is conductive to form second
The heavy doping buried regions of type；
Remove the second barrier layer.
Heavy doping buried regions, and the conductive-type of heavy doping buried regions can be formed by above-mentioned steps in the front of heavy doped conduction substrate
Type is different from the conduction type of heavy doped conduction substrate.Such as：For N-type heavy doped conduction substrate, p-type heavy doping buried regions, institute are formed thereon
Boron ion can be selected by stating the second ion.
Then, the lightly doped epitaxial layer of the second conduction type, its conduction type are formed in the top of the heavy doping buried regions
It is identical with the conduction type of heavy doping buried regions.Due between heavy doped conduction substrate and metal layer formed with the first barrier layer, in shape
Into in the lightly doped epitaxial layer of the second conduction type, the first barrier layer can effectively prevent arsenic（AS）Ion expands in high temperature environments
It is scattered in surrounding environment, with reacting gas fused deposition to heavy doped conduction substrate front, it is outer influences being lightly doped for the second conduction type
Prolong the quality of layer, so as to prevent arsenic（AS）The autodoping effect of ion has an impact lightly doped epitaxial layer.
The first barrier film and the second barrier film are formed by one-time process at the same time in the present embodiment, to simplify work
Skill process, and in the technique on graphical second barrier layer, the second barrier layer is removed by dry etching, so as to protect
First barrier layer at the heavy doped conduction substrate back side is stayed, prevents arsenic（AS）The autodoping effect of ion produces shadow to lightly doped epitaxial layer
Ring..
Wherein, the first barrier layer and the second barrier layer can be the composite bed of silicon nitride layer and oxygen pad layer, and oxygen pad layer leans on
The side of the nearly heavy doped conduction substrate, for improving the stress of silicon nitride.Heavy doped conduction substrate can be specifically put into low pressure boiler tube
In, generation silicon nitride is reacted with ammonia by dichlorosilane, silicon nitride layer is formed in the front and back of heavy doped conduction substrate.And
Formed before silicon nitride layer, by thermal oxidation technology, physical deposition or chemical deposition process in the front of heavy doped conduction substrate and the back of the body
Face forms oxygen pad layer.
First barrier film and the second barrier film can certainly be formed by different process.Specifically, can be with
The first barrier layer is formed after the second barrier layer is removed, then at the back side of heavy doped conduction substrate, then again in the upper of heavy doping buried regions
The square lightly doped epitaxial layer into same conduction type.
With reference to shown in Fig. 5-Fig. 7, the specific manufacturing process of power IC device of the embodiment of the present invention is：
Step a, arsenic ion is adulterated into silicon semiconductor substrate, forms N-type heavy doped conduction substrate 10.Can also be in heavy doping base
The front at bottom 10 forms N-type lightly doped epitaxial layer（Not shown in figure）, for improving the breakdown voltage of CDMOS products.
Step b, by thermal oxidation technology, physical deposition or chemical deposition process in the front of N-type heavy doped conduction substrate 10 and
The back side forms oxygen pad layer 30, and then N-type heavy doped conduction substrate 10 is put into low pressure boiler tube, is reacted and given birth to ammonia by dichlorosilane
Into silicon nitride, silicon nitride layer 20 is formed on oxygen pad layer 30.
Step c, coats photoresist on the positive silicon nitride layer 20 of N-type heavy doped conduction substrate 10, is then exposed, and shows
Shadow, forms photoresist and retains region and photoresist and do not retain region, wherein, photoresist, which does not retain region and corresponds to p-type heavy doping, to be buried
Region where layer 40, is then mask with silicon nitride layer 20, and the front doping boron ion to heavy doped conduction substrate 10, forms p-type
Heavy doping buried regions 40.10 positive silicon nitride layer 20 of N-type heavy doped conduction substrate is removed finally by dry etching.
Step d, in the front doping boron ion of N-type heavy doped conduction substrate 10, forms p-type lightly doped epitaxial layer 50.
Step e, active area, polycrystalline, N-type source and drain, p-type source and drain, contact hole are formed in the front of N-type heavy doped conduction substrate 10
Deng existing very ripe production method in the prior art, this will not be detailed here.
Step f, the drain metal layer of VDMOS is formed at the back side of N-type heavy doped conduction substrate 10（Not shown in figure）.
Embodiment two
Based on same inventive concept, a kind of power IC device is provided in the present embodiment, it includes the first conduction type
Heavy doped conduction substrate and metal layer, are formed in the heavy doping in the heavy doped conduction substrate doped with the first ion, the metal layer
The back side of substrate.Wherein, contact of first ion with metal layer forms low contact resistance.
Technical scheme, by varying the Doped ions of power IC device substrate, makes itself and backside of substrate
The contact of metal layer forms low contact resistance, so as to eliminate backside of substrate injection and annealing process, reduces CDMOS products
Production cost, shortens the fabrication cycle of CDMOS products.
Specifically, the metal layer can be the drain electrode of VDMOS, by reducing contact electricity of first ion with metal layer
Resistance, and then VDMOS conducting resistances can be reduced, improve the performance of CDMOS products.
Wherein, the heavy doped conduction substrate can select N-type semiconductor substrate, can provide leading for smaller for CDMOS products
Be powered resistance.
Further, when the semiconductor base is silicon semiconductor substrate, first ion can select arsenic ion,
Because the contact resistance of arsenic ion and metal layer is only antimony（Sb）The 1/5 of the contact resistance of ion and metal layer, forms low contact
Resistance, so as to reduce the conducting resistance of VDMOS, improves the performance of CDMOS products.Simultaneously as substrate need not be increased
The back side is injected with annealing process to reduce conducting resistance, so as to reduce the production cost of CDMOS products, shortens CDMOS productions
The fabrication cycle of product.
Since CDMOS products can include p-type CMOS, N-type CMOS, p-type DMOS and N-type DMOS at the same time, in order to same
P-type MOS is formed in substrate at the same time and N-type MOS, CDMOS product also needs to the heavy doping buried regions that includes the second conduction type, formation
In the front of heavy doped conduction substrate.Further, in order to improve the breakdown voltage of CDMOS, buried in the heavy doping of the second conduction type
The top of layer is also formed with the lightly doped epitaxial layer of the second conduction type.
N-type heavily doped silicon semiconductor base for adulterating arsenic ion, the autodoping effect of arsenic ion is to the in order to prevent
The lightly doped epitaxial layer of two conduction types has an impact, it is preferred that is formed between the heavy doped conduction substrate and the metal layer
There is the first barrier layer, during the lightly doped epitaxial layer of the second conduction type is formed, the first barrier layer can effectively prevent
Arsenic（AS）Ion is diffused into surrounding environment in high temperature environments, with reacting gas fused deposition to heavy doped conduction substrate front, shadow
The quality of the lightly doped epitaxial layer of the second conduction type is rung, so as to prevent arsenic（AS）The autodoping effect of ion is outer to being lightly doped
Prolong layer to have an impact.
Specifically, first barrier layer can be the composite bed for including silicon nitride layer and oxygen pad layer, and the oxygen pad layer
Close to the side of the heavy doped conduction substrate, for improving the stress of silicon nitride.
As shown in fig. 7, the power IC device in the present embodiment includes：
The N-type heavily doped silicon semiconductor base 10 of arsenic ion is adulterated, in the positive shape of N-type heavily doped silicon semiconductor base 10
Into there is N-type lightly doped epitaxial layer（Not shown in figure）；
It is formed in the positive p-type heavy doping buried regions 40 of N-type heavily doped silicon semiconductor base 10；
It is formed in the p-type lightly doped epitaxial layer 50 of the top of p-type heavy doping buried regions 40；
It is formed in the active area of the top of p-type lightly doped epitaxial layer 50, polycrystalline, N-type source and drain, p-type source and drain, contact hole etc.；
It is sequentially formed at the oxygen pad layer 30, silicon nitride layer 20 and metal layer at 10 back side of N-type heavily doped silicon semiconductor base（Figure
Not shown in）.
The above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, some improvement and replacement can also be made, these improve and replace
Also it should be regarded as protection scope of the present invention.
Claims (8)
- A kind of 1. production method of power IC device, it is characterised in that including：The first ion is adulterated into semiconductor base, forms the heavy doped conduction substrate of the first conduction type；The first barrier film is formed at the back side of the heavy doped conduction substrate, the second resistance is formed in the front of the heavy doped conduction substrate Barrier film；Graphical second barrier film, forms the pattern on the second barrier layer；Using second barrier layer pattern as mask, the second ion is adulterated to the heavy doped conduction substrate, forms the second conduction type Heavy doping buried regions；The second barrier layer is only removed by dry etching；The lightly doped epitaxial layer of the second conduction type is formed in the top of the heavy doping buried regions；Metal layer is formed under first barrier film, wherein, contact of first ion with metal layer forms low Contact resistance.
- 2. production method according to claim 1, it is characterised in that the semiconductor base is silicon semiconductor substrate；Institute It is arsenic ion to state the first ion.
- 3. production method according to claim 1, it is characterised in that it is thin that first barrier layer is formed by one-time process Film and the second barrier film.
- 4. production method according to claim 3, it is characterised in that first barrier layer and the second barrier layer include The composite bed of silicon nitride layer and oxygen pad layer, the oxygen pad layer is close to the side of the heavy doped conduction substrate.
- 5. production method according to claim 4, it is characterised in that it is thin that first barrier layer is formed by one-time process Film and the second barrier film include：Oxygen pad layer is formed by front and back of the thermal oxidation technology in the heavy doped conduction substrate；The heavy doped conduction substrate is put into low pressure boiler tube, by dichlorosilane and ammonia reaction generation silicon nitride, in the pad Silicon nitride layer is formed in oxygen layer.
- 6. a kind of power IC device, it is characterised in that the power IC device utilizes production method as claimed in claim 1 Manufacture；The power IC device includes：The heavy doped conduction substrate of first conduction type, doped with the first ion in the heavy doped conduction substrate；Metal layer, is formed in the back side of the heavy doped conduction substrate；Wherein, contact of first ion with metal layer forms low contact resistance；The heavy doping buried regions pattern of second conduction type, is formed in the front of the heavy doped conduction substrate；The lightly doped epitaxial layer of second conduction type, is formed in above the heavy doping buried regions；First barrier layer, between the heavy doped conduction substrate and the metal layer.
- 7. power IC device according to claim 6, it is characterised in that first ion is arsenic ion.
- 8. power IC device according to claim 6, it is characterised in that first barrier layer include silicon nitride layer and Oxygen pad layer, the oxygen pad layer is close to the side of the heavy doped conduction substrate.
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| CN106558549A (en) * | 2015-09-25 | 2017-04-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor device and preparation method thereof, electronic installation |
| CN108550529B (en) * | 2018-04-28 | 2021-10-15 | 江苏新顺微电子股份有限公司 | Manufacturing method of high-voltage VDMOS device |
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| CN101640217A (en) * | 2009-08-19 | 2010-02-03 | 中国电子科技集团公司第五十五研究所 | Structure and method for improving current crowding effect of microwave power transistor emitter region |
| EP2528105A2 (en) * | 2010-01-18 | 2012-11-28 | Hyundai Heavy Industries Co., Ltd. | Method for fabricating a back contact solar cell |
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| CN100361281C (en) * | 2005-11-11 | 2008-01-09 | 中国电子科技集团公司第五十五研究所 | Semiconductor platform technology |
| CN100533761C (en) * | 2007-12-28 | 2009-08-26 | 中国电子科技集团公司第五十五研究所 | A ballasting resistor structure of microwave power transistor dynamic emitter electrode |
| US9230810B2 (en) * | 2009-09-03 | 2016-01-05 | Vishay-Siliconix | System and method for substrate wafer back side and edge cross section seals |
| CN102324406A (en) * | 2011-09-30 | 2012-01-18 | 上海晶盟硅材料有限公司 | Epitaxial wafer substrate capable of reducing auto-doping during epitaxy, epitaxial wafer and semiconductor device |
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| CN101640217A (en) * | 2009-08-19 | 2010-02-03 | 中国电子科技集团公司第五十五研究所 | Structure and method for improving current crowding effect of microwave power transistor emitter region |
| EP2528105A2 (en) * | 2010-01-18 | 2012-11-28 | Hyundai Heavy Industries Co., Ltd. | Method for fabricating a back contact solar cell |
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