CN104810251A - Semiconductor packaging technology - Google Patents

Semiconductor packaging technology Download PDF

Info

Publication number
CN104810251A
CN104810251A CN201510210887.1A CN201510210887A CN104810251A CN 104810251 A CN104810251 A CN 104810251A CN 201510210887 A CN201510210887 A CN 201510210887A CN 104810251 A CN104810251 A CN 104810251A
Authority
CN
China
Prior art keywords
wafer
inspection
end process
semiconductor packaging
packaging technology
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510210887.1A
Other languages
Chinese (zh)
Inventor
张伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitech Semiconductor Wuxi Co Ltd
Original Assignee
Hitech Semiconductor Wuxi Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitech Semiconductor Wuxi Co Ltd filed Critical Hitech Semiconductor Wuxi Co Ltd
Priority to CN201510210887.1A priority Critical patent/CN104810251A/en
Publication of CN104810251A publication Critical patent/CN104810251A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

The invention provides a semiconductor packaging technology. The semiconductor packaging technology includes the Front End of Line and the Back End of Line, the Front End of Line includes wafer back grinding, wafer dicing, ultraviolet etching, wafer plasma cleaning, silicon printing, wafer curing, chip bonding, wire bonding and detecting; the Back End of Line includes plastic packaging, laser marking, rear curing, ball soldering, cutting separation, detecting and conveying. The semiconductor packaging technology is applied to electronic products thin and convenient to carry and is highly practical, multiple times of detection is performed during packaging, bad products are reduced, and production efficiency is improved.

Description

A kind of semiconductor packaging process
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of semiconductor packaging process.
Background technology
Chip encapsulation technology has gone through the transition of good several generations, representational technical indicator develop rapidly, comprise chip area more and more close with the ratio of package area, applicable frequency is more and more higher, heat resistance is become better and better, and number of pins increases, and pin-pitch reduces, weight reduces, and reliability improves etc.The most basic factor of these changes comes from the market demand.From the middle and later periods in the 80's, electronic product is just towards portable and miniaturized, networking and multimedization development, and this market demand proposes corresponding requirement to Circuit assembly technology: the raising of unit volume information and the raising of unit interval information.In order to meet these requirements, certainly will will improve the functional density of Circuit assembly, this just becomes the most important factor promoting chip encapsulation technology development.
Summary of the invention
For in existing semiconductor technology, electronic product frivolous portable, require higher encapsulation technology, the invention provides a kind of semiconductor packaging process, in order to achieve the above object, the present invention is by the following technical solutions: a kind of semiconductor packaging process, comprises FEOL, last part technology, and described FEOL comprises: chip back surface grinding, wafer cutting, ultraviolet etching, the cleaning of wafer plasma body, silicon printing, wafer solidification, die bonding, wire bonding, inspection; Described last part technology comprises plastic packaging, laser marking, Post RDBMS, solder ball, cutting and separating, inspection, conveying.
Preferably, be placed on printing stencil by substrate carry out silicon printing operation in described FEOL by vacuum cup, in described FEOL, inspection operation comprises internal visual inspection, 2 step quality control internal visual inspections.
Preferably, before carrying out plastic packaging in described backend process, plasma cleaning to be carried out to substrate and chip, check in described backend process and comprise that outside inspection is looked into, the inspection of quality control external visual.
Beneficial effect of the present invention: this packaging technology, for frivolous portable electronic product, repeatedly checks, reduces bad product, improves production efficiency.
Accompanying drawing explanation
Fig. 1 is present invention process flow chart.
Embodiment
According to Fig. 1, a kind of semiconductor packaging process, comprise FEOL, last part technology, described FEOL comprises: chip back surface grinding, wafer cutting, ultraviolet etching, the cleaning of wafer plasma body, silicon printing, wafer solidification, die bonding, wire bonding, inspection; Described last part technology comprises plastic packaging, laser marking, Post RDBMS, solder ball, cutting and separating, inspection, conveying.
Preferably, be placed on printing stencil by substrate carry out silicon printing operation in described FEOL by vacuum cup, in described FEOL, inspection operation comprises internal visual inspection, 2 step quality control internal visual inspections.
Preferably, before carrying out plastic packaging in described backend process, plasma cleaning to be carried out to substrate and chip, check in described backend process comprise that outside inspection is looked into, the inspection of quality control external visual.

Claims (3)

1.一种半导体封装工艺，其特征在于：包括前段工艺、后段工艺，所述前段工艺包括：晶片背面研磨、晶片切割、紫外线刻蚀、晶片等离子体清洗、硅印刷、晶圆固化、芯片粘接、引线键合、检查；所述后段工艺包括塑封、激光打标、后固化、焊锡球、切割分离、检查、输送。 1. A semiconductor encapsulation process, characterized in that it includes a front-end process and a back-end process, and the front-end process includes: wafer back grinding, wafer cutting, ultraviolet etching, wafer plasma cleaning, silicon printing, wafer curing, chip Bonding, wire bonding, inspection; the back-end process includes plastic packaging, laser marking, post-curing, solder balls, cutting and separation, inspection, and transportation. 2.根据权利要求1所述的一种半导体封装工艺，其特征在于：所述前段工艺中将衬底通过真空吸盘置于印刷模板上进行硅印刷操作，所述前段工艺中检查操作包括内部目视检查、2步质量控制内部目视检查。 2. A semiconductor packaging process according to claim 1, characterized in that: in the front-end process, the substrate is placed on the printing template by a vacuum chuck to carry out silicon printing operation, and the inspection operation in the front-end process includes internal target Visual inspection, 2-step quality control internal visual inspection. 3.根据权利要求1所述的一种半导体封装工艺，其特征在于：所述后端工艺中进行塑封之前要对衬底及芯片进行等离子清洗，所述后端工艺中检查包括外部视检查、质量控制外部目视检查。 3. A semiconductor packaging process according to claim 1, characterized in that: the substrate and the chip are to be plasma-cleaned before plastic packaging in the back-end process, and the inspection in the back-end process includes external visual inspection, Quality control external visual inspection.
CN201510210887.1A 2015-04-29 2015-04-29 Semiconductor packaging technology Pending CN104810251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510210887.1A CN104810251A (en) 2015-04-29 2015-04-29 Semiconductor packaging technology

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510210887.1A CN104810251A (en) 2015-04-29 2015-04-29 Semiconductor packaging technology

Publications (1)

Publication Number Publication Date
CN104810251A true CN104810251A (en) 2015-07-29

Family

ID=53694990

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510210887.1A Pending CN104810251A (en) 2015-04-29 2015-04-29 Semiconductor packaging technology

Country Status (1)

Country Link
CN (1) CN104810251A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109244008A (en) * 2018-09-01 2019-01-18 温州市科泓机器人科技有限公司 For manufacturing the intelligent assembly line of chip
CN111128879A (en) * 2019-12-27 2020-05-08 青岛歌尔微电子研究院有限公司 Wafer and cutting method thereof
CN114121743A (en) * 2021-10-29 2022-03-01 广东汇芯半导体有限公司 Semiconductor circuit manufacturing plant

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110267087A1 (en) * 2010-04-28 2011-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for wafer level classification of light emitting device
CN204257596U (en) * 2014-11-26 2015-04-08 四川大雁微电子有限公司 A kind of semiconductor packages bonding die bonding wire special product checking tool

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110267087A1 (en) * 2010-04-28 2011-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for wafer level classification of light emitting device
CN204257596U (en) * 2014-11-26 2015-04-08 四川大雁微电子有限公司 A kind of semiconductor packages bonding die bonding wire special product checking tool

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
太原理工大学: "IC封装工艺简介", 《道客巴巴文库》 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109244008A (en) * 2018-09-01 2019-01-18 温州市科泓机器人科技有限公司 For manufacturing the intelligent assembly line of chip
CN111128879A (en) * 2019-12-27 2020-05-08 青岛歌尔微电子研究院有限公司 Wafer and cutting method thereof
CN114121743A (en) * 2021-10-29 2022-03-01 广东汇芯半导体有限公司 Semiconductor circuit manufacturing plant

Similar Documents

Publication Publication Date Title
US9281254B2 (en) Methods of forming integrated circuit package
TWI499034B (en) Integrated circuit structure and forming method thereof
TWI534975B (en) Variable-size solder bump structures for integrated circuit packaging
US20160379747A1 (en) Vertical inductor for wlcsp
CN104810251A (en) Semiconductor packaging technology
JP2007048958A (en) Semiconductor device and manufacturing method thereof
Lin et al. Advanced 3D eWLB-PoP (embedded wafer level ball grid array-package on package) technology
WO2012068763A1 (en) Gird-array ic chip package without carrier and manufacturing method thereof
CN211150513U (en) Package body
KR101032546B1 (en) Carrierless chip package for integrated circuit devices, and methods of making same
US20150014848A1 (en) Semiconductor device and fabrication method thereof
CN104485320A (en) Embedded sensing chip encapsulation structure with vertical through hole and manufacturing method thereof
US20140239475A1 (en) Packaging substrate, semiconductor package and fabrication methods thereof
Xian et al. Dicing die attach challenges at multi die stack packages
EP3346492A3 (en) Semiconductor chip package and fabrication method thereof
JP2016119366A5 (en)
US20130009311A1 (en) Semiconductor carrier, package and fabrication method thereof
WO2020087253A1 (en) Ic package
US20140191379A1 (en) Low-k chip packaging structure
US7851342B2 (en) In-situ formation of conductive filling material in through-silicon via
CN104347542A (en) Five-side packaged CSP (chip scale package) structure and manufacturing process
CN106997851A (en) A kind of wafer scale（Or panel level）The preparation method of sensor chip encapsulation
JP2009004609A5 (en)
JP2009065034A5 (en)
US9583444B2 (en) Method for applying magnetic shielding layer, method for manufacturing a die, die and system

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20150729

WD01 Invention patent application deemed withdrawn after publication