CN104767697A - Aviation full-duplex switched Ethernet controller and control method thereof - Google Patents
Aviation full-duplex switched Ethernet controller and control method thereof Download PDFInfo
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Abstract
The embodiment of the invention provides an AFDX controller IP core. The AFDX controller IP core comprises a host interface module, a sending function module, a receiving function module, an MAC module, a register configuration module, a cache DPRAM module, a DPRAM bus control module and an SRAM bus control module. The invention correspondingly provides a control method based on the AFDX controller IP core. The problems that a traditional AFDX controller implementation method is poor in real-time performance, low in integration degree, complex in processing process and poor in transportability, occupies too many resources and the like. The design method guarantees real-time performance, improves the integration degree of a system, optimizes the data processing process, reduces the resources occupation rate of an FPGA and improves the performance of an AFDX controller.
Description
Technical field
The application relates to electronic circuit technology field, is specifically related to a kind of aviation full-duplex switching Ethernet controller and control method thereof.
Background technology
AFDX (Avionics Full Duplex Switched Ethernet, aviation full-duplex switching Ethernet) be one of current more advanced avionics network data transmission technology, it has the features such as band is roomy, integrated level is high, real-time and good reliability, has huge applications potentiality in military avionics field.AFDX controller is the part of AFDX network, as the interface that avionics system is connected with AFDX packet switch, by peculiar technology such as traffic shaping, virtual link scheduling, integrity checking and Redundancy Managements, ensure that safety and the reliability of exchanges data between avionics system.
But, in the practical application of AFDX network, different types of data have different delay requirements, and the upper delay of traditional AFDX controller implementation all Frames in traffic shaping with virtual link scheduling process is all identical, can not meet the process of different delay data, real-time is poor.
AFDX receiving unit function comprises integrity checking and Redundancy Management function, first will do integrity checking after receiving Frame, and the frame that then integrity checking is qualified just proceeds Redundancy Management.Traditional way be two functions separately, after integrity checking passes through, two qualified Frames of network are stored respectively, read data frame again after Redundancy Management starts, carries out Redundancy Management after acquisition data frame information again.If two processes can be combined together, so not only can save FPGA resource, algorithmic procedure more can be made to simplify, reduce error probability, raise the efficiency.
The implementation of tradition AFDX controller virtual link layer is: adopt the structure that IEEE802.3 ethernet mac layer function is separated with AFDX virtual link layer proprietary feature, data first carry out the proprietary feature process of AFDX again through the process of ethernet mac layer.Whole data handling procedure is loaded down with trivial details, resource occupation is many, degree of integration is low, portability is poor.
Summary of the invention
In view of this, the main purpose of the embodiment of the present invention is to provide a kind of AFDX controller, the problem such as solve traditional AFDX controller implementation poor real, degree of integration is low, resource occupation is many, handling process is complicated, portability is poor.This design ensure that real-time, improves level of integrated system, optimizes flow chart of data processing, reduces FPGA resource occupancy, improves the performance of AFDX controller.。
The embodiment of the present invention realizes like this, a kind of AFDX controller, comprising: host interface module, sending function module, receiving module, MAC module, register configuration module, buffer memory DPRAM module, DPRAM bus control module, SRAM bus control module;
Described buffer memory DPRAM module is connected with host interface module and DPRAM bus control module respectively, for realizing host interface and the intercommunicating data buffer storage of IP kernel;
Described register configuration module is connected with host interface module, carries out parameter configuration for being responsible for each bar virtual link;
Described DPRAM bus control module also respectively with receiving module and sending function model calling, for realizing the bus marco of IP kernel inter access DPRAM;
Described receiving module also with MAC model calling, for depositing the Frame received, adopt integrity checking and Redundancy Management to realize the distinctive virtual link layer function of AFDX protocol stack in conjunction with optimized algorithm;
Described sending function module is also connected with MAC module and SRAM bus control module respectively, for reading the Frame sent, adopts static priority virtual link dispatching algorithm to realize the distinctive virtual link layer function of AFDX protocol stack;
Described SRAM bus control module is connected with external SRAM, for realizing IP kernel access external SRAM bus marco;
Described MAC module is connected with external physical medium, for controlling the passage between logical links and physical link and coordinate; The use of transmission medium is managed, completes full duplex job control function, meanwhile, add CRC check position and number of frames SN during transmission, during reception, carry out CRC check;
Described host interface module is for realizing the host interface with PERCOM peripheral communication.
Further, the concrete signal of described host interface comprises: address signal addr, data-signal data, chip selection signal csn, write useful signal wrn, read useful signal oen and interrupt signal irq.
Further, described MAC module comprises a MAC module and the 2nd MAC module of parallel setting further, described receiving module respectively with a MAC module and the 2nd MAC model calling, receive the data from a described MAC module and the 2nd MAC module; Described sending function module respectively with a MAC module and the 2nd MAC model calling, send data respectively to a described MAC module and the 2nd MAC module; A described MAC module and the 2nd MAC module respectively with an outside PHY module and the 2nd PHY model calling.
Further, buffer memory DPRAM module comprises dual port RAM, and the capacity of described RAM can configure
Further, bus communication speed is 10M bps or 100M bps.
According to the other one side of the embodiment of the present invention, the embodiment of the present invention also provides a kind of control method based on AFDX controller, comprising: AFDX controller sends Frame and processes; AFDX controller receiving data frame also processes.
Further, the step that described transmission Frame also processes comprises further:
Transmission Frame reads: avionics system data are put in buffer memory DPRAM via host interface module, then by DPRAM bus control module and sending function module from buffer memory DPRAM by data reading, according to different virtual links through SRAM bus control module partitioned storage in external SRAM;
Static priority virtual link is dispatched: after sending module is dispatched to respective virtual link according to static priority virtual link dispatching algorithm, obtain the address that this Frame is deposited in external SRAM, from this initial address, Frame reads by each 4 Bytes, requires to mail to a MAC module and the 2nd MAC module according to Redundancy Management;
MAC sends: MAC module Frame is added before top guide and CRC check position by Ethernet protocol requirement through a PHY module and the 2nd PHY module to AFDX network.
Further, the step that described receiving data frames also processes comprises further:
MAC receiving function: MAC module, after a PHY module and the 2nd PHY module receive the Frame in AFDX network, is removed front top guide and carries out CRC check to Frame, then delivering to receiver module;
Integrity checking and Redundancy Management are in conjunction with optimization process: the data that MAC module transmits by receiver module, stored in own cache, until after data frame receipt, carry out integrity checking and Redundancy Management to Frame;
Receiving data frames is deposited: to receiving the data processing and pass through, be stored in buffer memory DPRAM by DPRAM bus control module by data, last avionics system is read away data via host interface module from buffer memory DPRAM.
Further, described reading and transmission comprise 128 virtual links respectively.
According to technique scheme, the embodiment of the present invention has following effect:
(1) adopt based on static priority virtual link dispatching algorithm when sending, different virtual links can arrange the different priority of height two as requested.Adopt the virtual link of " priority scheduling ", its high-priority data frame transmission lag is significantly less than the delay of lower-priority data frame.Priority scheduling strategy can overcome all identical defect of the Delay Bound of all Frames in standard A FDX scheduling model, meets the data processing that different delay requires." emergency data " in AFDX network is made to have better real-time.
(2) when receiving, integrity checking and Redundancy Management function being optimized, have employed integrity checking and Redundancy Management in conjunction with optimized algorithm, two functional modules are integrated together.Like this under the prerequisite not affecting function, make two functional modules be fused into one, not only can save FPGA resource, algorithmic procedure more can be made to simplify, optimize flow chart of data processing, reduce error probability, raise the efficiency.
(3) have employed ethernet mac layer and AFDX virtual link layer special function fusion structure, what not only achieve that above patent mentions in the mac layer is that transmission frame adds AB network identity, SN information, and achieves the Redundancy Management function of transmission.Realize in the mac layer sending Redundancy Management function, only need add gating switch between MAC layer and PHY, require Frame gating to mail to PHY1 or PHY2 according to Redundancy Management like this, the demand that AFDX terminal control unit sends Redundancy Management can be realized, optimize the handling process to sending redundant data, reduce FPGA resource occupancy, improve performance.
(4) host interface module, host interface and intercommunicating DPRAM buffer memory and DPRAM bus control module is provided, and external SRAM bus control module.These functional module functions provided, make IP kernel of the present invention have better general portability.As, the host interface provided can directly be connected with PCI bridging chip, and SRAM controller can directly communicate with external SRAM.Like this, IP kernel provided by the invention is easy to the scheme realizing AFDX terminal board.
(5) adopt VHDL code to write, IP kernel integration packaging, has general portability.
(6) simultaneously, this controller can be embedded in SOC (SOC (system on a chip)) and SIP (single package system) chip internal, realizes the height integrated chip with band AFDX controller.
Accompanying drawing explanation
By reading the detailed description done non-limiting example done with reference to the following drawings, the other features, objects and advantages of the application will become more obvious:
Fig. 1 shows the AFDX controller IP kernel structured flowchart that the application provides;
The AFDX controller IP kernel that Fig. 2 shows the application to be provided sends Frame read functions state machine transition diagram;
Fig. 3 shows the AFDX controller IP kernel static priority virtual link dispatching algorithm state machine transition diagram that the application provides;
Fig. 4 shows the AFDX controller IP kernel MAC sending function state machine transition diagram that the application provides;
Fig. 5 shows the AFDX controller IP kernel MAC receiving function state machine transition diagram that the application provides;
Fig. 6 shows AFDX controller IP kernel integrity checking and Redundancy Management that the application provides in conjunction with optimized algorithm state machine transition diagram
The AFDX controller IP kernel receiving data frames that Fig. 7 shows the application to be provided deposits functional status machine transition diagram.
Embodiment
Below in conjunction with drawings and Examples, the application is described in further detail.Be understandable that, specific embodiment described herein is only for explaining related invention, but not the restriction to this invention.It also should be noted that, for convenience of description, in accompanying drawing, illustrate only the part relevant to Invention.
It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combine mutually.Below with reference to the accompanying drawings and describe the application in detail in conjunction with the embodiments.
As shown in Figure 1, for AFDX controller IP kernel structured flowchart of the present invention, comprising: host interface module, sending function module, receiving module, MAC module, register configuration module, buffer memory DPRAM module, DPRAM bus control module, SRAM bus control module;
Described buffer memory DPRAM module is connected with host interface module and DPRAM bus control module respectively, for realizing host interface and the intercommunicating data buffer storage of IP kernel;
Described register configuration module is connected with host interface module, carries out parameter configuration for being responsible for each bar virtual link;
Described DPRAM bus control module also respectively with receiving module and sending function model calling, for realizing the bus marco of IP kernel inter access DPRAM;
Described receiving module also with MAC model calling, for depositing the Frame received, adopt integrity checking and Redundancy Management to realize the distinctive virtual link layer function of AFDX protocol stack in conjunction with optimized algorithm;
Described sending function module is also connected with MAC module and SRAM bus control module respectively, for reading the Frame sent, adopts static priority virtual link dispatching algorithm to realize the distinctive virtual link layer function of AFDX protocol stack;
Described SRAM bus control module is connected with external SRAM, for realizing IP kernel access external SRAM bus marco;
Described MAC module is connected with external physical medium, for controlling the passage between logical links and physical link and coordinate; The use of transmission medium is managed, completes full duplex job control function, meanwhile, add CRC check position and number of frames SN during transmission, during reception, carry out CRC check;
Described host interface module is for realizing the host interface with PERCOM peripheral communication.
There is provided another preferred embodiment, the concrete signal of described host interface comprises: address signal addr, data-signal data, chip selection signal csn, write useful signal wrn, read useful signal oen and interrupt signal irq.
Another preferred embodiment is provided, described MAC module comprises a MAC module and the 2nd MAC module of parallel setting further, described receiving module respectively with a MAC module and the 2nd MAC model calling, receive the data from a described MAC module and the 2nd MAC module; Described sending function module respectively with a MAC module and the 2nd MAC model calling, send data respectively to a described MAC module and the 2nd MAC module; A described MAC module and the 2nd MAC module respectively with an outside PHY module and the 2nd PHY model calling.
There is provided another preferred embodiment, buffer memory DPRAM module comprises dual port RAM, and the capacity of described RAM can configure.AFDX controller IP kernel of the present invention meets the AFDX terminal protocol of ARINC664 specification, can be connected with AFDX network, and be responsible for transmission and the reception of Frame, its link transmission rate is 10M bps or 100M bps.
According to the other one side of the embodiment of the present invention, the embodiment of the present invention also provides a kind of control method based on AFDX controller, comprising: AFDX controller sends Frame and processes; AFDX controller receiving data frame also processes.
Contrast accompanying drawing to be below specifically described above-mentioned flow process.
Further, the step that described transmission Frame also processes comprises further:
It is as follows that AFDX controller IP kernel of the present invention sends Frame handling process:
Transmission Frame reads: first avionics system data are put in buffer memory DPRAM via host interface module, then by DPRAM bus control module and sending function module from buffer memory DPRAM by data reading, according to different virtual links through SRAM bus control module partitioned storage in external SRAM;
Static priority virtual link is dispatched: the sending module of this IP kernel, after being dispatched to respective virtual link, obtains the address that this Frame is deposited in external SRAM according to static priority virtual link dispatching algorithm.From this initial address, Frame reads by each 4 Bytes, requires to mail to a MAC module and the 2nd MAC module according to Redundancy Management;
MAC sending function: the MAC module of this IP kernel, before Frame is added top guide and CRC check position by Ethernet protocol requirement through a PHY module and the 2nd PHY module to AFDX network.
In transmission flow, send Frame read functions and have 9 states, State Transferring relation as shown in Figure 2.
The state that AFDX controller IP kernel provided by the invention sends digital independent functional status machine is as shown in the table:
Table 1, AFDX controller IP kernel sends the state of digital independent functional status machine
| sequence number | state | explanation |
| 1 | idle | idle condition. |
| 2 | read_desc | read to send Frame descriptor pointer. |
| 3 | check_desc | check and send Frame status condition. |
| 4 | samp_req | sample port Frame is read in request. |
| 5 | req | judge whether to continue to read to send Frame. |
| 6 | fill_fifo | read and send Frame. |
| 7 | check_result | check to read and send Frame state outcome. |
| 8 | write_result | write-read is got and is sent Frame state outcome. |
| 9 | udperror | uDP head mistake. |
Table 2, the state transition condition explanation in Fig. 2
In transmission flow, static priority virtual link scheduling feature has 6 states, and State Transferring relation as shown in Figure 3.
AFDX controller IP kernel provided by the invention, the state of static priority virtual link scheduling feature state machine is as shown in the table:
Table 3, the state of AFDX controller IP kernel static priority virtual link scheduling feature state machine
Table 4, the state transition condition explanation in Fig. 3
In transmission flow, MAC sending function has 11 states, and State Transferring relation as shown in Figure 4.
The state of AFDX controller IP kernel MAC sending function state machine provided by the invention is as shown in the table:
Table 5, the state of AFDX controller IP kernel MAC sending function state machine
Table 6, the state transition condition explanation in Fig. 4
AFDX controller IP kernel receiving data frames handling process of the present invention is as follows:
MAC receiving function: the MAC module of this IP kernel, after a PHY module and the 2nd PHY module receive the Frame in AFDX network, removes front top guide and carries out CRC check to Frame, then delivering to receiver module.
Integrity checking and Redundancy Management are in conjunction with optimization process: the receiver module of this IP kernel, and data MAC module transmitted, stored in own cache, until after data frame receipt, carry out integrity checking and Redundancy Management to Frame.
Receiving data frames is deposited: to receiving the data processing and pass through, data be stored in buffer memory DPRAM by DPRAM bus control module.Last avionics system is read away data via host interface module from buffer memory DPRAM.
Receive in flow process, MAC receiving function has 9 states, and State Transferring relation as shown in Figure 5.
The state of AFDX controller IP kernel MAC receiving function state machine provided by the invention is as shown in the table:
Table 7, the state of AFDX controller IP kernel MAC receiving function state machine
| sequence number | state | explanation |
| 1 | idle | idle condition. |
| 2 | wait_fsd | deng start frame frame delimiter. |
| 3 | data1 | the data received are put into the low four of a byte. |
| 4 | data2 | the data received are put into the high four of a byte. |
| 5 | check_crc | frame CRC check. |
| 6 | report_status | receiving data frames receives status report. |
| 7 | wait_report | wait for the frame end of transmission. |
| 8 | discard_packet | abandon erroneous frame. |
| 9 | errorst | received frame loading error occurring. |
Table 8, the state transition condition explanation in Fig. 5
Receive in flow process, integrity checking and Redundancy Management have 16 states in conjunction with optimized algorithm processing capacity, and State Transferring relation as shown in Figure 6.
AFDX controller IP kernel integrity checking provided by the invention and Redundancy Management as shown in the table in conjunction with the state of optimized algorithm processing capacity state machine:
Table 9, AFDX controller IP kernel integrity checking and Redundancy Management are in conjunction with the state of optimized algorithm processing capacity state machine
Table 10, the state transition condition explanation in Fig. 6
Receive in flow process, receiving data frames is deposited function and is had 8 states, and State Transferring relation as shown in Figure 7.
The state that AFDX controller IP kernel receiving data frames provided by the invention deposits functional status machine is as shown in the table:
Table 11, AFDX controller IP kernel receiving data frames deposits the state of functional status machine
Table 12, the state transition condition explanation in Fig. 7
More than describe and be only the preferred embodiment of the application and the explanation to institute's application technology principle.Those skilled in the art are to be understood that, invention scope involved in the application, be not limited to the technical scheme of the particular combination of above-mentioned technical characteristic, also should be encompassed in when not departing from described inventive concept, other technical scheme of being carried out combination in any by above-mentioned technical characteristic or its equivalent feature and being formed simultaneously.The technical characteristic that such as, disclosed in above-mentioned feature and the application (but being not limited to) has similar functions is replaced mutually and the technical scheme formed.
Claims (9)
1. an AFDX controller, is characterized in that, comprising: host interface module, sending function module, receiving module, MAC module, register configuration module, buffer memory DPRAM module, DPRAM bus control module, SRAM bus control module;
Described buffer memory DPRAM module is connected with host interface module and DPRAM bus control module respectively, for realizing host interface and the intercommunicating data buffer storage of IP kernel;
Described register configuration module is connected with host interface module, carries out parameter configuration for being responsible for each bar virtual link;
Described DPRAM bus control module also respectively with receiving module and sending function model calling, for realizing the bus marco of IP kernel inter access DPRAM;
Described receiving module also with MAC model calling, for depositing the Frame received, adopt integrity checking and Redundancy Management to realize the distinctive virtual link layer function of AFDX protocol stack in conjunction with optimized algorithm;
Described sending function module is also connected with MAC module and SRAM bus control module respectively, for reading the Frame sent, adopts static priority virtual link dispatching algorithm to realize the distinctive virtual link layer function of AFDX protocol stack;
Described SRAM bus control module is connected with external SRAM, for realizing IP kernel access external SRAM bus marco;
Described MAC module is connected with external physical medium, for controlling the passage between logical links and physical link and coordinate; The use of transmission medium is managed, completes full duplex job control function, meanwhile, add CRC check position and number of frames SN during transmission, during reception, carry out CRC check;
Described host interface module is for realizing the host interface with PERCOM peripheral communication.
2. AFDX controller according to claim 1, is characterized in that, the concrete signal of described host interface comprises: address signal addr, data-signal data, chip selection signal csn, write useful signal wrn, read useful signal oen and interrupt signal irq.
3. A FDX controller according to claim 1, it is characterized in that, described MAC module comprises a MAC module and the 2nd MAC module of parallel setting further, described receiving module respectively with a MAC module and the 2nd MAC model calling, receive the data from a described MAC module and the 2nd MAC module; Described sending function module respectively with a MAC module and the 2nd MAC model calling, send data respectively to a described MAC module and the 2nd MAC module; A described MAC module and the 2nd MAC module respectively with an outside PHY module and the 2nd PHY model calling.
4. A FDX controller according to claim 1, is characterized in that, buffer memory DPRAM module comprises dual port RAM, and the capacity of described dual port RAM can configure.
5. A FDX controller according to claim 1, is characterized in that, bus communication speed is 10M bps or 100M bps.
6. based on a control method for AFDX controller, it is characterized in that, comprising:
AFDX controller sends Frame and processes;
AFDX controller receiving data frame also processes.
7. control method according to claim 6, is characterized in that, the step that described transmission Frame also processes comprises further:
Transmission Frame reads: avionics system data are put in buffer memory DPRAM via host interface module, then by DPRAM bus control module and sending function module from buffer memory DPRAM by data reading, according to different virtual links through SRAM bus control module partitioned storage in external SRAM;
Static priority virtual link is dispatched: after sending module is dispatched to respective virtual link according to static priority virtual link dispatching algorithm, obtain the address that this Frame is deposited in external SRAM, from this initial address, Frame reads by each 4Bytes, requires to mail to a MAC module and the 2nd MAC module according to Redundancy Management;
MAC sends: MAC module Frame is added before top guide and CRC check position by Ethernet protocol requirement through a PHY module and the 2nd PHY module to AFDX network.
8. control method according to claim 6, is characterized in that, the step that described receiving data frames also processes comprises further:
MAC receives: MAC module, after a PHY module and the 2nd PHY module receive the Frame in AFDX network, is removed front top guide and carries out CRC check to Frame, then delivering to receiver module;
Integrity checking and Redundancy Management are in conjunction with optimization process: the data that MAC module transmits by receiver module, stored in own cache, until after data frame receipt, carry out integrity checking and Redundancy Management to Frame;
Receiving data frames is deposited: to receiving the data processing and pass through, be stored in buffer memory DPRAM by DPRAM bus control module by data, last avionics system is read away data via host interface module from buffer memory DPRAM.
9. the control method according to claim 7 or 8, is characterized in that, described reading and transmission comprise 128 virtual links respectively.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105406998A (en) * | 2015-11-06 | 2016-03-16 | 天津津航计算技术研究所 | Dual-redundancy gigabit ethernet media access controller IP core based on FPGA |
| CN107390548A (en) * | 2017-08-31 | 2017-11-24 | 中国民航大学 | A kind of avionics HWIL simulation data path control system |
| CN109946955A (en) * | 2019-03-15 | 2019-06-28 | 西安微电子技术研究所 | A kind of double-network redundant ethernet controller Linux trawl performance controller |
| CN110798288A (en) * | 2019-01-28 | 2020-02-14 | 通号城市轨道交通技术有限公司 | Redundant communication method and device |
| CN111682928A (en) * | 2020-06-18 | 2020-09-18 | 北京国科天迅科技有限公司 | Full-duplex communication method and device in optical fiber avionics communication system |
| CN112350911A (en) * | 2020-10-13 | 2021-02-09 | 中国运载火箭技术研究院 | Ground electrical system based on multiple communication buses |
| CN115576656A (en) * | 2022-12-12 | 2023-01-06 | 山东三未信安信息科技有限公司 | Device, method and equipment for inter-domain communication |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050220029A1 (en) * | 2004-04-02 | 2005-10-06 | Airbus France | Simulation and test system for at least one item of equipment on an AFDX network |
| CN102761488A (en) * | 2012-07-13 | 2012-10-31 | 中国航天科技集团公司第九研究院第七七一研究所 | High-speed full duplex switched Ethernet controller |
| CN102780789A (en) * | 2011-05-11 | 2012-11-14 | 孙然 | Design scheme for high-bandwidth network processor data bus interface module |
| CN103049414A (en) * | 2012-12-28 | 2013-04-17 | 中国航空工业集团公司第六三一研究所 | Method for converting and transmitting data between FC (fiber channel) bus and CAN (controller area network) bus |
| CN203151539U (en) * | 2012-11-09 | 2013-08-21 | 北京航空航天大学 | AFDX terminal system virtual link layer IP core |
| US20140100718A1 (en) * | 2012-10-05 | 2014-04-10 | Airbus Operations (Sas) | Flight control system using simplex computers and aircraft comprising same |
-
2015
- 2015-01-23 CN CN201510035509.4A patent/CN104767697A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050220029A1 (en) * | 2004-04-02 | 2005-10-06 | Airbus France | Simulation and test system for at least one item of equipment on an AFDX network |
| CN102780789A (en) * | 2011-05-11 | 2012-11-14 | 孙然 | Design scheme for high-bandwidth network processor data bus interface module |
| CN102761488A (en) * | 2012-07-13 | 2012-10-31 | 中国航天科技集团公司第九研究院第七七一研究所 | High-speed full duplex switched Ethernet controller |
| US20140100718A1 (en) * | 2012-10-05 | 2014-04-10 | Airbus Operations (Sas) | Flight control system using simplex computers and aircraft comprising same |
| CN203151539U (en) * | 2012-11-09 | 2013-08-21 | 北京航空航天大学 | AFDX terminal system virtual link layer IP core |
| CN103049414A (en) * | 2012-12-28 | 2013-04-17 | 中国航空工业集团公司第六三一研究所 | Method for converting and transmitting data between FC (fiber channel) bus and CAN (controller area network) bus |
Non-Patent Citations (1)
| Title |
|---|
| 王鹏: "AFDX交换机及交换芯片中关键模块的设计", 《万方数据知识服务平台》 * |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105406998A (en) * | 2015-11-06 | 2016-03-16 | 天津津航计算技术研究所 | Dual-redundancy gigabit ethernet media access controller IP core based on FPGA |
| CN107390548A (en) * | 2017-08-31 | 2017-11-24 | 中国民航大学 | A kind of avionics HWIL simulation data path control system |
| CN107390548B (en) * | 2017-08-31 | 2018-06-19 | 中国民航大学 | A kind of avionics HWIL simulation data path control system |
| CN110798288A (en) * | 2019-01-28 | 2020-02-14 | 通号城市轨道交通技术有限公司 | Redundant communication method and device |
| CN110798288B (en) * | 2019-01-28 | 2021-01-15 | 通号城市轨道交通技术有限公司 | Redundant communication method and device |
| CN109946955A (en) * | 2019-03-15 | 2019-06-28 | 西安微电子技术研究所 | A kind of double-network redundant ethernet controller Linux trawl performance controller |
| CN111682928A (en) * | 2020-06-18 | 2020-09-18 | 北京国科天迅科技有限公司 | Full-duplex communication method and device in optical fiber avionics communication system |
| CN111682928B (en) * | 2020-06-18 | 2021-06-08 | 北京国科天迅科技有限公司 | Full-duplex communication method and device in optical fiber avionics communication system |
| CN112350911A (en) * | 2020-10-13 | 2021-02-09 | 中国运载火箭技术研究院 | Ground electrical system based on multiple communication buses |
| CN115576656A (en) * | 2022-12-12 | 2023-01-06 | 山东三未信安信息科技有限公司 | Device, method and equipment for inter-domain communication |
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