CN104766825A - Flash device and method for improving gate capacitance of flash device - Google Patents
Flash device and method for improving gate capacitance of flash device Download PDFInfo
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- CN104766825A CN104766825A CN201410009073.7A CN201410009073A CN104766825A CN 104766825 A CN104766825 A CN 104766825A CN 201410009073 A CN201410009073 A CN 201410009073A CN 104766825 A CN104766825 A CN 104766825A
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000007667 floating Methods 0.000 claims abstract description 43
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 38
- 229920005591 polysilicon Polymers 0.000 claims abstract description 38
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 21
- 238000005516 engineering process Methods 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 238000002955 isolation Methods 0.000 claims description 10
- 238000005520 cutting process Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- 239000002985 plastic film Substances 0.000 claims 1
- 229920006255 plastic film Polymers 0.000 claims 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 abstract description 14
- 230000004913 activation Effects 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 abstract 1
- 239000000243 solution Substances 0.000 description 5
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000008280 blood Substances 0.000 description 1
- 210000004369 blood Anatomy 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention provides a flash device and a method for improving the gate capacitance of the flash device. A polysilicon layer for preparing a floating gate is injected with Ge ions locally and the etched, and the secondary floating gate with a step pattern is finally prepared. On the premise that key size of the device is not influenced, the contact area between a dielectric layer and the floating/control gate can be effectively increased, and the control gate capacitance is improved; the secondary floating gate enables better contact between the dielectric layer and the floating/control gate, and the performance of the device is further improved; the floating gate is composed of the polysilicon layer and a silicon germanium (SiGe)layer, a Si-SiGe heterojunction is formed in the floating gate, and SiGE has better activation characteristic and lower gate resistance; and the junction capacitance generated by the Si-SiGe heterojunction makes contribution to the capacitance of the whole device, and the performance of the flash device is improved.
Description
Technical field
The present invention relates to semiconductor memory preparation field, be specifically related to a kind of method and the flash device that increase flash device gate electric capacity.
Background technology
At present along with the development of semiconductor fabrication, especially at the design aspect of memory cell, in order to enhance competitiveness, need the performance improving device as far as possible, to realize the read/write of faster efficiency, to meet the continuous pursuit of people to high performance device.
Fig. 1-3 is the flow chart that in prior art prepared by flash device: concrete steps are as follows:
First provide a substrate 1, side forms tunnel oxide 2, floating gate material layer 3 and mask layer 4 successively over the substrate, as shown in Figure 1; Then etching forms shallow trench, grinds after carrying out filling oxide layer to groove, forms fleet plough groove isolation structure 5, as shown in Figure 2; Remove residue mask layer 4 ', after a dielectric layer 6 is prepared on the surface of floating gate material layer 3a, then in this dielectric layer 6 disposed thereon one control gate material layer 7, go out as shown in Figure 3; Carry out follow-up unit component district forming step and source and drain injection technology, subsequent technology adopts prior art institute conventional techniques means, therefore does not repeat them here.
In order to obtain more high-performance and more large storage capacity, the area of device cell is the smaller the better.This is restricted with regard to making the critical size of floating boom, and the reduction of the size of floating boom own can cause the reduction of the contact area between floating boom and control gate, namely coupling capacitance reduces, and effectively high coupling ratios means that memory has lower operating voltage and power consumption, therefore, how when ensureing that device critical dimensions is constant, the coupling capacitance effectively increasing flash is the direction that those skilled in the art endeavour to study always.
Summary of the invention
The invention provides a kind of method increasing flash device gate electric capacity, by floating boom preparation is formed the secondary floating boom with step cutting pattern, effectively can increase the coupling capacitance of flash, and then can effectively increase control gate electric capacity, improve device performance.
The technical solution used in the present invention is:
Increase a method for flash device gate electric capacity, wherein, comprise the following steps:
There is provided a substrate, in upper surface deposited oxide layer, the first polysilicon layer and the mask layer successively of described substrate;
Etch successively in described mask layer, the first polysilicon layer and oxide layer to described substrate and form shallow trench, deposit a packed layer and be full of described shallow trench and the upper surface covering residue mask layer, packed layer described in polishing, to the upper surface of this residue mask layer, forms fleet plough groove isolation structure;
After removing described residue hard mask layer, the sidewall that described fleet plough groove isolation structure exposes prepares a side wall, and with described side wall for mask carries out ion implantation technology, to form an ion doped layer in residue first polysilicon layer;
After removing described side wall, etching removes part described residue first polysilicon layer, to form the floating boom with step cutting pattern;
Prepare a dielectric layer surface that described floating boom exposes is covered completely, then in described dielectric layer disposed thereon second polysilicon layer in order to prepare control gate.
Above-mentioned method, wherein, the material of described mask layer is Si
3n
4.
Above-mentioned method, wherein, the material of described oxide layer and described packed layer is silica.
Above-mentioned method, wherein, after removing described residue hard mask layer, deposition one deck side wall film also carries out selective etch to this side wall film, to form described side wall.
Above-mentioned method, wherein, the material of described side wall film is SiN.
Above-mentioned method, wherein, adopts Ge ion to carry out described ion implantation technology.
Above-mentioned method, wherein, described dielectric layer is ono dielectric layer.
Above-mentioned method, wherein, adopts thermal oxidation technology to prepare described ono dielectric layer.
Above-mentioned method, wherein, the material of described ion doped layer is germanium silicon.
A kind of flash device, wherein, described flash device comprises a substrate, described substrate is formed with stacking gate structure, and this stacking gate structure comprises floating boom, dielectric layer and the control gate with step cutting pattern, described dielectric layer covers the upper surface of described floating boom, and described control gate covers the upper surface of described dielectric layer;
Wherein, described floating boom comprises a polysilicon layer and partly covers the germanium-silicon layer of this polysilicon layer upper surface.
Above-mentioned device, wherein, has a tunnel oxide between described stacking gate and described substrate, and the material of this tunnel oxide is silica.
Above-mentioned device, wherein, described dielectric layer is the ono dielectric layer adopting thermal oxidation technology to prepare.
Above-mentioned device, wherein, the material of described control gate is polysilicon.
Owing to present invention employs above technical scheme, inject rear by carrying out local ion to the polysilicon layer preparing floating boom and etch, finally prepare the secondary floating boom that has step cutting pattern, under the prerequisite not affecting device critical dimensions, effectively can increase the contact area of dielectric layer and floating boom and control gate, this is beneficial to and improves control gate electric capacity; The secondary floating gate structure simultaneously formed also can make dielectric layer and have better contact between floating boom and control gate, and then boost device performance.
Accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, the present invention and feature, profile and advantage will become more obvious.Mark identical in whole accompanying drawing indicates identical part.Deliberately proportionally do not draw accompanying drawing, focus on purport of the present invention is shown.
Fig. 1-3 is the flow chart that in prior art prepared by flash;
Fig. 4-10 is a kind of flow chart increasing the method for flash device gate electric capacity provided by the invention;
Figure 11 is the partial structurtes sectional view of flash structure provided by the invention.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:
With reference to shown in Fig. 4-10, the invention provides a kind of method increasing flash device gate electric capacity, comprise the following steps:
Step S1: provide a substrate 1, then prepares tunnel oxide 2, first polysilicon layer 3 and mask layer 4 successively at this substrate 1 upper surface, and preferably, tunnel oxide 2 material is silica, and mask layer 4 material is Si
3n
4.Structure as shown in Figure 4.
Step S2: adopt Patternized technique etching to form shallow trench, then prepare a packed layer shallow trench is filled, adopt chemical mechanical milling tech to be polished to remaining mask layer 4 ' upper surface to stop, forming fleet plough groove isolation structure 5(STI, Shallow Trench Isolation).Preferably, this packed layer material is silica.Structure as shown in Figure 5.
Step S3: remove remaining mask layer 4 ', as shown in Figure 6.
Step S4: the sidewall exposed at fleet plough groove isolation structure 5 forms side wall 8, and concrete steps are:
First prepare one deck side wall film device upper surface is covered completely, preferably, depositing operation can be adopted to form layer of sin layer as side wall film; Then adopt selective etch technique to etch side wall film, the sidewall finally exposed at fleet plough groove isolation structure 5 forms side wall 8, and makes this side wall 8 cover the top of the first polysilicon layer 3a.In an embodiment of the present invention, by the reaction condition of adjustment etching, the width of the side wall 8 finally obtained is adjusted.As shown in Figure 7.
Step S5: carry out ion implantation, forms an ion doped layer 3b in the first polysilicon layer 3a.In an embodiment of the present invention, preferably adopt Ge ion to inject, Ge ion and the first polysilicon layer 3a of injection react, and then in the first polysilicon layer 3a, form the ion doped layer 3b that a material is SiGe.As shown in Figure 8.
Step S6: remove side wall 8, and carry out etching technics the first polysilicon layer 3a is etched, preferably, adopt plasma etching industrial to etch.Owing to defining the ion doped layer 3b of a SiGe in step S5, when adopting plasma etching, the etch rate of gas to SiGe of etching is slower, and it is very fast for the etch rate of polysilicon, after etching after a while, the polysilicon layer of ion doped layer 3b both sides is removed, and is that the ion doped layer 3b of SiGe then loses less by material, structure shown in up-to-date formation Fig. 9.As shown in the figure, after etching, define the floating boom with step cutting pattern through ion implantation, it is made up of jointly the remaining polysilicon layer 3c of bottom and the ion doped layer 3b be positioned on remaining polysilicon layer 3c.
Step S7: prepare a dielectric layer 6 and covered completely on the surface of the exposure of floating boom, preferably, adopts thermal oxidation technology to form an ono dielectric layer by the surface coverage of secondary floating boom; Then, then in dielectric layer 6 disposed thereon one deck second polysilicon layer 7 in order to prepare control gate, and proceed the forming step of follow-up flash cellular zone.Due to the technological means that subsequent step adopts prior art usual, therefore do not repeat them here.
Owing to adopting above preparation technology, finally prepare the secondary floating boom that has step cutting pattern, under the prerequisite not affecting device critical dimensions, effectively can increase the contact area of dielectric layer, this is conducive to improving control gate electric capacity; The secondary floating gate structure simultaneously formed also improves dielectric layer can have better contact with between floating boom and control gate, and then boost device performance.
Further, because the floating boom that formed in the present embodiment is made up of jointly the polysilicon of bottom and the SiGe be positioned on polysilicon, therefore both interfaces are formed with Si-SiGe heterojunction, and doping has better activation characteristic and lower gate resistance in sige; The junction capacitance that Si-SiGe heterojunction produces simultaneously can contribute to the electric capacity of whole flash device further, promotes have good effect for flash device performance.
Meanwhile, present invention also offers a kind of flash device architecture, as shown in figure 11, comprise a base substrate 1 ', above substrate 1 ', have a pile stacked gate structure, between stacking gate structure and substrate 1 ', have a tunnel oxide 2 '.This stacking gate comprises floating boom, dielectric layer 6 and control gate 7 from bottom to top successively; Wherein, floating boom is the secondary floating boom with step cutting pattern, and this floating boom is jointly made up of the polysilicon layer 3c of bottom and the germanium-silicon layer 3b be positioned on this polysilicon layer 3c; Dielectric layer is the ONO thin layer adopting thermal oxidation technology preparation to be formed, and control gate material is polysilicon;
And the substrate being positioned at stacking gate structure both sides is provided with shallow channel isolation area, and it is filled with silica medium, further, in the substrate of stacking gate structure both sides, be also provided with source class and drain electrode, because this figure is two dimension view, therefore indicated in the drawings.
Floating boom due to the flash device that the invention provides is a secondary floating boom with step shape, the contact area with dielectric layer can be increased, this is conducive to increasing control gate electric capacity, thus increase voltage couples efficiency and coupled voltages, and reduce device power consumption, also can not impact existing device area simultaneously, utilize this technology also can reduction of device area further simultaneously, to bring read/write efficiency faster.
Further, because the floating boom formed in the present embodiment is made up of with the SiGe be positioned on polysilicon jointly the polysilicon of bottom, therefore both interfaces are formed with Si-SiGe heterojunction, and doping has better activation characteristic and lower gate resistance in sige; The junction capacitance that Si-SiGe heterojunction produces simultaneously can contribute to the electric capacity of whole flash device further, promotes have good effect for flash device performance.
Above preferred embodiment of the present invention is described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, the equipment wherein do not described in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or being revised as the Equivalent embodiments of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (13)
1. increase a method for flash device gate electric capacity, it is characterized in that, comprise the following steps:
There is provided a substrate, in upper surface deposited oxide layer, the first polysilicon layer and the mask layer successively of described substrate;
Oxide layer, the first polysilicon layer and mask layer described in etched portions form shallow trench to described substrate successively, deposit a packed layer and be full of described shallow trench and the upper surface covering residue mask layer, packed layer described in polishing, to the upper surface of this residue mask layer, forms fleet plough groove isolation structure;
After removing described residue hard mask layer, the sidewall that described fleet plough groove isolation structure exposes prepares a side wall, and with described side wall for mask carries out ion implantation technology, to form an ion doped layer in residue first polysilicon layer;
After removing described side wall, and point residue first polysilicon layer is removed in the portion of etching, forms the floating boom with step cutting pattern;
Prepare a dielectric layer surface that described floating boom exposes is covered completely, then in described dielectric layer disposed thereon second polysilicon layer in order to prepare control gate.
2. the method for claim 1, is characterized in that, the material of described mask layer is Si3N4.
3. the method for claim 1, is characterized in that, the material of described tunnel oxide and described packed layer is silica.
4. the method for claim 1, is characterized in that, after removing described residue hard mask layer, first deposits one deck side wall plastic film covering at device upper surface, then carries out selective etch to described side wall film, form described side wall.
5. the method for claim 1, is characterized in that, the material of described side wall film is SiN.
6. the method for claim 1, is characterized in that, adopts Ge ion to carry out described ion implantation technology.
7. the method for claim 1, is characterized in that, described dielectric layer is ono dielectric layer.
8. method as claimed in claim 7, is characterized in that, adopts thermal oxidation technology to prepare described ono dielectric layer.
9. the method for claim 1, is characterized in that, the material of described ion doped layer is germanium silicon.
10. a flash device, it is characterized in that, described flash device comprises a substrate, described substrate is formed with stacking gate structure, and this stacking gate structure comprises floating boom, dielectric layer and the control gate with step cutting pattern, described dielectric layer covers the upper surface of described floating boom, and described control gate covers the upper surface of described dielectric layer;
Wherein, described floating boom is made up of polysilicon layer and the germanium-silicon layer be positioned on described polysilicon layer, and described germanium-silicon layer part is covered in the upper surface of described polysilicon layer.
11. devices as claimed in claim 10, it is characterized in that there is a tunnel oxide between described stacking gate and described substrate, and the material of this tunnel oxide are silica.
12. devices as claimed in claim 10, is characterized in that, described dielectric layer is the ono dielectric layer adopting thermal oxidation technology to prepare.
13. devices as claimed in claim 10, is characterized in that, the material of described control gate is polysilicon.
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| CN201410009073.7A CN104766825B (en) | 2014-01-08 | 2014-01-08 | A kind of method and flash devices of increase flash device gate capacitance |
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| CN201410009073.7A CN104766825B (en) | 2014-01-08 | 2014-01-08 | A kind of method and flash devices of increase flash device gate capacitance |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108766970A (en) * | 2018-06-13 | 2018-11-06 | 上海华力微电子有限公司 | A kind of SONOS memories and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060281244A1 (en) * | 2005-06-08 | 2006-12-14 | Masayuki Ichige | Nonvolatile semiconductor memory device and method of manufacturing the same |
| US20070004137A1 (en) * | 2005-06-30 | 2007-01-04 | Hynix Semiconductor Inc. | Method of manufacturing semiconductor device |
| CN101257025A (en) * | 2006-11-07 | 2008-09-03 | 株式会社东芝 | Nonvolatile semiconductor memory device and manufacturing method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060281244A1 (en) * | 2005-06-08 | 2006-12-14 | Masayuki Ichige | Nonvolatile semiconductor memory device and method of manufacturing the same |
| US20070004137A1 (en) * | 2005-06-30 | 2007-01-04 | Hynix Semiconductor Inc. | Method of manufacturing semiconductor device |
| CN101257025A (en) * | 2006-11-07 | 2008-09-03 | 株式会社东芝 | Nonvolatile semiconductor memory device and manufacturing method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108766970A (en) * | 2018-06-13 | 2018-11-06 | 上海华力微电子有限公司 | A kind of SONOS memories and preparation method thereof |
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