CN104753496A - Frequency band self-tuning three-level complex band-pass filter - Google Patents
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Abstract
The invention relates to a frequency band self-tuning three-level complex band-pass filter. The frequency band self-tuning three-level complex band-pass filter is characterized by comprising a double-channel three-level complex band-pass filter and an annular frequency oscillator, wherein an adjustable capacitor array is inlaid in an annular frequency oscillator; and the annular frequency oscillator is connected with a digital tuning module. By the special-purpose digital frequency tuning module for the annular frequency oscillator and the filter, automatic frequency band selecting and tuning of a multi-frequency-band filter can be realized; the adjustable capacitor array is inlaid in the annular oscillator, so that frequency deviation caused by influences of voltage change, temperature drifting and process deviation is detected, and frequency selection and filtering characteristic tuning of the filter are carried out by automatically adjusting digital control signals of the variable capacitor array; and the frequency band self-tuning three-level complex band-pass filter has quite high robust performance on the aspect of the influences of voltage change, temperature drifting and process deviation.
Description
Technical field
The present invention relates to filter field, be specifically related to a kind of frequency band self-tuning three grades of complex bandpass filters.
Background technology
Band pass filter in conventional radio frequency passage mostly is single band structure, is applicable to the radio-frequency transmitter application of single frequency.Along with the development of multimode, multiband RF receiver, multi-band bandpass filter becomes one of indispensable module of radio-frequency transmitter.The capacitance that what existing multi-band bandpass filter all adopted is in manual adjustments circuit, and then select its working band and regulate its filtering characteristic.But, in practice, this multi-band bandpass filter can be subject to the impact of change in voltage, temperature drift and process deviation, the frequency band corresponding to the digital value of earlier set and filtering characteristic is caused to produce larger frequency shift (FS), required signal can by deep fades, and less desirable noise can enter in analog baseband signal, finally have a strong impact on signal to noise ratio and the quality of data of receiver; Meanwhile, because each device size of filter cannot be revised, qualitative or quantitative frequency compensation is carried out to band pass filter and becomes very difficult.
Summary of the invention
Object of the present invention is just to provide a kind of frequency band self-tuning three grades of complex bandpass filters, and it can effectively solve the problem, and realizes the automatic selection of filter band and the automatic tuning of filtering characteristic.
For achieving the above object, present invention employs following technical scheme to implement:
A kind of frequency band self-tuning three grades of complex bandpass filters, it is characterized in that: comprise binary channels three grades of complex bandpass filters and annular frequency oscillator, annular frequency oscillator is embedded with and identical tunable capacitor array in binary channels three grades of complex filters, annular frequency oscillator produces frequency signal by self-oscillation and exports digital tuning module to, the frequency signal that annular frequency oscillator exports by digital tuning module and ideal frequency signal carry out asking poor, regulate digital signal according to difference and the digital signal after regulating is fed back to binary channels three grades of complex bandpass filters and annular frequency oscillator.
The present invention compared with prior art, by adopting annular frequency oscillator and filter special digital frequency tuning module, realizes the automatic frequency band selection of multiband filter and tuning; Ring oscillator is embedded with tunable capacitor array, identical with the tunable capacitor array in complex bandpass filters, thus detect the frequency departure that the impact due to change in voltage, temperature drift and process deviation causes, carry out the frequency band selection of filter by automatically regulating variable capacitor array digital controlled signal and filtering characteristic tuning; Compared with conventional filter circuit, in change in voltage, the affecting of temperature drift and process deviation, there is high robust performance.
Accompanying drawing explanation
Fig. 1 is structural representation of the present invention;
Fig. 2 is the circuit structure schematic diagram of binary channels three grades of complex bandpass filters;
Fig. 3 is the circuit theory diagrams of tunable capacitor array;
Fig. 4 is the circuit structure schematic diagram of operational amplifier;
Fig. 5 is the circuit structure schematic diagram of middle annular frequency oscillator;
Fig. 6 is inverter circuit structure schematic diagram;
Fig. 7 is the circuit structure schematic diagram of digital tuning module;
Fig. 8 is the algorithm flow chart of digital tuning module.
Embodiment
In order to make objects and advantages of the present invention clearly understand, below in conjunction with embodiment, the present invention is specifically described.Should be appreciated that following word only in order to describe one or more concrete execution modes of the present invention, considered critical is not carried out to the protection range that the present invention specifically asks.
The technical scheme that the present invention takes as shown in Figure 1, a kind of frequency band self-tuning three grades of complex bandpass filters, comprise binary channels three grades of complex bandpass filters 11 and annular frequency oscillator 12, annular frequency oscillator 12 is embedded with and identical tunable capacitor array in binary channels three grades of complex filters, annular frequency oscillator 12 produces frequency signal by self-oscillation and exports digital tuning module 13 to, the frequency signal that annular frequency oscillator 12 exports by digital tuning module 13 and ideal frequency signal carry out asking poor, regulate digital signal according to difference and the digital signal after regulating is fed back to binary channels three grades of complex bandpass filters 11 and annular frequency oscillator 12.Annular frequency oscillator 12 and filter special digital frequency tuning module is adopted to carry out frequency band from selecting to a binary channels three grades of complex bandpass filters 11; Ring oscillator is joined end to end by inverter and forms, be embedded with tunable capacitor array, it is identical with the tunable capacitor array in complex bandpass filters, by adopting the frequency tuning module of special digital, relatively ring oscillator exports the difference of frequency of oscillation and reference frequency, show that the equivalent capacitance value of the tunable capacitor array in band pass filter should increase or reduce, thus realize the automatic selection of frequency band.
Concrete is operating as:
Digital tuning module 13 forms; INPUT+ and INPUT-is the positive and negative input of binary channels three grades of complex bandpass filters 11 respectively, OUTPUT+ and OUTPUT-is respectively the positive and negative output of binary channels three grades of complex filters, binary channels three grades of complex bandpass filters 11 comprise six groups of identical tunable capacitor arrays, jointly determine its frequency characteristic with resistance device, active operational amplifier; Annular frequency oscillator 12 produces frequency signal by self-oscillation and enters digital tuning module 13, is embedded with and the identical tunable capacitor array of binary channels three grades of complex filters in annular frequency oscillator 12; The frequency signal that annular frequency oscillator 12 exports by digital tuning module 13 and ideal frequency signal carry out asking poor, regulate digital signal S [6:0] according to difference, and new S [6:0] value produced is sent in binary channels three grades of complex bandpass filters 11 and annular frequency oscillator 12;
The circuit structure schematic diagram of Fig. 2 binary channels three grades of complex bandpass filters 11, complex bandpass filters is channel structure, is divided into I, Q two-way, and every road is again differential configuration to suppress common-mode noise; Whole complex bandpass filters forms by three grades, and every grade is the filter cell of two second order (Biquad) structure, and therefore, filter is six stage structures; Variable capacitor array C1 in band pass filter, the circuit structure of C2, C3, C4, C5, C6 are identical with size, and six operational amplifiers OPA1, OPA2, OPA3, OPA4, OPA5, OPA6 have identical circuit structure and device size; VINI is the I road input of complex filter, and VINQ is the Q road input of complex filter, and VOUTI is the I road output of complex filter, and VOUTQ is the Q road output of negative filter; I branch input signal enters first order filter cell by VINI, one end of the positive pole contact resistance R1 of input VINI, the electrode input end of one end that the other end of resistance R1 divides four tunnels to connect tunable capacitor array C1 respectively, one end of resistance R3, one end of resistance R8 and operational amplifier OPA1; The other end of variable capacitor array C1 and the other end short circuit of resistance R3 one end of one end of contact resistance R13 and resistance R6, the cathode output end of the amplifier of concatenation operation simultaneously OPA1; The electrode input end of one end that the other end of resistance R13 divides four tunnels to connect tunable capacitor array C5 respectively, one end of resistance R17, one end of resistance R22 and operational amplifier OPA2; The other end of variable capacitor array C5 and the other end short circuit of resistance R17 one end of one end of contact resistance R25 and resistance R20, the cathode output end of the amplifier of concatenation operation simultaneously OPA2; The electrode input end of one end that the other end of resistance R25 divides four tunnels to connect tunable capacitor array C9 respectively, one end of resistance R29, one end of resistance R34 and operational amplifier OPA3; The other end of variable capacitor array C9 and the other end short circuit of resistance R29 the negative pole of one end of contact resistance R32 and output VOUTI, the cathode output end of the amplifier of concatenation operation simultaneously OPA3; One end of the negative pole contact resistance R2 of input VINI, the negative input of one end that the other end of resistance R2 divides four tunnels to connect tunable capacitor array C2 respectively, one end of resistance R4, one end of resistance R7 and operational amplifier OPA1; The other end of variable capacitor array C2 and the other end short circuit of resistance R4 one end of one end of contact resistance R14 and resistance R5, the cathode output end of the amplifier of concatenation operation simultaneously OPA1; The negative input of one end that the other end of resistance R14 divides four tunnels to connect tunable capacitor array C6 respectively, one end of resistance R18, one end of resistance R21 and operational amplifier OPA2; The other end of variable capacitor array C6 and the other end short circuit of resistance R18 one end of one end of contact resistance R26 and resistance R19, the cathode output end of the amplifier of concatenation operation simultaneously OPA2; The negative input of one end that the other end of resistance R26 divides four tunnels to connect tunable capacitor array C10 respectively, one end of resistance R30, one end of resistance R33 and operational amplifier OPA3; The other end of variable capacitor array C10 and the other end short circuit of resistance R30 the positive pole of one end of contact resistance R31 and output VOUTI, the cathode output end of the amplifier of concatenation operation simultaneously OPA3; Q branch input signal enters first order filter cell by VINQ, one end of the positive pole contact resistance R9 of input VINQ, the electrode input end of one end that the other end of resistance R9 divides four tunnels to connect tunable capacitor array C3 respectively, one end of resistance R11, one end of resistance R6 and operational amplifier OPA4; The other end of variable capacitor array C3 and the other end short circuit of resistance R11 one end of one end of contact resistance R15 and resistance R8, the cathode output end of the amplifier of concatenation operation simultaneously OPA4; The electrode input end of one end that the other end of resistance R15 divides four tunnels to connect tunable capacitor array C7 respectively, one end of resistance R23, one end of resistance R20 and operational amplifier OPA5; The other end of variable capacitor array C7 and the other end short circuit of resistance R23 one end of one end of contact resistance R27 and resistance R22, the cathode output end of the amplifier of concatenation operation simultaneously OPA5; The electrode input end of one end that the other end of resistance R27 divides four tunnels to connect tunable capacitor array C11 respectively, one end of resistance R35, one end of resistance R32 and operational amplifier OPA6; The other end of variable capacitor array C9 and the other end short circuit of resistance R29 the negative pole of one end of contact resistance R32 and output VOUTQ, the cathode output end of the amplifier of concatenation operation simultaneously OPA6; One end of the negative pole contact resistance R10 of input VINQ, the negative input of one end that the other end of resistance R10 divides four tunnels to connect tunable capacitor array C4 respectively, one end of resistance R12, one end of resistance R6 and operational amplifier OPA4; The other end of variable capacitor array C4 and the other end short circuit of resistance R12 one end of one end of contact resistance R16 and resistance R7, the cathode output end of the amplifier of concatenation operation simultaneously OPA4; The negative input of one end that the other end of resistance R16 divides four tunnels to connect tunable capacitor array C8 respectively, one end of resistance R24, one end of resistance R19 and operational amplifier OPA5; The other end of variable capacitor array C8 and the other end short circuit of resistance R24 one end of one end of contact resistance R28 and resistance R22, the cathode output end of the amplifier of concatenation operation simultaneously OPA5; The negative input of one end that the other end of resistance R28 divides four tunnels to connect tunable capacitor array C12 respectively, one end of resistance R36, one end of resistance R32 and operational amplifier OPA6; The other end of variable capacitor array C12 and the other end short circuit of resistance R36 the positive pole of one end of contact resistance R34 and output VOUTQ, the cathode output end of the amplifier of concatenation operation simultaneously OPA6;
Fig. 3 is the circuit theory diagrams of tunable capacitor array, has identical circuit structure and device size with six variable capacitor array C1, C2, C3, C4, C5, C6 in Fig. 2; PORT1 and PORT2 is two connectivity ports of tunable capacitor array, PORT1 divides eight tunnels to be connected with the input of switch swt1, swt2, swt3, swt4, swt5, swt6 and one end of electric capacity C17 respectively, the output of switch swt1, swt2, swt3, swt4, swt5, swt6 connects one end of electric capacity C18, C19, C20, C21, C22, C23, C24 respectively, and the other end short circuit of electric capacity C17, C18, C19, C20, C21, C22, C23, C24 also connects tunable capacitor matrix ports PORT2; The control signal of switch swt1, swt2, swt3, swt4, swt5, swt6 is respectively S0, S1, S2, S3, S4, S5, S6;
Fig. 4 is the circuit structure schematic diagram of operational amplifier, and wherein VINP and VINN is respectively the positive and negative input of operational amplifier, VOUTP and VOUTN is respectively the positive and negative output of operational amplifier, the bias voltage that VB1, VB2 and VB3 provide for external circuit; Supply voltage VDD divides 14 tunnels to connect the source electrode of transistor M1, M2, M3 respectively, one end of electric capacity C15, C16, one end of resistance R39, R40, R43, R44, external voltage VB1 connects the grid of transistor M1, M2 and M3, one end of drain electrode contact resistance R37 of transistor M1, the drain electrode of transistor M10 and output port VOUTP; The source shorted of transistor M4, M5, M6, M7 also connects the drain electrode of transistor M2, the grid of transistor M4 connects input port VINP, the grid of transistor M5 connects input port VINN, the grid short circuit of transistor M5, M6, and connect external voltage port VB2, the drain electrode short circuit of transistor M4, M5, and the one end connecting the drain electrode of transistor M8, the grid of transistor M10 and electric capacity C13, the other end of electric capacity C13 is connected with resistance R37; The drain electrode short circuit of transistor M6, M7 also connects the grid of one end of electric capacity C14, the drain electrode of transistor M9 and transistor M11; The drain electrode of transistor M3 connects the drain electrode of transistor M11, one end of resistance R38, and the output port VOUTN of concatenation operation amplifier; One end of resistance R38 connects one end of electric capacity C14; The grid of transistor M8 and the grid short circuit of transistor M9, its short circuit point is the common mode electrical level VCMFB of common-mode circuit feedback; The source electrode access ground of transistor M8, M9, M10, M11; Electric capacity C15 and resistance R39 is connected in parallel, one end connects supply voltage VDD, the other end connects the drain electrode of transistor M12, grid connects output head anode VOUTP, electric capacity C16 and resistance R40 is connected in parallel, one end connects supply voltage VDD, and the other end connects the drain electrode of transistor M13, and the grid of transistor M13 connects negative pole of output end VOUTN; The source electrode of transistor M12 and the source shorted of transistor M13, and connect the drain electrode of transistor M14 and the short circuit point of resistance R41 and resistance R42; Resistance R41 and R42 is connected in series, and one end connects supply voltage VDD, other end access ground; Resistance R43 connects the drain electrode of transistor M15, and resistance R44 connects the drain electrode of transistor M16, and the grid of transistor M15, M16 all connects bias voltage VB3, the drain electrode short circuit of transistor M15, M16, and is connected with draining with the grid of transistor M17; The grid of transistor M17 is connected with the grid of transistor M14, the source electrode access ground of transistor M14, M17;
Fig. 5 is the circuit structure schematic diagram of annular frequency oscillator 12, wherein VSTART is pumping signal input, VOUT is oscillation frequency signal output, PORT3 and PORT4 is the two ends port of tunable capacitor array, tunable capacitor array shown in tunable capacitor array and Fig. 3 has identical structure and device size, and inverter INV1, INV2, INV3, INV4 have identical circuit structure, step signal enters first inverter INV1 of annular frequency oscillator 12 from VSTART port, the output signal of inverter INV1 divides two-way to enter inverter INV2 and the grid end being connected transistor M20, the output signal of inverter INV2 divides two-way to connect transistor M19 respectively, the grid of M22, supply voltage VDD enters the source electrode of transistor M18, its drain electrode connects the drain electrode of transistor M19, the drain electrode of transistor M19 divides three tunnels to connect transistor M20 respectively, the drain electrode of M22 and the input of inverter INV3, the source electrode of transistor M20 connects the drain electrode of transistor M21, transistor M21, the grid short circuit of M18, and one end of contact resistance R45, one end of the other end contact resistance R46 of resistance R45, the other end of resistance R46 connects output VOUT, the source electrode of transistor M21, M22 all accesses ground GND, the input that the output of inverter INV3 divides two-way to connect inverter INV4 respectively and PORT4 port, the output connectivity port VOUT of inverter INV4, port PO RT3 contact resistance R45, R46 are connected in series a place, one end of electric capacity C25 and the input of switch swt1, swt2, swt3, swt4, swt5, swt6 is connected respectively with time-division eight tunnel, the output of switch swt1, swt2, swt3, swt4, swt5, swt6 connects one end of electric capacity C26, C27, C28, C29, C30, C31, C32 respectively, the other end short circuit of electric capacity C25, C26, C27, C28, C29, C30, C31, C32, and connectivity port PORT4, the control signal of switch swt1, swt2, swt3, swt4, swt5, swt6 is respectively S0, S1, S2, S3, S4, S5, S6,
Fig. 6 is inverter circuit structure schematic diagram, wherein IN is the input of inverter, OUT is the output of inverter, supply voltage VDD enters the source electrode of transistor M23, the grid end short circuit of transistor M23 and M24, and connect input port IN, the drain electrode short circuit of transistor M23 and M24, and connect output port OUT, the source electrode access ground GND of transistor M24;
Figure 7 shows that the circuit structure schematic diagram of digital tuning module 13.Digital tuning module 13 by frequency-dividing counter, counter, digital subtractor and successive approximation register composition; The precision of frequency-dividing counter sum counter is 11; The reset signal end that Clear1 and Clear2 provides for system, respectively the clr end of linking number digit subtracter and the clr end of successive approximation register; EN1 and EN2 is respectively the enable signal end of frequency-dividing counter and successive approximation register, the 6.4MHz reference frequency that Fref provides for external circuit, tuned frequency signal Ftune is the output frequency signal of annular frequency oscillator 12 in Fig. 5, the clock signal that CLK provides for external circuit, respectively the input end of clock CLK of linking number digit subtracter and successive approximation register; When EN1 is high level, frequency-dividing counter sum counter starts simultaneously, reference frequency signal Fref inputs from the CLK input of frequency-dividing counter, and produce the digital signal F [10:0] of 11, tuned frequency signal Ftune inputs from the CLK input of counter, and produces 11 position digital signal C [10:0]; Highest order F [10] in digital signal F [10:0] enters the Enable Pin EN of digital subtractor SUB, all the other enter the input A of digital subtractor, digital signal C [10:0] enters the input B of digital subtractor, the digital signal of digital subtractor to input carries out subtraction, and produce increment signal up and decreasing signal down, and enter B end and the A end of successive approximation register respectively; Successive approximation register carries out the computing of binary system increasing or decreasing according to the increment signal up sent into and decreasing signal down to digital value S [6:0], produces new digital signal S [6:0] and sends in the tunable capacitor array of grade complex bandpass filters of three shown in Fig. 2 and the tunable capacitor array of the loop oscillator shown in Fig. 5 simultaneously;
Fig. 8 is the algorithm flow chart of digital tuning module 13.At initial time, output signal F [10:0], the C [10:0] of the frequency-dividing counter sum counter in Fig. 7 are all initialized to 11 ' b0, and namely 11 bit character codes, are 0; Output signal up and the down signal of digital subtractor 6 are all initialized as 1 ' b0, and the output signal S [6:0] of successive approximation register is initialized as 7 ' b0; Subsequently, under the control of Enable Pin, frequency-dividing counter sum counter starts simultaneously, now judge whether the highest order F [10] in F [10:0] is 1: if F [10] is 1, then judge whether the highest order C [10] of C [10:0] is 1: if C [10] is 1, then judge whether the decimal value of C [10:0] is greater than 1024 and threshold value sum, and in this invention, threshold value is 16; If the decimal value of C [10:0] is greater than 1024 and threshold value sum, S [10:0] is then made to carry out binary system from add-one operation, and to reset F [10:0] be 11 ' b0, C [10:0] is that 11 ' b0, up and down signal is 1 ' b0, restart frequency-dividing counter sum counter afterwards, enter next circulation; If the decimal value of C [10:0] is less than 1024 and threshold value sum, then keep current S [6:0] value, and end number is tuning; If C [10] is not 1, then judge whether the decimal value of C [10:0] is less than the difference of 1024 and threshold value, and in the present invention, threshold value is 16; If the decimal value of C [10:0] is less than the difference of 1024 and threshold value, S [10:0] is then made to carry out binary system from subtracting 1 computing, and to reset F [10:0] be 11 ' b0, C [10:0] is that 11 ' b0, up and down signal is 1 ' b0, restart frequency-dividing counter sum counter afterwards, enter next circulation; If the decimal value of C [10:0] is greater than the difference of 1024 and threshold value, then keep current S [6:0] value, and end number is tuning; If F [10] is not 1, then frequency-dividing counter 4 sum counter 5 enters the cycle count that operating state carries out counting frequency division to Fref and Ftune.
In a word, the present invention effectively can realize the automatic selection of filter band and the automatic tuning of filtering characteristic.
The above is only the preferred embodiment of the present invention; should be understood that; for those skilled in the art; to know in the present invention after contents; under the premise without departing from the principles of the invention; can also make some equal conversion to it and substitute, these convert on an equal basis and substitute and also should be considered as belonging to protection scope of the present invention.
Claims (4)
1. a frequency band self-tuning three grades of complex bandpass filters, it is characterized in that: comprise binary channels three grades of complex bandpass filters and annular frequency oscillator, annular frequency oscillator is embedded with and identical tunable capacitor array in binary channels three grades of complex filters, annular frequency oscillator produces frequency signal by self-oscillation and exports digital tuning module to, the frequency signal that annular frequency oscillator exports by digital tuning module and ideal frequency signal carry out asking poor, regulate digital signal according to difference and the digital signal after regulating is fed back to binary channels three grades of complex bandpass filters and annular frequency oscillator.
2. frequency band self-tuning according to claim 1 three grades of complex bandpass filters, it is characterized in that: the embedded tunable capacitor array of annular frequency oscillator comprises two connectivity port PORT1 and PORT2, connectivity port PORT1 divide eight tunnels respectively with switch swt1, switch swt2, switch swt3, switch swt4, switch swt5, the input of switch swt6 is connected with one end of electric capacity C17, switch swt1, switch swt2, switch swt3, switch swt4, switch swt5, the output of switch swt6 connects electric capacity C18 respectively, electric capacity C19, electric capacity C20, electric capacity C21, electric capacity C22, electric capacity C23, one end of electric capacity C24, electric capacity C17, electric capacity C18, electric capacity C19, electric capacity C20, electric capacity C21, electric capacity C22, the other end short circuit of electric capacity C23 and electric capacity C24 is also connected with connectivity port PORT2.
3. frequency band self-tuning according to claim 1 and 2 three grades of complex bandpass filters, it is characterized in that: annular frequency oscillator comprises pumping signal input VSTART, oscillation frequency signal output VOUT, for connecting connectivity port PORT3 and the connectivity port PORT4 of tunable capacitor array, input VSTART is connected with inverter INV1, the output signal of inverter INV1 divides two-way to be connected to inverter INV2 and the grid end being connected transistor M20 respectively, the output signal of inverter INV2 divides two-way to be connected to transistor M19 respectively, the grid of transistor M22, supply voltage VDD connects the source electrode of transistor M18, the drain electrode of transistor M18 connects the drain electrode of transistor M19, the drain electrode of transistor M19 divides three tunnels to connect transistor M20 respectively, the drain electrode of transistor M22 and the input of inverter INV3, the source electrode of transistor M20 connects the drain electrode of transistor M21, transistor M21, the grid short circuit of transistor M18 one end of contact resistance R45, one end of the other end contact resistance R46 of resistance R45, the other end of resistance R46 connects output VOUT, the source electrode of transistor M21, transistor M22 all accesses ground GND, the output of the input that the output of inverter INV3 divides two-way to connect inverter INV4 respectively and connectivity port PORT4, inverter INV4 connects output VOUT, connected node access connectivity port PORT3 between resistance R45, resistance R46.
4. frequency band self-tuning according to claim 3 three grades of complex bandpass filters, is characterized in that: digital tuning module comprises frequency-dividing counter, counter, digital subtractor and successive approximation register; The precision of frequency-dividing counter sum counter is 11; Digital subtractor is connected with reset signal end Clear1 with Clear2 of system respectively with the clr end of successive approximation register; Frequency-dividing counter and successive approximation register arrange enable signal end EN1 and EN2 respectively, frequency-dividing counter is arranged the CLK input that reference frequency signal Fref is provided for receiving external circuit, counter is arranged the CLK input for receiving the tuned frequency signal Ftune that annular frequency oscillator exports, digital subtractor and successive approximation register arrange the input end of clock CLK receiving the clock signal clk that external circuit provides respectively; When the signal EN1 that frequency-dividing counter receives is high level, frequency-dividing counter sum counter starts simultaneously, reference frequency signal Fref inputs from the CLK input of frequency-dividing counter, and produce the digital signal F [10:0] of 11, tuned frequency signal Ftune inputs from the CLK input of counter, and produces 11 position digital signal C [10:0]; Highest order F [10] in digital signal F [10:0] enters the Enable Pin EN of digital subtractor, all the other 9 the input A entering digital subtractor, digital signal C [10:0] enters the input B of digital subtractor, the digital signal of digital subtractor 6 to input carries out subtraction, and produces B end and A end that increment signal up and decreasing signal down also enters successive approximation register respectively; Successive approximation register carries out the computing of binary system increasing or decreasing according to the increment signal up sent into and decreasing signal down to digital value S [6:0], produces new digital signal S [6:0] and sends in the tunable capacitor array of three grades of complex bandpass filters and endless loop oscillator simultaneously.
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| CN107771273B (en) * | 2015-08-06 | 2020-07-21 | 桑迪士克科技有限责任公司 | Ring oscillator for temperature detection in broadband supply noise environments |
| CN108768389A (en) * | 2018-04-26 | 2018-11-06 | 清华大学 | A kind of multiband two-stage annular voltage controlled oscillator in phaselocked loop |
| CN108768389B (en) * | 2018-04-26 | 2020-06-05 | 清华大学 | Multi-band two-stage annular voltage-controlled oscillator for phase-locked loop |
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Application publication date: 20150701 |