CN104752610A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN104752610A CN104752610A CN201310745826.6A CN201310745826A CN104752610A CN 104752610 A CN104752610 A CN 104752610A CN 201310745826 A CN201310745826 A CN 201310745826A CN 104752610 A CN104752610 A CN 104752610A
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Abstract
The invention relates to a semiconductor structure and a forming method thereof. The forming method comprises providing a semiconductor substrate; forming a plurality of insulation layers and a plurality of pseudo gate material layers on the surface of the substrate in an interval staggering mode; forming a through ole in the insulation layers and the pseudo gate material layers, wherein the bottom of the through hole is formed in the surface of the substrate; forming a channel layer on the surface of the inner wall of the through hole; removing the pseudo gate material layers to form grooves; forming function layers on the surfaces of the inner walls of the grooves; forming gate layers on the surfaces of the function layers, wherein the grooves are filled with the gate layers. By the aid of the method, the formed semiconductor structure integration level can be improved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of semiconductor structure and formation way thereof.
Background technology
Memory occupies critical role in semi-conductor market, due to constantly popularizing of portable electric appts, the proportion shared in whole memory application of nonvolatile memory (non-volatile memory) is also increasing, and the share of the nonvolatile memory of current more than 90% is occupied by flash memory (flash memory).But due to the needs of stored charge, the floating boom of flash memory can not be unconfined thinning along with the reduction of device size, about 32nm is the limit of flash memory characteristic size (CD, critical dimension), therefore in the urgent need to the research and development of nonvolatile memory of future generation.
Resistance-variable storing device (RRAM, Resistive Memory) is a kind of novel nonvolatile memory, has the advantage such as high density, low cost.The principle of resistance-variable storing device, mainly by the effect of the signal of telecommunication, makes storage medium realize reversible transformation between high resistance state and low resistance state, thus realizes storage purpose.Storage medium conventional in resistance-variable storing device mainly contains phase-change material, ferroelectric material, ferromagnetic material, binary metal oxide material, organic material etc.Wherein comparatively extensive with the application of binary metal oxide material, as Nb
2o
5, Al
2o
3, Ta
2o
5, Ti
xo, Cu
xo etc.
Existing resistance-variable storing device is planar structure, and the area occupied is comparatively large, and integrated level is lower.
Transistor is the base components in integrated circuit, and existing transistor is generally distributed in the surface of Semiconductor substrate, occupies larger area, faces the problem that integrated level is lower equally.
Summary of the invention
The problem that the present invention solves is to provide a kind of semiconductor structure and formation way thereof, improves the integrated level of semiconductor structure.
For solving the problem, the invention provides a kind of formation method of semiconductor structure, comprising: substrate is provided; Some insulating barriers of stacked spaced apart and some dummy grid material layers is formed at described substrate surface; In described insulating barrier and dummy grid material layer, form through hole, described via bottoms is positioned at substrate surface; Channel layer is formed on described through-hole wall surface; Remove dummy grid material layer, form groove; Functional layer is formed on described groove inner wall surface; Form grid layer on described functional layer surface, described grid layer fills full described groove.
Optionally, described functional layer comprises the change resistance layer being positioned at described groove inner wall surface, the metal level being positioned at described change resistance layer surface.
Optionally, the material of described insulating barrier is silica, silicon nitride, silicon oxynitride, silicon oxide carbide or carbon silicon oxynitride, and the thickness of described insulating barrier is 30nm ~ 60nm.
Optionally, the material of described change resistance layer is binary metal oxide.
Optionally, the material of described change resistance layer is HfO
2, TiO
2, Ta
2o
5or ZrO
2.
Optionally, the material of described metal level is Hf, Ti, Ta or Zr.
Optionally, the material of described metal level is identical with the metallic element in described change resistance layer.
Optionally, the material of described functional layer is low-K dielectric material.
Optionally, the material of described insulating barrier is silica, silicon nitride, silicon oxynitride, silicon oxide carbide or carbon silicon oxynitride, and doped with N-type impurity ion or p type impurity ion in described insulating barrier.
Optionally, the mass fraction of described N-type impurity ion or p type impurity ion is 6% ~ 14%.
Optionally, also comprise: after the described channel layer of formation, carry out annealing in process, make the Impurity Diffusion in described insulating barrier enter in channel layer, form source-drain area, the temperature of described annealing is 400 DEG C ~ 800 DEG C, and annealing time is 3min ~ 10min.
Optionally, the material of described channel layer is monocrystalline silicon, monocrystalline germanium or monocrystalline germanium SiClx.
Optionally, the thickness of described channel layer is less than 7nm.
Optionally, described channel layer fills full described through hole.
Optionally, the material of described channel layer is monocrystalline germanium, and the method forming described channel layer comprises: in described through hole, form the amorphous germanium layer of filling full described through hole, carry out annealing in process, make described amorphous germanium layer change single crystal germanium layer into described amorphous germanium layer.
Optionally, described annealing in process is carried out under atmosphere of inert gases, and the temperature of described annealing in process is 500 DEG C ~ 800 DEG C, and annealing time is 4 hours ~ 6 hours.
Optionally, also comprise: form the dielectric layer of filling full described through hole at described channel layer surface.
Optionally, the material of described channel layer is monocrystalline germanium, and the method forming described channel layer comprises: form silicon germanide layer on described storage medium layer surface, in described silicon germanide layer, the content of germanium is 30% ~ 55%; Oxidation processes is carried out to described silicon germanide layer, the germanium in described silicon germanide layer is separated out, formed and be positioned at the single crystal germanium layer on storage medium layer surface and be positioned at the silicon oxide layer on described single crystal germanium layer surface.
Optionally, described oxidation processes is the annealing process under oxygen atmosphere, and temperature is 600 DEG C ~ 1000 DEG C, and oxygen concentration is 10% ~ 80%, and annealing time is 20min ~ 200min.
For solving the problem, technical scheme of the present invention also provides a kind of semiconductor structure adopting said method to be formed, and comprising: substrate; Be positioned at some insulating barriers of the stacked spaced apart of described substrate surface and some grid layers; Be positioned at the through hole of described insulating barrier and grid layer, described via bottoms is positioned at substrate surface; Be positioned at the channel layer on described through-hole wall surface; Functional layer between described grid layer and channel layer, between grid layer and insulating barrier.
Compared with prior art, technical scheme of the present invention has the following advantages:
Technical scheme of the present invention, after some insulating barriers and some pseudo-gate dielectric material layers of substrate surface formation stacked spaced apart, forms through hole, forms channel layer on described through-hole wall surface in described insulating barrier and dummy grid material layer; Remove dummy grid material layer, form groove; Functional layer and the grid layer being positioned at described functional layer surface is formed in described groove.Described semiconductor structure has multilayer lamination structure, can improve the quantity of the suprabasil semiconductor device of unit are, thus improve the integrated level of described semiconductor structure.
Further, described functional layer can be change resistance layer and the metal level being positioned at described change resistance layer surface, makes the described semiconductor structure of formation as random access memory unit; Described functional layer can also be high K dielectric material, makes the semiconductor structure of formation as transistor.Because the material of described channel layer is mono-crystalline structures, and thickness is lower, can improve the carrier mobility in described semiconductor structure, and reduces the capture ability of described channel layer to electric charge, thus improves the performance of the semiconductor structure formed.
Accompanying drawing explanation
Fig. 1 to Fig. 7 is the schematic diagram of the forming process of the semiconductor structure of one embodiment of the present of invention;
Fig. 8 to Figure 14 is the schematic diagram of the forming process of the semiconductor structure of another embodiment of the present invention.
Embodiment
As stated in the Background Art, resistance-variable storing device and the transistor of prior art mostly are planar structure, and the horizontal area of the chip that described resistance-variable storing device and transistor are occupied is comparatively large, is unfavorable for the raising of the integrated level of device.
In embodiments of the invention, form resistance-variable storing device and the transistor of stacked structure, improve the integrated level of described resistance-variable storing device and transistor.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Please refer to Fig. 1, substrate 100 is provided.
The material of described substrate 100 comprises the semi-conducting materials such as silicon, germanium, SiGe, GaAs, and described substrate 100 can be body material also can be composite construction, as silicon-on-insulator, can also be the non-semiconducting material such as glass.Those skilled in the art can select the type of described substrate 100 according to the semiconductor device that substrate 100 is formed, therefore the type of described Semiconductor substrate should not limit the scope of the invention.
Please refer to Fig. 2, described substrate 100 is formed some insulating barriers 201 and the dummy grid material layer 202 of stacked spaced apart.
The material of described insulation material layer 201 is the insulating dielectric materials such as silica, silicon nitride, silicon oxynitride, silicon oxide carbide or carbon silicon oxynitride, and the thickness of described insulating barrier 201 is 30nm ~ 60nm.The technique such as chemical vapour deposition (CVD), physical vapour deposition (PVD) can be adopted to form described insulation material layer 201.In the present embodiment, the material of described insulation material layer 201 is silica.
The material of described dummy grid material layer 202 also can be the insulating dielectric materials such as silica, silicon nitride, silicon oxynitride, silicon oxide carbide or carbon silicon oxynitride, and described dummy grid material layer 202 is different materials from insulation material layer 201.The thickness of described dummy grid material layer 202 is 20nm ~ 50nm.Chemical vapor deposition method can be adopted to form described dummy grid material layer 202.In the present embodiment, the material of described dummy grid material layer 202 is silicon nitride.
What be positioned at described substrate 100 surface is insulation material layer 201, and described insulation material layer 201 is as the isolation structure between substrate 100 and the grid layer of follow-up formation, and the isolation structure between neighboring gates layer.
Please refer to Fig. 3, please refer to Fig. 2 at described dummy grid material layer 202() and insulation material layer 201(please refer to Fig. 2) in form through hole 101, described via bottoms is positioned at substrate 100 surface, forms dummy gate layer 212 and insulating barrier 211.
The method forming described through hole 101 comprises: form Patterned masking layer on described insulation material layer 202 surface being positioned at top layer, have opening in described Patterned masking layer, described opening defines the cross sectional dimensions and position that need the through hole formed; Etch described insulation material layer 201 and dummy grid material layer 202 to substrate 100 surface along described opening, form through hole 101; Then described Patterned masking layer is removed.In the present embodiment, the material of described Patterned masking layer can be photoresist layer, adopts cineration technics to remove described Patterned masking layer.
The cross section of described through hole 101 and circle, the diameter of described circle is 5nm ~ 200nm, and in the present embodiment, the cross-sectional diameter of described through hole is 6nm.
Dry etch process can be adopted to form described through hole 101, and concrete, the etching gas that described dry etch process adopts is: CF
4, C
2f
6, C
3f
8in one or more gases.
Described through hole 101 exposes the part surface of substrate 100.
Please refer to Fig. 4, please refer to Fig. 3 at described through hole 101() sidewall surfaces formation channel layer 300.
The material of described channel layer 300 is silicon, germanium or SiGe, and the material of described raceway groove 604 is mono-crystalline structures.
In the present embodiment, the material of described channel layer 300 is germanium, and described channel layer 300 fills full described through hole 101.In described the present embodiment, form the method for described channel layer 300: deposition of Germanium material layer in described through hole 101, because described through-hole side wall is dielectric material, the described germanium material layer adopting depositing operation to be formed is non-crystalline material, and described germanium material layer fills full described through hole 101; Then annealing in process is carried out to described germanium material layer, described annealing in process is carried out under atmosphere of inert gases, and the temperature of described annealing in process is 500 DEG C ~ 800 DEG C, and annealing time is 4 hours ~ 6 hours, described germanium material layer recrystallization is made to form single crystal germanium layer, as channel layer 300.The channel layer 300 of mono-crystalline structures has higher carrier mobility, thus can improve the operating efficiency of described non-volatile memory cells.
In other embodiments of the invention, described channel layer 300 only filling part through hole, follow-up at the full described through hole of described channel layer 300 surface formation dielectric layer filling.
In other embodiments of the invention, other semi-conducting materials, such as silicon can also be formed in described through hole 101, then by high-temperature annealing process, make described silicon semiconductor material become monocrystalline silicon layer, as channel layer.
In other embodiments of the invention, after germanium silicon layer can also being formed in through hole, oxidation processes is carried out to described germanium silicon layer, form single crystal germanium layer and silicon oxide layer.
The thickness of described channel layer 300 can be less than 7nm, and to make described channel layer 300 have lower charge-trapping efficiency, the thickness of described channel layer 300 is less, lower to the capture rate of electric charge, thus can improve the performance of the resistance-variable storing device of formation.
Please refer to Fig. 5, remove described dummy gate layer 212(and please refer to Fig. 4), form groove 213.
Wet-etching technology is adopted to remove described dummy gate layer 212.In the present embodiment, the material of described dummy gate layer 212 is silicon nitride, and the etching solution that described wet-etching technology adopts is phosphoric acid solution.
The follow-up grid layer forming functional layer and be positioned at described storage medium layer surface in described groove 213.
Please refer to Fig. 6, please refer to Fig. 5 at described groove 213() inner wall surface formed functional layer 400.
Described functional layer 400 comprises the change resistance layer 401 being positioned at described groove inner wall surface, the metal level 402 being positioned at described change resistance layer 401 surface.
The material of described change resistance layer 401 is binary metal oxide, and the material of described change resistance layer 401 can be HfO
2, TiO
2, Ta
2o
5or ZrO
2in one or more.
The material of described metal level 402 is the metal materials such as Hf, Ti, Ta or Zr.Concrete, the material of described metal level 402 is identical with the metallic element in described change resistance layer 401.
In the present embodiment, the material of described change resistance layer 401 is HfO
2, accordingly, the material of described metal level 401 is Hf.
Chemical vapor deposition method can be adopted to form described change resistance layer 401 and metal level 402.
In other embodiments of the invention, the material of described change resistance layer 401 is TiO
2, accordingly, the material of described metal level 401 is Ti.
Described metal level 402, change resistance layer 401 and channel layer 300 form the memory cell of resistance-variable storing device, by being applied to the voltage on metal level 402 and channel layer 300, the resistance of change resistance layer 401 is changed, makes changed by the electric current of described change resistance layer 401 and realize read-write capability.
Please refer to Fig. 7, formed on described functional layer 400 surface and fill full described groove 213(and please refer to Fig. 6) grid layer 403.
The material of described grid layer 403 be polysilicon, Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi one or more, the thickness of described grid layer 403 is 20nm ~ 50nm.The techniques such as chemical vapor deposition method, sputtering technology or evaporation can be adopted to form described grid layer 403.In the present embodiment, the material of described grid layer 403 is Al.
Adopt above-mentioned rear grid technique to form described grid layer 403, the heat budget that can avoid the formation of in the process of functional layer 400 and channel layer 300 etc. impacts performances such as the work functions of grid layer 403, thus avoids the performance affecting the resistance-variable storing device formed.
A kind of semiconductor structure adopting said method to be formed also is provided in the present embodiment.
Please refer to Fig. 7, Fig. 7 is the schematic diagram of described semiconductor structure.
Described semiconductor structure comprises: substrate 100; Be positioned at some insulating barriers 211 and some grid layers 403 of the stacked spaced apart on described substrate 100 surface; Be positioned at the through hole of described insulating barrier 211 and grid layer 403, described via bottoms is positioned at substrate 100 surface; Be positioned at the channel layer 300 on described through-hole wall surface; Functional layer 400 between described grid layer 403 and channel layer 300, between grid layer 403 and insulating barrier 211.
Described functional layer 400 comprises change resistance layer 401, is positioned at the metal level 402 on described change resistance layer 401 surface.The material of described change resistance layer 401 is binary metal oxide, can be HfO
2, TiO
2, Ta
2o
5or ZrO
2.The material of described metal level 402 is Hf, Ti, Ta or Zr, and the material of described metal level 402 can be identical with the metallic element in described change resistance layer 401.
The material of described insulating barrier 211 is silica, silicon nitride, silicon oxynitride, silicon oxide carbide or carbon silicon oxynitride, and the thickness of described insulating barrier 211 is 30nm ~ 60nm.
The material of described channel layer 300 is monocrystalline silicon, monocrystalline germanium or monocrystalline germanium SiClx.The thickness of described channel layer 300 is less than 7nm.Described channel layer 300 fills full described through hole.
Described semiconductor structure is random access memory unit, and described random access memory unit is stacked structure, can improve the integrated level of resistance-variable storing device.Further, the thickness of described channel layer is less than 7nm, and to make described channel layer have lower charge-trapping efficiency, the thickness of described channel layer is less, lower to the capture rate of electric charge, thus can improve the performance of the resistance-variable storing device of formation.
In another embodiment of the present invention, additionally provide a kind of formation method of semiconductor structure.
Please refer to Fig. 8, substrate 500 is provided, described substrate 500 is formed some insulating barriers 511 and the dummy gate layer 512 of stacked spaced apart, and is positioned at the through hole 501 of described some insulating barriers 511 and dummy gate layer 512.
The material of described insulating barrier 511 is silica, silicon nitride, silicon oxynitride, silicon oxide carbide or carbon silicon oxynitride, and doped with N-type impurity ion or p type impurity ion in described insulating barrier 511, the mass fraction of described N-type impurity ion or p type impurity ion is 6% ~ 14%.
When semiconductor structure to be formed is nmos pass transistor, doped with N-type impurity ion in described insulating barrier 511; When semiconductor structure to be formed is PMOS transistor, doped with p type impurity ion in described insulating barrier 511.The thickness of described insulating barrier 511 is 30nm ~ 60nm.The technique such as chemical vapour deposition (CVD), physical vapour deposition (PVD) can be adopted to form described insulating barrier 511.In the present embodiment, semiconductor structure to be formed is PMOS transistor, and the material of described insulating barrier 511 is the silica of boron-doping, and wherein the mass fraction of boron is 10%.
The material of described dummy gate layer 512 also can be the insulating dielectric materials such as silica, silicon nitride, silicon oxynitride, silicon oxide carbide or carbon silicon oxynitride, and described dummy gate layer 512 is different materials from insulating barrier 511.The thickness of described dummy gate layer 512 is 20nm ~ 50nm.Chemical vapor deposition method can be adopted to form described dummy gate layer 512.In the present embodiment, the material of described dummy gate layer 512 is silicon nitride.
What be positioned at described substrate 500 surface is insulating barrier 511, and described insulating barrier 511 is as the isolation structure between substrate 500 and the grid layer of follow-up formation, and the isolation structure between neighboring gates layer.Further, the Doped ions in described insulating barrier can also as the ion source forming source-drain area.
Please refer to Fig. 9, form layer of channel material 601 in described through hole 501 inner wall surface.
Adopt chemical vapor deposition method or sputtering technology, described layer of channel material 601 is formed in described through hole 501 inner wall surface, layer of channel material 601 described in the present embodiment is silicon germanide layer, follow-up oxidation processes is carried out to described layer of channel material 601, form the single crystal germanium layer being positioned at described through hole 501 inner wall surface, as channel layer.
Owing to adopting described chemical vapor deposition method or sputtering technology to form layer of channel material 601 at described through hole 501 inner wall surface Direct precipitation, so the material of the described layer of channel material 601 formed is non-crystalline material.
In other embodiments of the invention, the layer of channel material of crystallite or polycrystalline structure can also be formed.Material due to described layer of channel material 601 is not mono-crystalline structures, the mobility of follow-up charge carrier in layer of channel material 601 can be affected, and described layer of channel material 601 can have stronger capture ability to electronics, can reduce charge carrier quantity, the performance of the transistor that impact is formed.
In the present embodiment, the material of described layer of channel material 601 is SiGe, and wherein the content of germanium is 30% ~ 55%.
Please refer to Figure 10, Fig. 9 be please refer to described layer of channel material 601() carry out oxidation processes, form the channel layer 602 being positioned at through hole 501 inner wall surface and the oxide layer 603 being positioned at described channel layer 602 surface.
The thickness of channel layer 602 described in the present embodiment is less than 7nm.
In the present embodiment, the material of described layer of channel material 601 is SiGe, oxidation processes is carried out to described silicon germanide layer, germanium in described silicon germanide layer is separated out, formed and be positioned at the single crystal germanium layer of through hole 501 inner wall surface and be positioned at the silicon oxide layer on described single crystal germanium layer surface, described single crystal germanium layer is as channel layer 602, and described silicon oxide layer is oxide layer 603.
Described oxidation processes is the annealing in process under oxygen atmosphere, and described oxidation processes is the annealing process under oxygen atmosphere, and temperature is 600 DEG C ~ 1000 DEG C, and oxygen concentration is 10% ~ 80%, and annealing time is 20min ~ 200min.In annealing process under described oxygen atmosphere, described oxygen atom can destroy the silicon-germanium key in SiGe, form silica, and germanium atom again crystallization can form monocrystalline germanium under high annealing, because the surface of oxygen atom with described germanium silicon layer contacts, at first so described silicon oxide layer is formed in the surface of single crystal germanium layer, and because the lattice structure constant of silicon oxide layer is comparatively large, the described single crystal germanium layer of formation and the gross thickness of silicon oxide layer are greater than the gross thickness of not oxidized germanium silicon layer before treatment.
In other embodiments of the invention, amorphous silicon layer or amorphous germanium layer can also be formed in the inner wall surface of described through hole 501, then high-temperature annealing process is passed through, described amorphous silicon layer or amorphous germanium layer is made to become monocrystalline silicon layer, or single crystal germanium layer, described high-order annealing process can be rapid thermal annealing, spike annealing or laser annealing technique, and described annealing in process is carried out under atmosphere of inert gases, the temperature of described annealing in process is 500 DEG C ~ 800 DEG C, and annealing time is 4 hours ~ 6 hours.
In the present embodiment, the oxide skin(coating) 603 on described channel layer 602 and surface thereof does not fill completely described through hole 501, follow-up can in described through hole 501 filled media material, described through hole 501 is filled up.
Please refer to Figure 11, form dielectric layer 604 on described oxide skin(coating) 603 surface, described dielectric layer 604 is filled full described through hole 501(and be please refer to Figure 10).
The material of described dielectric layer 604 can be silica, silicon nitride, silicon oxynitride, silicon oxide carbide or carbon silicon oxynitride layer insulating dielectric materials.The method forming described dielectric layer 604 can be chemical vapor deposition method, high-density plasma deposition process, atom layer deposition process etc.
The method forming described dielectric layer 604 comprises: deposits dielectric materials in described through hole 501, and full described through hole filled by described dielectric material, and covers the insulating barrier 511 being positioned at top layer; Using the insulating barrier 511 of described top layer as stop-layer, planarization is carried out to above-mentioned dielectric material, form dielectric layer 604.
After the described dielectric layer 604 of formation, can also annealing in process be carried out, make the Doped ions in described insulating barrier 511, diffuse in described channel layer 602, in described channel layer 602, form doped region, as source-drain area.In other embodiments of the invention, after the described channel layer 602 of formation, annealing in process can be carried out, in described channel layer 602, forms source-drain area, and then form described dielectric layer 604.The temperature of described annealing in process is 400 DEG C ~ 800 DEG C, and annealing time is 3min ~ 10min.
Please refer to Figure 12, remove described dummy gate layer 512(and please refer to Figure 11), form groove 513.
Wet-etching technology is adopted to remove described dummy gate layer 512.In the present embodiment, the material of described dummy gate layer 512 is silicon nitride, and the etching solution that described wet-etching technology adopts is phosphoric acid solution.
The follow-up grid layer forming functional layer and be positioned at described functional layer surface in described groove 513.
Please refer to Figure 13, form functional layer 605 in the inner wall surface of described groove 513.
The material of described functional layer 605 is low-K dielectric material, as the gate dielectric layer of transistor.
The material of described functional layer 605 can be HfO
2, La
2o
3, HfSiON, HfAlO
2, SiO
2, ZrO
2, Al
2o
3in one or more.In the present embodiment, the material of described functional layer 605 is HfO
2.
Before the described dummy grid 512 of removal, carry out annealing in process, make the Doped ions in described insulating barrier 511 diffuse in channel layer 602, form source-drain area, the doping content in described insulating barrier 511 can be reduced.In the process forming described functional layer 605, the Doped ions in described insulating barrier 511 is avoided to diffuse in described functional layer 605, the performance of the final transistor formed of impact.
Chemical vapor deposition method or atom layer deposition process can be adopted to form described functional layer 605.
Please refer to Figure 14, formed on described functional layer 605 surface and fill full described groove 513(and please refer to Figure 13) grid layer 606.
The material of described grid layer 606 be polysilicon, Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi one or more, the thickness of described grid layer 606 is 20nm ~ 50nm.The techniques such as chemical vapor deposition method, sputtering technology or evaporation can be adopted to form described grid layer 606.In the present embodiment, the material of described grid layer 606 is Al.
Adopt above-mentioned rear grid technique to form described grid layer 606, the heat budget in the process forming the material layer such as functional layer 605, channel layer 602 can be avoided to impact performances such as the work functions of grid layer 606, thus avoid the performance affecting the transistor formed.
In the present embodiment, also provide a kind of semiconductor structure adopting said method to be formed.
Please refer to Figure 14, Figure 14 is the schematic diagram of above-mentioned semiconductor structure.
Described semiconductor structure comprises: substrate 500; Be positioned at some insulating barriers 511 and some grid layers 606 of the stacked spaced apart on described substrate 500 surface; Be positioned at the through hole of described insulating barrier 511 and grid layer 606, described via bottoms is positioned at substrate 500 surface; Be positioned at the channel layer 602 on described through-hole wall surface; Functional layer 605 between described grid layer 606 and channel layer 602, between grid layer 606 and insulating barrier 511.
The material of described functional layer 605 is low-K dielectric material, can be HfO
2, La
2o
3, HfSiON, HfAlO
2, SiO
2, ZrO
2, Al
2o
3in one or more.In the present embodiment, the material of described functional layer 605 is HfO
2.
The material of described insulating barrier 511 is silica, silicon nitride, silicon oxynitride, silicon oxide carbide or carbon silicon oxynitride, and doped with N-type impurity ion or p type impurity ion in described insulating barrier.
The material of described grid layer 606 be polysilicon, Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi one or more, the thickness of described grid layer 606 is 20nm ~ 50nm.
The material of described channel layer 602 is monocrystalline silicon, monocrystalline germanium or monocrystalline germanium SiClx.The thickness of described channel layer 602 is less than 7nm.
In the present embodiment, also comprise the oxide skin(coating) 603 that is positioned at described channel layer 602 surface and be positioned at described oxide skin(coating) 603 surface and fill the dielectric layer 604 of full described through hole.
In the present embodiment, the semiconductor structure of formation is the transistor of stacked structure, and described transistor stack, in substrate, can improve the quantity of the transistor that unit area basis is formed, and improves the integrated level of semiconductor structure.And the channel layer of described transistor is mono-crystalline structures, can improve the carrier mobility of transistor, improve the performance of transistor.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. a formation method for semiconductor structure, is characterized in that, comprising:
Substrate is provided;
Some insulating barriers of stacked spaced apart and some dummy grid material layers is formed at described substrate surface;
In described insulating barrier and dummy grid material layer, form through hole, described via bottoms is positioned at substrate surface;
Channel layer is formed on described through-hole wall surface;
Remove dummy grid material layer, form groove;
Functional layer is formed on described groove inner wall surface;
Form grid layer on described functional layer surface, described grid layer fills full described groove.
2. the formation method of semiconductor structure according to claim 1, is characterized in that, described functional layer comprises the change resistance layer being positioned at described groove inner wall surface, the metal level being positioned at described change resistance layer surface.
3. the formation method of semiconductor structure according to claim 2, is characterized in that, the material of described insulating barrier is silica, silicon nitride, silicon oxynitride, silicon oxide carbide or carbon silicon oxynitride, and the thickness of described insulating barrier is 30nm ~ 60nm.
4. the formation method of semiconductor structure according to claim 2, is characterized in that, the material of described change resistance layer is binary metal oxide.
5. the formation method of semiconductor structure according to claim 4, is characterized in that, the material of described change resistance layer is HfO
2, TiO
2, Ta
2o
5or ZrO
2.
6. the formation method of semiconductor structure according to claim 2, is characterized in that, the material of described metal level is Hf, Ti, Ta or Zr.
7. the formation method of semiconductor structure according to claim 4, is characterized in that, the material of described metal level is identical with the metallic element in described change resistance layer.
8. the formation method of semiconductor structure according to claim 1, is characterized in that, the material of described functional layer is low-K dielectric material.
9. the formation method of semiconductor structure according to claim 8, it is characterized in that, the material of described insulating barrier is silica, silicon nitride, silicon oxynitride, silicon oxide carbide or carbon silicon oxynitride, and doped with N-type impurity ion or p type impurity ion in described insulating barrier.
10. the formation method of semiconductor structure according to claim 9, is characterized in that, the mass fraction of described N-type impurity ion or p type impurity ion is 6% ~ 14%.
The formation method of 11. semiconductor structures according to claim 9, it is characterized in that, also comprise: after the described channel layer of formation, carry out annealing in process, the Impurity Diffusion in described insulating barrier is made to enter in channel layer, form source-drain area, the temperature of described annealing is 400 DEG C ~ 800 DEG C, and annealing time is 3min ~ 10min.
The formation method of 12. semiconductor structures according to claim 3 or 9, it is characterized in that, the material of described channel layer is monocrystalline silicon, monocrystalline germanium or monocrystalline germanium SiClx.
The formation method of 13. semiconductor structures according to claim 12, is characterized in that, the thickness of described channel layer is less than 7nm.
The formation method of 14. semiconductor structures according to claim 13, is characterized in that, described channel layer fills full described through hole.
The formation method of 15. semiconductor structures according to claim 14, it is characterized in that, the material of described channel layer is monocrystalline germanium, the method forming described channel layer comprises: in described through hole, form the amorphous germanium layer of filling full described through hole, annealing in process is carried out to described amorphous germanium layer, makes described amorphous germanium layer change single crystal germanium layer into.
The formation method of 16. semiconductor structures stated according to claim 15, is characterized in that, described annealing in process is carried out under atmosphere of inert gases, and the temperature of described annealing in process is 500 DEG C ~ 800 DEG C, and annealing time is 4 hours ~ 6 hours.
The formation method of 17. semiconductor structures according to claim 13, is characterized in that, also comprise: form the dielectric layer of filling full described through hole at described channel layer surface.
The formation method of 18. semiconductor structures stated according to claim 17, it is characterized in that, the material of described channel layer is monocrystalline germanium, and the method forming described channel layer comprises: form silicon germanide layer on described storage medium layer surface, in described silicon germanide layer, the content of germanium is 30% ~ 55%; Oxidation processes is carried out to described silicon germanide layer, the germanium in described silicon germanide layer is separated out, formed and be positioned at the single crystal germanium layer on storage medium layer surface and be positioned at the silicon oxide layer on described single crystal germanium layer surface.
The formation method of 19. semiconductor structures stated according to claim 18, is characterized in that, described oxidation processes is the annealing process under oxygen atmosphere, and temperature is 600 DEG C ~ 1000 DEG C, and oxygen concentration is 10% ~ 80%, and annealing time is 20min ~ 200min.
20. semiconductor structures formed according to the formation method of the semiconductor structure in claim 1 to claim 19 described in any one claim, is characterized in that, comprising:
Substrate;
Be positioned at some insulating barriers of the stacked spaced apart of described substrate surface and some grid layers;
Be positioned at the through hole of described insulating barrier and grid layer, described via bottoms is positioned at substrate surface;
Be positioned at the channel layer on described through-hole wall surface;
Functional layer between described grid layer and channel layer, between grid layer and insulating barrier.
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