CN104752433A - Nonvolatile memory cell and forming method thereof - Google Patents
Nonvolatile memory cell and forming method thereof Download PDFInfo
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- CN104752433A CN104752433A CN201310745767.2A CN201310745767A CN104752433A CN 104752433 A CN104752433 A CN 104752433A CN 201310745767 A CN201310745767 A CN 201310745767A CN 104752433 A CN104752433 A CN 104752433A
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Abstract
Provided are a nonvolatile memory cell and a forming method thereof. The nonvolatile memory cell comprises a substrate, a plurality of insulation layers, a plurality of grid electrode layers, channel layers and storage dielectric layers, wherein the insulation layers and the grid electrode layers are located on the substrate and are stacked at intervals, and through holes perpendicular to the substrate are formed in the insulation layers and the grid electrode layers, the channel layers are located in the through holes, the surfaces of the channel layers are flush with the tops of the through holes, and the storage dielectric layers are located between the grid electrode layers and the channel layer. The nonvolatile memory cell can improve the integration level of a nonvolatile memory.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of non-volatile memory cells and forming method thereof.
Background technology
Usually, semiconductor memory for storing data is divided into volatile memory and nonvolatile memory, obliterated data when volatile memory is easy to break in the supply, even and if nonvolatile memory still can keep the data in memory after power supply is closed.Nonvolatile semiconductor memory has the advantages that cost is low, density is large.Therefore, nonvolatile memory is widely used in every field, comprise embedded system, such as computer, switch, cell phone, network interconnection apparatus, network interconnection, instrument and meter and automobile device, also comprise emerging voice, image, data storage class product, such as digital camera, digital recorder etc. simultaneously.
In recent years, there is the silicon-oxide-nitride--nonvolatile memory of oxide-silicon (SONOS) structure obtain and study widely, the memory of described SONOS structure is convenient to manufacture and compatible with the manufacturing process of integrated circuit, in the outer peripheral areas being convenient to be formed in integrated circuit and logic region.In described oxidenitride oxide structure, nitride layer is used for trapped electrons, and described oxidenitride oxide structure instead of the floating gate structure in legacy memory.
In the Nonvolatile memery unit of existing oxidenitride oxide structure, described oxide-nitride-oxide layer is generally all formed directly into substrate surface, occupy larger chip area, the integrated level of described nonvolatile memory need further raising.
Summary of the invention
The problem that the present invention solves is to provide a kind of non-volatile memory cells and forming method thereof, improves the integrated level of nonvolatile memory.
For solving the problem, the invention provides a kind of non-volatile memory cells, comprising: substrate; Be positioned at some insulating barriers of suprabasil stacked spaced apart and some grid layers, in grid layer and insulating barrier, be formed with the through hole perpendicular to substrate; Be positioned at the channel layer of described through hole, the surface of described channel layer flushes with via top; Storage medium layer between described grid layer and channel layer.
Optionally, described storage medium layer comprise be positioned at grid layer sidewall surfaces the first oxide skin(coating), be positioned at the nitride layer of described first oxide layer surface and be positioned at the second oxide skin(coating) of described nitride layer surface.
Optionally, described first oxide skin(coating) is silica, nitride layer is silicon nitride, the second oxide skin(coating) is silica; Or described first oxide skin(coating) is oxygen calorize hafnium, nitride layer is hafnium nitride, the second oxide skin(coating) is oxygen calorize hafnium.
Optionally, the thickness of described first oxide skin(coating) is 0.1nm ~ 1nm, and the thickness of described nitride layer is 1nm ~ 2nm, and the thickness of the second oxide skin(coating) is 0.1nm ~ 1nm.
Optionally, described storage medium layer covers the sidewall surfaces of through hole.
Optionally, the described storage medium layer also upper surface of cover gate layer and lower surface.
Optionally, the material of described insulating barrier is silica, silicon nitride, silicon oxynitride, silicon oxide carbide or carbon silicon oxynitride, and the thickness of described insulating barrier is 30nm ~ 60nm.
Optionally, the material of described grid layer be polysilicon, Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi one or more, the thickness of described grid layer is 20nm ~ 50nm.
Optionally, the material of described channel layer is silicon, germanium or SiGe.
Optionally, the thickness of described channel layer is less than 7nm.
Optionally, described channel layer fills full described through hole.
Optionally, the dielectric layer being positioned at the full described through hole of described channel layer surface filling is also comprised.
Technical scheme of the present invention also provides a kind of formation method of above-mentioned non-volatile memory cells, comprising: provide substrate; Formed and be positioned at some insulating barriers of suprabasil stacked spaced apart and some grid layers; The through hole perpendicular to substrate is formed in described grid layer and insulating barrier; Form the channel layer being positioned at described through hole, the surface of described channel layer flushes with via top; Form the storage medium layer between described grid layer and channel layer.
Optionally, the formation method of described channel layer and storage medium layer comprises: form storage medium layer on described through-hole wall surface, form channel layer on described storage medium layer surface, the thickness of described channel layer is less than 7nm.
Optionally, the formation method of described grid layer, storage medium layer and channel layer comprises: formed and be positioned at some insulating barriers of suprabasil stacked spaced apart and some dummy grid material layers; In described insulating barrier and dummy grid material layer, form through hole, described via bottoms is positioned at substrate surface; Channel layer is formed in described through hole; Remove dummy grid material layer, form groove; Storage medium layer is formed on described groove inner wall surface; Form grid layer on described storage medium layer surface, described grid layer fills full described groove.
Optionally, described channel layer is silicon, germanium or SiGe.
Optionally, the material of described channel layer is germanium, and the method forming described germanium channel layer comprises: form silicon germanide layer on described storage medium layer surface, in described silicon germanide layer, the content of germanium is 30% ~ 55%; Oxidation processes is carried out to described silicon germanide layer, the germanium in described silicon germanide layer is separated out, formed and be positioned at the single crystal germanium layer on storage medium layer surface and be positioned at the silicon oxide layer on described single crystal germanium layer surface.
Optionally, described oxidation processes is the annealing process under oxygen atmosphere, and temperature is 600 DEG C ~ 1000 DEG C, and oxygen concentration is 10% ~ 80%, and annealing time is 20min ~ 200min.
Optionally, described channel layer fills full described through hole.
Optionally, also comprise: form the dielectric layer of filling full described groove at described channel layer surface.
Compared with prior art, technical scheme of the present invention has the following advantages:
In technical scheme of the present invention, described non-volatile memory cells is formed with some insulating barriers of stacked spaced apart and some grid layers at substrate surface; The through hole perpendicular to substrate is formed in described grid layer and insulating barrier; In described through hole, form channel layer, and be formed with storage medium layer between described grid layer and channel layer.The grid layer of described non-volatile memory cells is vertical stack, insulating barrier is as the isolation structure between neighboring gates layer, the quantity of the described non-volatile memory cells that the substrate of unit are is formed can be improved like this, improve the integrated level of nonvolatile memory.
Further, the thickness of described channel layer is less than 7nm, can reduce the capture ability of described channel layer to electric charge; The thickness of described channel layer is less, less to the effect of catching of the electric charge in channel layer, can improve the efficiency that electronics passes in and out described storage medium layer, thus improve the read-write efficiency of described Nonvolatile memery unit.
Further, in the process forming described Nonvolatile memery unit, some insulating barriers of stacked spaced apart and some dummy grid material layers can first be formed in substrate; Through hole is formed in described insulating barrier and dummy grid material layer; Channel layer is formed in described through hole; Remove dummy grid material layer, form groove; Storage medium layer is formed on described groove inner wall surface; Form grid layer on described storage medium layer surface, described grid layer fills full described groove.After channel layer and storage medium layer are formed, form described grid layer again, the heat budget forming described channel layer and storage medium layer can be avoided to impact performances such as the work functions of grid layer, thus avoid the performance affecting the non-volatile memory cells formed.
Accompanying drawing explanation
Fig. 1 to Figure 14 is the structural representation of the forming process of the non-volatile memory cells of embodiments of the invention.
Embodiment
As described in the background art, the non-volatile memory cells that prior art is formed is formed directly into semiconductor substrate surface, and occupy larger chip area, integrated level is not high.
In embodiments of the invention, form the non-volatile memory cells of stacked structure, the integrated level of nonvolatile memory can be improved.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Please refer to Fig. 1, substrate 100 is provided.
The material of described substrate 100 comprises the semi-conducting materials such as silicon, germanium, SiGe, GaAs, and described substrate 100 can be body material also can be that composite construction is as silicon-on-insulator.Those skilled in the art can select the type of described substrate 100 according to the semiconductor device that substrate 100 is formed, therefore the type of described Semiconductor substrate should not limit the scope of the invention.
Please refer to Fig. 2, described substrate 100 is formed some insulating barriers 201 and some gate material layers 202 of stacked spaced apart.
The material of described insulation material layer 201 is the insulating dielectric materials such as silica, silicon nitride, silicon oxynitride, silicon oxide carbide or carbon silicon oxynitride, and the thickness of described insulating barrier 201 is 30nm ~ 60nm.The technique such as chemical vapour deposition (CVD), physical vapour deposition (PVD) can be adopted to form described insulation material layer 201.In the present embodiment, the material of described insulation material layer 201 is silica.
The material of described gate material layers 202 be polysilicon, Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi one or more, the thickness of described gate material layers 202 is 20nm ~ 50nm.The techniques such as chemical vapor deposition method, sputtering technology or evaporation can be adopted to form described gate material layers 202.In the present embodiment, the material of described gate material layers 202 is polysilicon.
What be positioned at described substrate 100 surface is insulation material layer 201, and described insulation material layer 101 is as the isolation structure between substrate 100 and gate material layers 202, and the isolation structure between neighboring gates material layer 202.
Please refer to Fig. 3, please refer to Fig. 2 at described gate material layers 202() and insulation material layer 201(please refer to Fig. 1) in formed perpendicular to the through hole 101 of substrate 100, form grid layer 212 and insulating barrier 211.
The method forming described through hole 101 comprises: form Patterned masking layer on described insulation material layer 202 surface being positioned at top layer, have opening in described Patterned masking layer, described opening defines the cross sectional dimensions and position that need the through hole formed; Etch described insulation material layer 201 and gate material layers 202 to substrate 100 surface along described opening, form through hole 101; Then described Patterned masking layer is removed.In the present embodiment, the material of described Patterned masking layer can be photoresist layer, adopts cineration technics to remove described Patterned masking layer.
In the present embodiment, the cross section of described through hole 101 and circle, the diameter of described circle is 5nm ~ 200nm.
Dry etch process can be adopted to form described through hole 101, and concrete, the etching gas that described dry etch process adopts is: CF
4, C
2f
6, C
3f
8in one or more gases.
Described through hole 101 exposes the part surface of substrate 100.
After forming described through hole 101, Doped ions injection can be carried out to the substrate 100 bottom described through hole 101, form doped region, and carry out the described Doped ions of annealing activation; Described Doped ions is N-type ion, for the non-volatile memory cells of follow-up formation provides electronic carrier.
Please refer to Fig. 4, form storage medium layer 300 in the sidewall surfaces of described through hole 101.
Described storage medium layer 300 covers the sidewall surfaces of through hole 101, described storage medium layer 300 for be positioned at through-hole side wall surface the first oxide skin(coating) 301, be positioned at the nitride layer 302 on the first oxide skin(coating) 301 surface, be positioned at the stacked structure of second oxide skin(coating) 303 on nitride layer 302 surface, wherein said nitride layer 302 is as the trapping layer of electronics.The thickness of described first oxide 301 is 0.1nm ~ 1nm, and the thickness of described nitride layer 302 is 1nm ~ 2nm, and the thickness of the second oxide skin(coating) 303 is 0.1nm ~ 1nm.
In the present embodiment, the material of described first oxide skin(coating) 301 is silica, and the material of described nitride layer 302 is silicon nitride, and the material of the second oxide skin(coating) 302 is silica.
In other embodiments of the invention, the material of described first oxide skin(coating) 301 is oxygen calorize hafnium, and the material of nitride layer 302 is hafnium nitride, and the material of the second oxide skin(coating) 303 is oxygen calorize hafnium.
The method forming described storage medium layer is chemical vapor deposition method, adopt chemical vapor deposition method to form the first oxide skin(coating), nitride layer and the second oxide skin(coating) successively in the inner wall surface of described through hole, described first oxide skin(coating), nitride layer and the second oxide skin(coating) also cover the insulating barrier 211 of top layer; Using described insulating barrier 211 as stop-layer, planarization is carried out to described first oxide skin(coating), nitride layer and the second oxide skin(coating), remove part first oxide skin(coating), nitride layer and the second oxide skin(coating) that are positioned at described insulating barrier 211 surface.In other embodiments of the invention, part first oxide skin(coating) of through hole 101 lower surface, nitride layer and the second oxide skin(coating) can also be removed by etching technics.
Described storage medium layer 300 is as the part of the stored charge of memory cell, wherein nitride layer 302 is as the trapping layer of electric charge, described second oxide skin(coating) 303 is as the tunneling oxide layer between nitride layer 302 and the channel layer of follow-up formation, electronics in channel layer enters nitride layer 302 by tunneling effect by described second oxide skin(coating) 303, described first oxide skin(coating) 301 stops increasing as the isolation between nitride layer 302 and grid layer 212, avoids the electronics in nitride layer 302 to enter in grid layer 212.
Please refer to Fig. 5, form layer of channel material 304 on described storage medium layer 300 surface.
Adopt chemical vapor deposition method or sputtering technology, described layer of channel material 304 is formed on described storage medium layer 300 surface, layer of channel material 304 described in the present embodiment is silicon germanide layer, follow-up oxidation processes is carried out to described layer of channel material 304, formed be positioned at described storage medium layer 300 surface single crystal germanium layer as channel layer.
Layer of channel material 304 is formed at the surperficial Direct precipitation of described storage medium layer 300, so the described layer of channel material 304 formed is non-crystalline material owing to adopting described chemical vapor deposition method or sputtering technology.
In other embodiments of the invention, the layer of channel material of crystallite or polycrystalline structure can also be formed.The material of described layer of channel material 304 is not mono-crystalline structures, the mobility of follow-up charge carrier in layer of channel material 304 can be affected, and the capture ability of described layer of channel material 304 pairs of electronics, electronics can be reduced and then pierce into quantity in storage medium layer 300, follow-up described layer of channel material to be processed, form mono-crystalline channel layer.
In the present embodiment, the material of described layer of channel material 304 is SiGe, and wherein the content of germanium is 30% ~ 55%.
Please refer to Fig. 6, Fig. 5 be please refer to described layer of channel material 304() carry out oxidation processes, form the channel layer 305 being positioned at storage medium layer surface and the oxide layer 306 being positioned at described channel layer surface.
The thickness of channel layer 305 described in the present embodiment is less than 7nm.
In the present embodiment, the material of described layer of channel material 304 is SiGe, oxidation processes is carried out to described silicon germanide layer, the germanium in described silicon germanide layer is separated out, formed and be positioned at the single crystal germanium layer on storage medium layer surface and be positioned at the silicon oxide layer on described single crystal germanium layer surface.
Described oxidation processes is the annealing in process under oxygen atmosphere, and described oxidation processes is the annealing process under oxygen atmosphere, and temperature is 600 DEG C ~ 1000 DEG C, and oxygen concentration is 10% ~ 80%, and annealing time is 20min ~ 200min.In annealing process under described oxygen atmosphere, described oxygen atom can destroy the silicon-germanium key in SiGe, form silica, and germanium atom again crystallization can form monocrystalline germanium under high annealing, because the surface of oxygen atom with described germanium silicon layer contacts, at first so described silicon oxide layer is formed in the surface of single crystal germanium layer, and because the lattice structure constant of silicon oxide layer is comparatively large, the described single crystal germanium layer of formation and the gross thickness of silicon oxide layer are greater than the gross thickness of not oxidized germanium silicon layer before treatment.
In other embodiments of the invention, amorphous silicon layer or amorphous germanium layer can also be formed on described storage medium layer 300 surface, then high-temperature annealing process is passed through, described amorphous silicon layer or amorphous germanium layer is made to become monocrystalline silicon layer, or single crystal germanium layer, described high-order annealing process can be rapid thermal annealing, spike annealing or laser annealing technique, and described annealing in process is carried out under atmosphere of inert gases, the temperature of described annealing in process is 500 DEG C ~ 800 DEG C, and annealing time is 4 hours ~ 6 hours.
In the present embodiment, the oxide skin(coating) 306 on described channel layer 305 and surface thereof does not fill completely described through hole 101, follow-up can in described through hole 101 filled media material, described through hole 101 is filled up.
Please refer to Fig. 7, form dielectric layer 307 on described oxide skin(coating) 306 surface, described dielectric layer 307 is filled full described through hole 101(and be please refer to Fig. 6).
The material of described dielectric layer 307 can be silica, silicon nitride, silicon oxynitride, silicon oxide carbide or carbon silicon oxynitride layer insulating dielectric materials.The method forming described dielectric layer 307 can be chemical vapor deposition method, high-density plasma deposition process, atom layer deposition process etc.
The method forming described dielectric layer 307 comprises: deposits dielectric materials in described through hole 101, and full described through hole filled by described dielectric material, and covers the insulating barrier 211 being positioned at top layer; Using the insulating barrier 211 of described top layer as stop-layer, planarization is carried out to above-mentioned dielectric material, form dielectric layer 307.
Please refer to Fig. 8, is the vertical view of described non-volatile memory cells.
Described storage medium layer 300 and channel layer 305 are loop configuration, can improve the contact area of described storage medium layer 300 and channel layer 305, improve the control ability of described grid layer to electronics in channel layer 305.Further, the thickness of described channel layer 305 is less, and in the present embodiment, the thickness of described channel layer 305 is less than 7nm, and the thickness of described channel layer 305 is less, less to the effect of catching of the electric charge in channel layer 305, can improve the read-write efficiency of described memory cell.
And described memory cell is stacked structure, the quantity of the described non-volatile memory cells that the substrate 100 of unit are is formed can be improved, improve the integrated level of nonvolatile memory.
In the present embodiment, additionally provide a kind of non-volatile memory cells adopting said method to be formed.
Please refer to Fig. 7, is the structural representation of non-volatile memory cells formed in the present embodiment.
Described non-volatile memory cells comprises: substrate 100; Be positioned at some insulating barriers 211 and some grid layers 212 of the stacked spaced apart in substrate 100, in grid layer 212 and insulating barrier 211, be formed with the through hole perpendicular to substrate; Be positioned at the channel layer 305 of described through hole, the surface of described channel layer 305 flushes with via top; Storage medium layer 300 between described grid layer 212 and channel layer 305.
In the present embodiment, described storage medium layer 300 covers the inner wall surface of through hole.
Described storage medium layer 300 comprise be positioned at through-hole wall surface the first oxide skin(coating) 301, be positioned at the nitride layer 302 on described first oxide skin(coating) 301 surface and be positioned at second oxide skin(coating) 303 on described nitride layer 302 surface.
Described first oxide skin(coating) 301 is silica, nitride layer 302 is silicon nitride, the second oxide skin(coating) 303 is silica; In other embodiments of the invention, described first oxide skin(coating) 301 is oxygen calorize hafnium, nitride layer 302 is hafnium nitride, the second oxide skin(coating) 303 is oxygen calorize hafnium.
The thickness of described first oxide skin(coating) 301 is 0.1nm ~ 1nm, and the thickness of described nitride layer 302 is 1nm ~ 2nm, and the thickness of the second oxide skin(coating) 303 is 0.1nm ~ 1nm.
The material of described insulating barrier 211 is silica, silicon nitride, silicon oxynitride, silicon oxide carbide or carbon silicon oxynitride, and the thickness of described insulating barrier 211 is 30nm ~ 60nm.
The material of described grid layer 212 be polysilicon, Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi one or more, the thickness of described grid layer 212 is 20nm ~ 50nm.Described grid layer 212 is as control gate.
The material of described channel layer 305 is silicon, germanium or SiGe.Described channel layer 305 is mono-crystalline structures.The thickness of described channel layer is less than 7nm.
Also comprise: the oxide skin(coating) 306 being positioned at described channel layer 305 surface, and the dielectric layer 307 on described oxide skin(coating) 306 surface, described dielectric layer 307 fills full described through hole.
Described storage medium layer 300 and channel layer 305 are loop configuration, can improve the contact area of described storage medium layer 300 and channel layer 305, improve the control ability of described grid layer to electronics in channel layer 305.Further, the thickness of described channel layer 305 is less, and in the present embodiment, the thickness of described channel layer 305 is less than 7nm; The thickness of described channel layer 305 is less, less to the effect of catching of the electric charge in channel layer 305, can improve the read-write efficiency of described memory cell.
Further, described memory cell is stacked structure, can improve the quantity of the described non-volatile memory cells that the substrate 100 of unit are is formed, improve the integrated level of nonvolatile memory.
Embodiments of the invention also provide the another kind formation method of described non-volatile memory cells.
Please refer to Fig. 9, substrate 400 is provided, form insulation material layer 501 and the dummy grid material layer 502 of stacked spaced apart on described substrate 400 surface.
The material of described insulation material layer 501 is the insulating dielectric materials such as silica, silicon nitride, silicon oxynitride, silicon oxide carbide or carbon silicon oxynitride, and the thickness of described insulating barrier 501 is 30nm ~ 60nm.The technique such as chemical vapour deposition (CVD), physical vapour deposition (PVD) can be adopted to form described insulation material layer 501.In the present embodiment, the material of described insulation material layer 501 is silica.
The material of described dummy grid material layer 502 also can be the insulating dielectric materials such as silica, silicon nitride, silicon oxynitride, silicon oxide carbide or carbon silicon oxynitride, and described dummy grid material layer 502 is different materials from insulation material layer 501.The thickness of described dummy grid material layer 502 is 20nm ~ 50nm.Chemical vapor deposition method can be adopted to form described dummy grid material layer 502.In the present embodiment, the material of described dummy grid material layer 502 is silicon nitride.
What be positioned at described substrate 400 surface is insulation material layer 501, and described insulation material layer 501 is as the isolation structure between substrate 400 and the grid layer of follow-up formation, and the isolation structure between neighboring gates layer.
Please refer to Figure 10, please refer to Fig. 9 at described dummy grid material layer 502() and insulation material layer 501(please refer to Fig. 9) in formed perpendicular to the through hole 401 of substrate 400, form dummy gate layer 512 and insulating barrier 511.
The method forming described through hole 401 is identical with the formation method of the through hole in a upper embodiment, and therefore not to repeat here.
In the present embodiment, the cross section of described through hole 401 and circle, the diameter of described circle is 30nm ~ 200nm.
Dry etch process can be adopted to form described through hole 401, and concrete, the etching gas that described dry etch process adopts is: CF
4, C
2f
6, C
3f
8in one or more gases.
Described through hole 401 exposes the part surface of substrate 400.
After forming described through hole 401, Doped ions injection can be carried out to the substrate 400 bottom described through hole 401, form doped region, and carry out the described Doped ions of annealing activation; Described Doped ions is N-type ion, for the non-volatile memory cells of follow-up formation provides electronic carrier.
Please refer to Figure 11, in described through hole 401, form the channel layer 604 of filling full described through hole 401.
The material of described channel layer 604 is silicon, germanium or SiGe, and the material of described raceway groove 604 is mono-crystalline structures.
In the present embodiment, the material of described channel layer 604 is germanium.In described the present embodiment, the method forming described channel layer 604 is, deposition of Germanium material layer in described through hole, then annealing in process is carried out to described germanium material layer, described annealing in process is carried out under atmosphere of inert gases, and the temperature of described annealing in process is 500 DEG C ~ 800 DEG C, and annealing time is 4 hours ~ 6 hours, form monocrystalline germanium, as channel layer 604.The channel layer 604 of mono-crystalline structures has higher carrier mobility, and lower charge-trapping rate, thus can improve the operating efficiency of described non-volatile memory cells.
In other embodiments of the invention, the method in an embodiment can also be adopted to form described channel layer 604, and therefore not to repeat here.
In the present embodiment, the thickness of described channel layer 604 is less than 7nm.
Please refer to Figure 12, remove described dummy gate layer 512(and please refer to Figure 11), form groove 522.
Wet-etching technology is adopted to remove described dummy gate layer 512.In the present embodiment, the material of described dummy gate layer 512 is silicon nitride, and the etching solution that described wet-etching technology adopts is phosphoric acid solution.
The follow-up grid layer forming storage medium layer and be positioned at described storage medium layer surface in described groove 522.
Please refer to Figure 13, please refer to Figure 12 at described groove 522() inner wall surface formed storage medium layer 600.
Described storage medium layer 600 comprises the first oxide skin(coating) 601 being positioned at described groove 522 inner wall surface, the nitride layer 602 being positioned at the first oxide skin(coating) 601 surface, is positioned at the stacked structure of second oxide skin(coating) 603 on nitride layer 602 surface, and wherein said nitride layer 603 is as the trapping layer of electronics.The thickness of described first oxide 601 is 0.1nm ~ 1nm, and the thickness of described nitride layer 602 is 1nm ~ 2nm, and the thickness of the second oxide skin(coating) 603 is 0.1nm ~ 1nm.
In the present embodiment, the material of described first oxide skin(coating) 601 is oxygen calorize hafnium, and the material of described nitride layer 302 is hafnium nitride, and the material of the second oxide skin(coating) 302 is oxygen calorize hafnium.
Please refer to Figure 14, form the full described groove 522(of filling on described storage medium layer 600 surface and please refer to Figure 13) grid layer 605.
The material of described grid layer 605 be polysilicon, Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi one or more, the thickness of described grid layer 605 is 20nm ~ 50nm.The techniques such as chemical vapor deposition method, sputtering technology or evaporation can be adopted to form described grid layer 605.In the present embodiment, the material of described grid layer 605 is Al.
Above-mentioned rear grid technique is adopted to form described grid layer 605, the heat budget that can avoid the formation of in the process of storage medium layer 600 and channel layer 604 etc. impacts performances such as the work functions of grid layer 605, thus avoids the performance affecting the non-volatile memory cells formed.
In the present embodiment, also provide a kind of non-volatile memory cells adopting said method to be formed.
Please refer to Figure 14, is the structural representation of described non-volatile memory cells.
The structure of described non-volatile memory cells comprises: substrate 400; Be positioned at some insulating barriers 511 and some grid layers 605 of the stacked spaced apart in substrate 100, in grid layer 605 and insulating barrier 511, be formed with the through hole perpendicular to substrate 100; Be positioned at the channel layer 604 of described through hole 100, the surface of described channel layer 604 flushes with via top; Storage medium layer 600 between described grid layer 605 and channel layer 604.
Described storage medium layer 600 goes back upper surface and the lower surface of cover gate layer 605.
Described storage medium layer 600 comprises the first oxide skin(coating) 601, is positioned at the nitride layer 602 on described first oxide skin(coating) 601 surface and is positioned at second oxide skin(coating) 603 on described nitride layer 602 surface.
In the present embodiment, described first oxide skin(coating) 601 is oxygen calorize hafnium, nitride layer 602 is hafnium nitride, the second oxide skin(coating) 603 is oxygen calorize hafnium.In other embodiments of the invention, described first oxide skin(coating) 601 is silica, nitride layer 602 is silicon nitride, the second oxide skin(coating) 603 is silica.
The thickness of described first oxide skin(coating) 601 is 0.1nm ~ 1nm, and the thickness of described nitride layer 302 is 1nm ~ 2nm, and the thickness of the second oxide skin(coating) 603 is 0.1nm ~ 1nm.
The material of described insulating barrier 511 is silica, silicon nitride, silicon oxynitride, silicon oxide carbide or carbon silicon oxynitride, and the thickness of described insulating barrier 511 is 30nm ~ 60nm.
The material of described grid layer 605 be polysilicon, Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi one or more, the thickness of described grid layer 605 is 20nm ~ 50nm.In the present embodiment, the material of described grid layer 605 is Al.
The material of described channel layer 604 is silicon, germanium or SiGe.Described channel layer 604 is mono-crystalline structures.In the present invention, the thickness of described channel layer 604 is less than 7nm.
Described channel layer 604 is column structure, can improve the contact area of described storage medium layer 600 and channel layer 604, improves the control ability of described grid layer to electronics in channel layer 305.Further, the thickness of described channel layer 305 is less, and in the present embodiment, the thickness of described channel layer 305 is less than 7nm; The thickness of described channel layer 305 is less, less to the effect of catching of the electric charge in channel layer 305, can improve the read-write efficiency of described memory cell.
Further, described memory cell is stacked structure, can improve the quantity of the described non-volatile memory cells that the substrate 100 of unit are is formed, improve the integrated level of nonvolatile memory.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. a non-volatile memory cells, is characterized in that, comprising:
Substrate;
Be positioned at some insulating barriers of suprabasil stacked spaced apart and some grid layers, in grid layer and insulating barrier, be formed with the through hole perpendicular to substrate;
Be positioned at the channel layer of described through hole, the surface of described channel layer flushes with via top;
Storage medium layer between described grid layer and channel layer.
2. non-volatile memory cells according to claim 1, it is characterized in that, described storage medium layer comprise be positioned at grid layer sidewall surfaces the first oxide skin(coating), be positioned at the nitride layer of described first oxide layer surface and be positioned at the second oxide skin(coating) of described nitride layer surface.
3. non-volatile memory cells according to claim 2, is characterized in that, described first oxide skin(coating) is silica, nitride layer is silicon nitride, the second oxide skin(coating) is silica; Or described first oxide skin(coating) is oxygen calorize hafnium, nitride layer is hafnium nitride, the second oxide skin(coating) is oxygen calorize hafnium.
4. non-volatile memory cells according to claim 2, is characterized in that, the thickness of described first oxide skin(coating) is 0.1nm ~ 1nm, and the thickness of described nitride layer is 1nm ~ 2nm, and the thickness of the second oxide skin(coating) is 0.1nm ~ 1nm.
5. non-volatile memory cells according to claim 1, is characterized in that, described storage medium layer covers the sidewall surfaces of through hole.
6. non-volatile memory cells according to claim 1, is characterized in that, described storage medium layer is the upper surface of cover gate layer and lower surface also.
7. non-volatile memory cells according to claim 1, is characterized in that, the material of described insulating barrier is silica, silicon nitride, silicon oxynitride, silicon oxide carbide or carbon silicon oxynitride, and the thickness of described insulating barrier is 30nm ~ 60nm.
8. non-volatile memory cells according to claim 1, it is characterized in that, the material of described grid layer be polysilicon, Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi one or more, the thickness of described grid layer is 20nm ~ 50nm.
9. non-volatile memory cells according to claim 1, is characterized in that, the material of described channel layer is silicon, germanium or SiGe.
10. non-volatile memory cells according to claim 1, is characterized in that, the thickness of described channel layer is less than 7nm.
11. non-volatile memory cells according to claim 1, is characterized in that, described channel layer fills full described through hole.
12. non-volatile memory cells according to claim 1, is characterized in that, also comprise and are positioned at the dielectric layer that described channel layer surface fills full described through hole.
The formation method of 13. 1 kinds of non-volatile memory cells, is characterized in that, comprising:
Substrate is provided;
Formed and be positioned at some insulating barriers of suprabasil stacked spaced apart and some grid layers;
The through hole perpendicular to substrate is formed in described grid layer and insulating barrier;
Form the channel layer being positioned at described through hole, the surface of described channel layer flushes with via top;
Form the storage medium layer between described grid layer and channel layer.
The formation method of 14. non-volatile memory cells according to claim 13, it is characterized in that, the formation method of described channel layer and storage medium layer comprises: form storage medium layer on described through-hole wall surface, form channel layer on described storage medium layer surface, the thickness of described channel layer is less than 7nm.
The formation method of 15. non-volatile memory cells according to claim 13, it is characterized in that, the formation method of described grid layer, storage medium layer and channel layer comprises: formed and be positioned at some insulating barriers of suprabasil stacked spaced apart and some dummy grid material layers; In described insulating barrier and dummy grid material layer, form through hole, described via bottoms is positioned at substrate surface; Channel layer is formed in described through hole; Remove dummy grid material layer, form groove; Storage medium layer is formed on described groove inner wall surface; Form grid layer on described storage medium layer surface, described grid layer fills full described groove.
The formation method of 16. non-volatile memory cells according to claim 13, is characterized in that, described channel layer be silicon, germanium or SiGe.
The formation method of 17. non-volatile memory cells according to claim 13, it is characterized in that, the material of described channel layer is germanium, and the method forming described germanium channel layer comprises: form silicon germanide layer on described storage medium layer surface, in described silicon germanide layer, the content of germanium is 30% ~ 55%; Oxidation processes is carried out to described silicon germanide layer, the germanium in described silicon germanide layer is separated out, formed and be positioned at the single crystal germanium layer on storage medium layer surface and be positioned at the silicon oxide layer on described single crystal germanium layer surface.
The formation method of 18. non-volatile memory cells according to claim 17, it is characterized in that, described oxidation processes is the annealing process under oxygen atmosphere, and temperature is 600 DEG C ~ 1000 DEG C, oxygen concentration is 10% ~ 80%, and annealing time is 20min ~ 200min.
The formation method of 19. non-volatile memory cells according to claim 13, is characterized in that, described channel layer fills full described through hole.
The formation method of 20. non-volatile memory cells according to claim 13, is characterized in that, also comprise: form the dielectric layer of filling full described groove at described channel layer surface.
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