CN104752430A - Structure of AND and NOR-logic devices and making method - Google Patents
Structure of AND and NOR-logic devices and making method Download PDFInfo
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- CN104752430A CN104752430A CN201310752397.5A CN201310752397A CN104752430A CN 104752430 A CN104752430 A CN 104752430A CN 201310752397 A CN201310752397 A CN 201310752397A CN 104752430 A CN104752430 A CN 104752430A
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Abstract
The invention discloses a structure of AND and NOR-logic devices. The AND-logic device is made on a P-trap or P-type substrate, the P-trap or P-type substrate is connected to the ground, the upper face is provided with two neighboring control gates, for respectively controlling two neighboring n-type conducting channels which are connected in series; two ends of each control gate are provided with a highly doped n-type source region and a drain region, used as the leading-out ends of two n-type conducting channels; a polycrystalline silicon grid electrode is located above each control gate, and two polycrystalline silicon grid electrodes are mutually electrically separated and leaded out independently. The structure of the NOR-logic device is similar to the structure of the AND-logic device, the difference is to be made in a n-trap or n-type substrate, and the source and drain regions are the highly doped p-type. The invention further discloses a making method for the structure of AND and NOR-logic devices. The structure of the AND and NOR-logic devices is capable of, through designing the novel AND and NOR-logic device structure, simplifying the device and circuit structure, reducing the circuit area and making cost, and simplifying the sequential control of the circuit.
Description
Technical field
The present invention relates to IC manufacturing field, particularly relate to and structure with NOR-logic device and preparation method thereof.
Background technology
Tradition AND gate uses 6 MOS(metal-oxide semiconductor (MOS)s) transistor realization, comprise 3 nMOS (n trap NMOS N-channel MOS N) and 3 pMOS (p-type NMOS N-channel MOS N), as shown in Figure 1.The operation principle of AND gate is: when A and B two inputs are simultaneously for high level " 1 ", output Y is high level " 1 ", otherwise output Y is low level " 0 ".
Tradition NOR gate logical circuit uses 4 MOS transistor to realize, and comprises 2 nMOS and 2 pMOS, as shown in Figure 2.The operation principle of NOR gate logical circuit is: when A and B two inputs are simultaneously for high level " 1 ", output Y is low level " 0 ", otherwise output Y is high level " 1 ".
The shortcoming of these two kinds of logical circuits is that circuit structure is complicated, and chip occupying area is large, and cost is high.
Summary of the invention
One of the technical problem to be solved in the present invention is to provide a kind of with the structure with NOR-logic device, and its circuit structure is simple, and chip occupying area is little, and cost of manufacture is low.
For solving the problems of the technologies described above, the structure with logical device of the present invention, is produced in p trap or p-type substrate, p trap or p-type Substrate ground, has the gate grid that two are close to above, controls its lower two adjacent and N-shaped conducting channels of series connection separately; There are doped n-type source region and drain region in the two ends of gate grid, as the exit of two N-shaped conducting channels; Respectively there is a polysilicon gate top of gate grid, two mutual electric isolation of polysilicon gate and independent to draw.
The structure of NOR-logic device of the present invention, is produced in n trap or n-type substrate; N trap or n-type substrate ground connection, have the gate grid that two are close to above, controls separately its lower two adjacent and p-type electric-conducting raceway grooves of series connection; There are highly-doped p-type source region and drain region in the two ends of gate grid, as the exit of two p-type electric-conducting raceway grooves; Respectively there is a polysilicon gate top of gate grid, two mutual electric isolation of polysilicon gate and independent to draw.
Two of the technical problem to be solved in the present invention be to provide said structure with or the manufacture method of NOR-logic device.
For solving the problems of the technologies described above, the manufacture method with logic OR NOR-logic device of the present invention, step comprises:
1) on substrate, the isolation of device is formed by conventional MOS manufacture craft, and p trap and n trap;
2) oxide layer of thermal oxide growth first gate grid, depositing polysilicon also etches formation first polysilicon gate;
3) oxide layer of thermal oxide growth second gate grid, simultaneously first polysilicon gate surface oxidation forms the separator of two polysilicon gates;
4) depositing polysilicon etch formation second polysilicon gate;
5) oxidise polysilicon gate lateral wall and surface, and complete the injection of grid curb wall and N-shaped and p-type source and drain;
6) use the metal silicide of conventional MOS manufacture craft formation device surface, through hole and Metal Bonding Technology, complete the making of device.
Relative to traditional with door and NOR gate logical circuit, of the present inventionly to have the following advantages and beneficial effect with NOR-logic device:
1. device is relative with circuit structure simple, circuit layout only takies the area of about two standard MOS device, much smaller than traditional and door and NOR gate logical circuit 6 MOS structure, therefore can save circuit area, improve circuit level, reduce cost of manufacture.
2. only have two gate grid, therefore, the sequencing control of circuit is simpler.
3. utilize a step thermal oxidation technology to form the oxide layer of second gate grid and the separator of two grids, simplify technique, and two polysilicon gates are close to or overlapping, such two grid-controlled two raceway grooves just can be close to and connect, thus reduce total length and the circuit area of two raceway grooves, reduce circuit signal and postpone.
Accompanying drawing explanation
Fig. 1 is traditional AND gate structure.
Fig. 2 is traditional NOR gate logic circuit structure.
Fig. 3 is planar structure that is of the present invention and logical device.
Fig. 4 is cross-section structure that is of the present invention and logical device.
Fig. 5 ~ Fig. 9 is basic fabrication processing schematic diagram (profile) that is of the present invention and logical device.
Figure 10 be to of the present invention improved with the basic fabrication processing of logical device after, the device architecture profile (non-final structure chart) when side wall 12 is formed.
In figure, description of reference numerals is as follows:
A, B: input
T1、T2、T5：pmos
T3、T4、T6：nMOS
Y: output
1:p trap or p-type substrate
2: isolation
3,4: gate grid
5,7: polysilicon gate
6: gate lateral wall oxide-film
8,12: side wall
9:n type source-drain area
10:p type source-drain area
11:n trap
Embodiment
Understand more specifically for having technology contents of the present invention, feature and effect, now by reference to the accompanying drawings, details are as follows:
Of the present invention with logical device structure, refer to shown in Fig. 3,4.
Be produced in p trap or p-type substrate with logical device.There are the gate grid that two are close to above, control its lower adjacent N-shaped conducting channel separately.Have doped n-type source region and drain region at the two ends of gate grid, source region, two raceway grooves and drain region form the series connection raceway groove that there is extraction at two ends.Above two gate grid, respectively have a polysilicon gate, two polysilicon gates can at a distance of, adjacent or mutually overlapping, but must electric isolation mutually, and independently to draw.
Two nMOS(connected should be similar to the operation principle of logical device and degenerate to disappearance unlike its shared source-drain area).Two N-shaped conducting channels directly connect.Two mutual electric isolation of polysilicon gate are also independently drawn, as two input control ends.Two source-drain areas one are as input, and another is as output.Substrate or p trap ground connection.When two gate grid are all high potential, the N-shaped raceway groove of whole series connection is opened, and break-over of device, exports as high level; When there being one or two gate grid to be electronegative potential, the N-shaped raceway groove of whole series connection is not opened, and device not conducting exports as low level.So just achieve to input electric current and the switch control rule of logic.
The structure of NOR-logic device and the similar with logical device, unlike NOR-logic element manufacturing on n trap or n-type substrate, source-drain area is highly-doped p-type.The operation principle of NOR-logic device is similar to the pMOS of two series connection, only has when two gate grid are all electronegative potential, and the p-type raceway groove of two series connection is opened, and break-over of device exports high level; Otherwise device not conducting, output low level.So just achieve NOR-logic function.
Be described in detail with the manufacture method with NOR-logic device above-mentioned below.
For with logical device, its basic fabrication processing is as follows:
Step 1, selects p-type 110 substrate, resistivity 10 ~ 18 ohmcm, thickness 600 ~ 700 microns.
Step 2, by location oxidation of silicon process or trench isolation techniques, forms the isolation 2 of device, then carries out photo etched mask and the ion implantation of p trap 1 and n trap 11, as shown in Figure 5.The method that multistep can be adopted to inject is to obtain the CONCENTRATION DISTRIBUTION of comparatively ideal trap.
Step 3, the sacrificial oxide layer about thermal oxide growth 100 ~ 200 Ethylmercurichlorendimide, after wet method is removed, the oxide layer of growth regulation one deck gate grid 3, thickness 30 ~ 300 Ethylmercurichlorendimide.Then deposit a layer thickness is the doping (N-shaped) of 500 ~ 3000 Ethylmercurichlorendimides or plain polysilicon, and photo etched mask also etches the figure forming polysilicon gate 5, as shown in Figure 6.
Above step 1-3 is similar to conventional CMOS technology, but when etching polysilicon, residual oxidization film will have been carved, or the oxide-film of remained on surface is removed clean by the mode adding wet method by dry method.
Step 4, the oxide layer of thermal oxide growth second layer gate grid 4, thickness 30 ~ 300 Ethylmercurichlorendimide, as shown in Figure 7.Simultaneously can grow layer of oxide layer on the surface of polysilicon gate 5, i.e. gate lateral wall oxide-film 6, its thickness can be slightly thicker than the oxide layer of second layer gate grid 4), this layer of gate lateral wall oxide-film 6 is as the isolation of polysilicon gate 5 and polysilicon gate 7.
Step 5, the polysilicon of deposit another layer of doping or undoped, thickness 500 ~ 3000 dust, can be consistent with the ground floor polysilicon thickness of step 3 deposit.Then carry out photo etched mask and dry etching, form the figure of polysilicon gate 7, as shown in Figure 8.
When determining the layout patterns of two-layered polysilicon gate electrode, can be separated by a distance between polysilicon gate 7 and polysilicon gate 5, also can be adjacent or mutually overlapping.Mutually overlapping being of value to of polysilicon gate maintains good etch topography, therefore advise that polysilicon gate 7 and polysilicon gate 5 are mutually overlapping, but overlapping area is unsuitable excessive, preferably not more than the half of polysilicon gate 5 length, the excessive capacity effect that may cause between two-layered polysilicon gate electrode of overlapping area, is unfavorable for circuit reliability.
Step 6, the oxidation on polysilicon sidewall and surface, oxide thickness about 20 ~ 70 Ethylmercurichlorendimide, can increase the injection of light dope source and drain (LDD) if desired.Then carry out the deposit of silica or silicon nitride and anti-carve technique, forming the side wall 8(SPACER of polysilicon gate), then ion implantation forms heavily doped N-shaped source-drain area 9 and p-type source-drain area 10.As shown in Figure 7.
Step 7, forms the techniques such as the metal silicide of device surface, through hole and metal connect by traditional CMOS manufacture craft, completes the making of device.
As improvement, on above-mentioned basic fabrication processing basis, the deposit of oxidation step silicon or silicon nitride can be increased between step 3 and step 4, there is no mask to anti-carve, form side wall 12 at the periphery of polysilicon gate 5, strengthen the isolation between two polysilicon gates, as shown in Figure 8.Other step is identical with above-mentioned basic fabrication processing.
Claims (10)
1. with the structure of logical device, it is characterized in that, be produced in p trap or p-type substrate, p trap or p-type Substrate ground, have the gate grid that two be close tos above, control its lower two adjacent and N-shaped conducting channels of connecting separately; There are doped n-type source region and drain region in the two ends of gate grid, as the exit of two N-shaped conducting channels; Respectively there is a polysilicon gate top of gate grid, two mutual electric isolation of polysilicon gate and independent to draw.
2. structure according to claim 1, is characterized in that, two polysilicon gates are spaced, next-door neighbour or overlapping.
3. the structure of NOR-logic device, is characterized in that, is produced in n trap or n-type substrate; N trap or n-type substrate ground connection, have the gate grid that two are close to above, controls separately its lower two adjacent and p-type electric-conducting raceway grooves of series connection; There are highly-doped p-type source region and drain region in the two ends of gate grid, as the exit of two p-type electric-conducting raceway grooves; Respectively there is a polysilicon gate top of gate grid, two mutual electric isolation of polysilicon gate and independent to draw.
4. structure according to claim 1, is characterized in that, two polysilicon gates are spaced, next-door neighbour or overlapping.
5., with the manufacture method of logic OR NOR-logic device, it is characterized in that, step comprises:
1) on substrate, the isolation of device is formed by conventional MOS manufacture craft, and p trap and n trap;
2) oxide layer of thermal oxide growth first gate grid, depositing polysilicon also etches formation first polysilicon gate;
3) oxide layer of thermal oxide growth second gate grid, simultaneously first polysilicon gate surface oxidation forms the separator of two polysilicon gates;
4) depositing polysilicon etch formation second polysilicon gate;
5) oxidise polysilicon gate lateral wall and surface, and complete the injection of grid curb wall and N-shaped and p-type source and drain;
6) use the metal silicide of conventional MOS manufacture craft formation device surface, through hole and Metal Bonding Technology, complete the making of device.
6. method according to claim 5, is characterized in that, the thickness of the oxide layer of gate grid is 30 ~ 300 Ethylmercurichlorendimides.
7. method according to claim 5, is characterized in that, step 2) and 3) between, also comprise step: silicon oxide deposition or silicon nitride medium layer, anti-carve, form side wall at ground floor polysilicon gate periphery.
8. method according to claim 5, is characterized in that, the thickness of polysilicon gate is 500 ~ 3000 Ethylmercurichlorendimides.
9. method according to claim 5, is characterized in that, step 5), oxide thickness 20 ~ 70 Ethylmercurichlorendimide.
10. method according to claim 5, is characterized in that, step 5), after polysilicon gate sidewall and surface oxidation, carries out the injection of light dope source and drain.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113098493A (en) * | 2021-04-01 | 2021-07-09 | 长鑫存储技术有限公司 | Logic gate circuit structure |
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| CN102693945A (en) * | 2011-03-21 | 2012-09-26 | 飞思卡尔半导体公司 | Split-gate non-volatile memory cell having improved overlap tolerance and method therefor |
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| US20130267074A1 (en) * | 2012-04-09 | 2013-10-10 | Freescale Semiconductor Inc. | Integration technique using thermal oxide select gate dielectric for select gate and apartial replacement gate for logic |
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| CN100593859C (en) * | 2002-07-02 | 2010-03-10 | 桑迪士克股份有限公司 | Technique for fabricating logic elements using multiple gate layers |
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| CN102637601A (en) * | 2011-02-14 | 2012-08-15 | 中芯国际集成电路制造(上海)有限公司 | Forming method of MOS (metal oxide semiconductor) transistor with buried channel |
| CN102693945A (en) * | 2011-03-21 | 2012-09-26 | 飞思卡尔半导体公司 | Split-gate non-volatile memory cell having improved overlap tolerance and method therefor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113098493A (en) * | 2021-04-01 | 2021-07-09 | 长鑫存储技术有限公司 | Logic gate circuit structure |
| CN113098493B (en) * | 2021-04-01 | 2023-05-30 | 长鑫存储技术有限公司 | Logic gate circuit structure |
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