CN104752418A - Structures and manufacturing methods of or logic and nand logic devices - Google Patents
Structures and manufacturing methods of or logic and nand logic devices Download PDFInfo
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- CN104752418A CN104752418A CN201310752395.6A CN201310752395A CN104752418A CN 104752418 A CN104752418 A CN 104752418A CN 201310752395 A CN201310752395 A CN 201310752395A CN 104752418 A CN104752418 A CN 104752418A
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Abstract
The invention discloses structures of or logic and nand logic devices. The or logic device is manufactured in a grounded p well or p type substrate, and two parallel and close door control gates are arranged on the upper side to control two adjacent and parallel n-type conductive trenches on the lower side respectively; a highly doped n type source region and drain region are arranged at the two ends of the door control gates along the direction of the boundary of the two door control gates to serve as lead-out ends of the two trenches; a polycrystalline gate is arranged on each door control gate; the two polycrystalline silicon gates are mutually electrically isolated and led out independently to serve as two input ends of or logic; the structures of the nand logic device and the or logic device are similar; the difference is that the nand logic device and the or logic device are manufactured in the n well or the n type substrate, and the source and drain regions are highly doped p type. The invention also discloses manufacturing methods of the or and nand logic devices of the structures. By designing the novel or and nand logic device structures, the devices and the circuit structures are simplified, the circuit area and the manufacturing cost are reduced, and the time sequence control of the circuit is simpler.
Description
Technical field
The present invention relates to IC manufacturing field, particularly relate to or the structure and preparation method thereof of logic and NAND Logic device.
Background technology
Tradition or gate logic use 6 MOS(metal-oxide semiconductor (MOS)s) transistor realization, comprise 3 nMOS (n trap NMOS N-channel MOS N) and 3 pMOS (p-type NMOS N-channel MOS N), as shown in Figure 1.The operation principle of tradition or gate logic is: when A and B two inputs are all electronegative potential " 0 ", output Y is electronegative potential " 0 "; Otherwise output Y is high potential " 1 ".
Tradition NAND gate logical circuit uses 4 MOS transistor to realize, and comprises nMOS and two pMOS, as shown in Figure 2.The operation principle of tradition NAND gate logical circuit is: when A and B two inputs are all high potential " 1 ", output Y is electronegative potential " 0 "; Otherwise output Y is high potential " 1 ".
The shortcoming of these two kinds of logical circuits is that circuit structure is complicated, and chip occupying area is large, and cost is high.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of or logic and NAND Logic device structure, and its circuit structure is simple, and chip occupying area is little, and cost of manufacture is low.
For solving the problems of the technologies described above, the structure of of the present invention or logical device, is produced in p trap or p-type substrate, p trap or p-type Substrate ground, has two parallel connections above and the gate grid of next-door neighbour, controls its lower two adjacent and N-shaped conducting channels of parallel connection separately; On the direction along two gate grid boundary lines, there are doped n-type source region and drain region at the two ends of gate grid, as the exit of two N-shaped conducting channels; Gate grid respectively have a polysilicon gate, two mutual electric isolation of polysilicon gate also independently to be drawn, as or two inputs of logic.
The structure of NAND Logic device of the present invention, is produced in n trap or n-type substrate, n trap or n-type substrate ground connection, has two parallel connections above and the gate grid of next-door neighbour, controls separately its lower two adjacent and p-type electric-conducting raceway grooves of parallel connection; On the direction along two gate grid boundary lines, there are highly-doped p-type source region and drain region at the two ends of gate grid, as the exit of two p-type electric-conducting raceway grooves; Gate grid respectively have a polysilicon gate, two mutual electric isolation of polysilicon gate are also independently drawn, as two inputs of NAND Logic.
That two of the technical problem to be solved in the present invention is to provide said structure or logic and NAND Logic device manufacture method.
For solving the problems of the technologies described above, the manufacture method of of the present invention or logic OR NAND Logic device, step comprises:
1) on substrate, the isolation of device is formed by conventional MOS manufacture craft, and p trap and n trap;
2) oxide layer of thermal oxide growth first gate grid, depositing polysilicon also etches formation first polysilicon gate;
3) oxide layer of thermal oxide growth second gate grid, simultaneously first polysilicon gate surface oxidation forms the separator of two polysilicon gates;
4) depositing polysilicon etch formation second polysilicon gate;
5) oxidise polysilicon gate lateral wall and surface, and complete the injection of grid curb wall and N-shaped and p-type source and drain;
6) use the metal silicide of conventional MOS manufacture craft formation device surface, through hole and Metal Bonding Technology, complete the making of device.
Relative to traditional or door and NAND gate logical circuit, of the present invention or logic and NAND Logic device have the following advantages and beneficial effect:
1. device is relative with circuit structure simple, the area that circuit layout takies is slightly less than 2 standard MOS device, much smaller relative to the area shared by traditional 6MOS's or door and 4MOS's NAND gate structure, therefore saves circuit area, improve circuit level, reduce cost.
2. only have two gate grid, therefore the sequencing control of circuit is more simple.
3. utilize a step thermal oxidation technology to form the oxide layer of second gate grid and the separator of two grids, simplify technique, and two polysilicon gates are close to or overlapping, such two grid-controlled two raceway grooves just can be close to and connect, thus reduce total length and the circuit area of two raceway grooves, reduce circuit signal and postpone.
Accompanying drawing explanation
Fig. 1 is tradition or gate logic structure chart.
Fig. 2 is traditional NAND gate logic circuit structure figure.
Fig. 3 is of the present invention or the planar structure schematic diagram of logical device.
Fig. 4 is the cross-sectional view of device along the first cross section and the second cross section of Fig. 3.
Fig. 5-Fig. 9 is of the present invention or the basic fabrication processing schematic diagram (profile) of logical device.
Figure 10 is after being improved basic fabrication processing that is of the present invention or logical device, the device architecture profile (non-final structure chart) when side wall 10 is formed.
In figure, description of reference numerals is as follows:
A, B: input
T1、T2、T5：pmos
T3、T4、T6：nMOS
Y: output
1:P trap or P type substrate
2: isolation
3,4: gate grid
5,7: polysilicon gate
6: gate lateral wall oxide-film
8,10: side wall
9:n type source-drain area
Embodiment
Understand more specifically for having technology contents of the present invention, feature and effect, now by reference to the accompanying drawings, details are as follows:
Of the present invention or logical device structure, refers to shown in Fig. 3,4.
Or logical device, be produced in p trap or p-type substrate, have two parallel connections above and the gate grid of next-door neighbour, control its lower adjacent N-shaped conducting channel separately.Along on two gate grid boundary line directions, respectively there are a N-shaped source region and drain region at the two ends of gate grid.Like this, using source and drain as extraction, form two N-shaped raceway grooves in parallel.Two gate grid respectively have a polysilicon gate, two polysilicon gate interpolars can interval, adjacent or mutually overlapping, but must be mutual electric isolation, and independently draws, as or two inputs of logic.
Should or the operation principle of logical device be similar to two nMOS in parallel, two source-drain areas one as input, one as output, p-type substrate or p trap ground connection.When one or two in two grids is high potential, has one or two raceway groove and open, raceway groove conducting, export high potential; When two grids are all electronegative potential, the raceway groove of whole parallel connection is closed completely, exports electronegative potential.So just achieve to input electric current or signal or logic switch controlling functions.
The structure of NAND Logic device and or the similar of logical device, unlike NAND Logic element manufacturing on n trap or n-type substrate, source-drain area is highly-doped p-type.The operation principle of NAND Logic device is similar to two pMOS in parallel, when being electronegative potential when there being one or two grids, has one or two p-type raceway groove conductings, exports high potential; When two grids are all high potential, raceway groove is closed, and exports electronegative potential.So just achieve NAND Logic function.
Below above-mentioned or logic and NAND Logic device manufacture method is described in detail.
For or logical device, its basic fabrication processing is as follows:
Step 1, selects p-type 110 substrate, resistivity 10 ~ 18 ohmcm, thickness 600 ~ 700 microns.
Step 2, by location oxidation of silicon process or trench isolation techniques, forms the isolation 2 of device, then the photo etched mask of p-type trap 1 and ion implantation.The method that multistep can be adopted to inject is to obtain the CONCENTRATION DISTRIBUTION of comparatively ideal trap.As shown in Figure 5.
Step 3, the sacrificial oxide layer about thermal oxide growth 100 ~ 200 Ethylmercurichlorendimide, after wet method is removed, the oxide layer of growth regulation one deck gate grid 3, thickness 30 ~ 300 Ethylmercurichlorendimide.Then deposit a layer thickness is the doping (N-shaped) of 500 ~ 3000 Ethylmercurichlorendimides or plain polysilicon, and photo etched mask also etches the figure forming polysilicon gate 5, as shown in Figure 6.
Above step 1-3 is similar to conventional CMOS technology, but when etching polysilicon, residual oxidization film will have been carved, or the oxide-film of remained on surface is removed clean by the mode adding wet method by dry method.
Step 4, the oxide layer of thermal oxide growth second layer gate grid 4, thickness 30 ~ 300 Ethylmercurichlorendimide, as shown in Figure 7.Simultaneously can grow layer of oxide layer on the surface of polysilicon gate 5, i.e. gate lateral wall oxide-film 6, its thickness can be slightly thicker than the oxide layer of second layer gate grid 4), this layer of gate lateral wall oxide-film 6 is as the isolation of polysilicon gate 5 and polysilicon gate 7.
Step 5, the polysilicon of deposit another layer of doping or undoped, thickness 500 ~ 3000 dust, can be consistent with the ground floor polysilicon thickness of step 3 deposit.Then carry out photo etched mask and dry etching, form the figure of polysilicon gate 7, as shown in Figure 8.
When determining the layout patterns of two-layered polysilicon gate electrode, can be separated by a distance between polysilicon gate 7 and polysilicon gate 5, also can be adjacent or mutually overlapping.Mutually overlapping being of value to of polysilicon gate maintains good etch topography, therefore advise that polysilicon gate 7 and polysilicon gate 5 are mutually overlapping, but overlapping area is unsuitable excessive, preferably not more than the half of polysilicon gate 5 length, the excessive capacity effect that may cause between two-layered polysilicon gate electrode of overlapping area, is unfavorable for circuit reliability.
Step 6, the oxidation on polysilicon sidewall and surface, oxide thickness about 20 ~ 70 Ethylmercurichlorendimide, can increase the injection of light dope source and drain (LDD) if desired.Then carry out the deposit of silica or silicon nitride and anti-carve technique, forming the side wall 8(SPACER of polysilicon gate), then ion implantation forms N-shaped heavy-doped source drain region 9, as shown in Figure 9.
Step 7, forms the techniques such as the metal silicide of device surface, through hole and metal connect by traditional CMOS manufacture craft, completes the making of device.
As improvement, on above-mentioned basic fabrication processing basis, the deposit of oxidation step silicon or silicon nitride can be increased between step 3 and step 4, there is no mask to anti-carve, form side wall 10 at the periphery of polysilicon gate 5, strengthen the isolation between two polysilicon gates, as shown in Figure 10.Other step is identical with above-mentioned basic fabrication processing.
Claims (10)
1. or the structure of logical device, it is characterized in that, be produced in p trap or p-type substrate, p trap or p-type Substrate ground have two parallel connections above and the gate grid of next-door neighbour, control its lower two adjacent and N-shaped conducting channels of parallel connection separately; On the direction along two gate grid boundary lines, there are doped n-type source region and drain region at the two ends of gate grid, as the exit of two N-shaped conducting channels; Gate grid respectively have a polysilicon gate, two mutual electric isolation of polysilicon gate also independently to be drawn, as or two inputs of logic.
2. structure according to claim 1, is characterized in that, two polysilicon gates are spaced, next-door neighbour or overlapping.
3. the structure of NAND Logic device, is characterized in that, is produced in n trap or n-type substrate, n trap or n-type substrate ground connection, has two parallel connections above and the gate grid of next-door neighbour, controls separately its lower two adjacent and p-type electric-conducting raceway grooves of parallel connection; On the direction along two gate grid boundary lines, there are highly-doped p-type source region and drain region at the two ends of gate grid, as the exit of two p-type electric-conducting raceway grooves; Gate grid respectively have a polysilicon gate, two mutual electric isolation of polysilicon gate are also independently drawn, as two inputs of NAND Logic.
4. structure according to claim 3, is characterized in that, two polysilicon gates are spaced, next-door neighbour or overlapping.
5. or the manufacture method of logic OR NAND Logic device, it is characterized in that, step comprises:
1) on substrate, the isolation of device is formed by conventional MOS manufacture craft, and p trap and n trap;
2) oxide layer of thermal oxide growth first gate grid, depositing polysilicon also etches formation first polysilicon gate;
3) oxide layer of thermal oxide growth second gate grid, simultaneously first polysilicon gate surface oxidation forms the separator of two polysilicon gates;
4) depositing polysilicon etch formation second polysilicon gate;
5) oxidise polysilicon gate lateral wall and surface, and complete the injection of grid curb wall and N-shaped and p-type source and drain;
6) use the metal silicide of conventional MOS manufacture craft formation device surface, through hole and Metal Bonding Technology, complete the making of device.
6. method according to claim 5, is characterized in that, the thickness of the oxide layer of gate grid is 30 ~ 300 Ethylmercurichlorendimides.
7. method according to claim 5, is characterized in that, step 2) and 3) between, also comprise step: silicon oxide deposition or silicon nitride medium layer, anti-carve, form side wall at ground floor polysilicon gate periphery.
8. method according to claim 5, is characterized in that, the thickness of polysilicon gate is 500 ~ 3000 Ethylmercurichlorendimides.
9. method according to claim 5, is characterized in that, two polysilicon gates are spaced, next-door neighbour or overlapping.
10. method according to claim 5, is characterized in that, step 5), after polysilicon gate sidewall and surface oxidation, carries out the injection of light dope source and drain.
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| CN102637601A (en) * | 2011-02-14 | 2012-08-15 | 中芯国际集成电路制造(上海)有限公司 | Forming method of MOS (metal oxide semiconductor) transistor with buried channel |
| CN102687400A (en) * | 2009-10-30 | 2012-09-19 | 株式会社半导体能源研究所 | Logic circuit and semiconductor device |
| CN102693945A (en) * | 2011-03-21 | 2012-09-26 | 飞思卡尔半导体公司 | Split-gate non-volatile memory cell having improved overlap tolerance and method therefor |
| CN102737970A (en) * | 2011-04-01 | 2012-10-17 | 无锡华润上华半导体有限公司 | Semiconductor device and manufacturing method for gate dielectric layer thereof |
| US20130267074A1 (en) * | 2012-04-09 | 2013-10-10 | Freescale Semiconductor Inc. | Integration technique using thermal oxide select gate dielectric for select gate and apartial replacement gate for logic |
-
2013
- 2013-12-31 CN CN201310752395.6A patent/CN104752418A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1689168A (en) * | 2002-07-02 | 2005-10-26 | 桑迪士克股份有限公司 | Technique for fabricating logic elements using multiple gate layers |
| CN102687400A (en) * | 2009-10-30 | 2012-09-19 | 株式会社半导体能源研究所 | Logic circuit and semiconductor device |
| CN102637601A (en) * | 2011-02-14 | 2012-08-15 | 中芯国际集成电路制造(上海)有限公司 | Forming method of MOS (metal oxide semiconductor) transistor with buried channel |
| CN102693945A (en) * | 2011-03-21 | 2012-09-26 | 飞思卡尔半导体公司 | Split-gate non-volatile memory cell having improved overlap tolerance and method therefor |
| CN102737970A (en) * | 2011-04-01 | 2012-10-17 | 无锡华润上华半导体有限公司 | Semiconductor device and manufacturing method for gate dielectric layer thereof |
| US20130267074A1 (en) * | 2012-04-09 | 2013-10-10 | Freescale Semiconductor Inc. | Integration technique using thermal oxide select gate dielectric for select gate and apartial replacement gate for logic |
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