CN104752354A - Structure and manufacturing method of mask read-only memory - Google Patents
Structure and manufacturing method of mask read-only memory Download PDFInfo
- Publication number
- CN104752354A CN104752354A CN201310727957.1A CN201310727957A CN104752354A CN 104752354 A CN104752354 A CN 104752354A CN 201310727957 A CN201310727957 A CN 201310727957A CN 104752354 A CN104752354 A CN 104752354A
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- China
- Prior art keywords
- type
- polysilicon gate
- information unit
- memory
- mask read
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 34
- 229920005591 polysilicon Polymers 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 25
- 238000002347 injection Methods 0.000 claims abstract description 16
- 239000007924 injection Substances 0.000 claims abstract description 16
- 238000002955 isolation Methods 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 6
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 6
- 238000002513 implantation Methods 0.000 claims description 13
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 5
- -1 phosphonium ion Chemical class 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 239000007943 implant Substances 0.000 claims description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims 1
- 229910052785 arsenic Inorganic materials 0.000 claims 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical group [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 229910044991 metal oxide Inorganic materials 0.000 abstract 2
- 150000004706 metal oxides Chemical class 0.000 abstract 2
- 238000005516 engineering process Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
- H10B20/34—Source electrode or drain electrode programmed
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- Semiconductor Memories (AREA)
Abstract
The invention discloses a manufacturing method of a mask read-only memory. The method comprises the steps of 1) forming shallow isolation trenches and performing P trap injection, 2) forming N-type buried sources and drains, 3) forming polysilicon gates, first isolation side walls and second isolation side walls, 4) performing source and drain injection on an NMOS (N-channel Metal Oxide Semiconductor) and performing N-type doping on an area of an information unit "1", 5) performing source and drain injection on a PMOS (P-channel Metal Oxide Semiconductor) and performing P-type doping on an area of an information unit "0", and 6) forming metal silicide on the polysilicon gates to complete manufacturing of the mask read-only memory. According to the method, the information unit "1" adopts the N-type polysilicon gate and the information unit "0" adopts the P-type polysilicon gate by changing a code write-in method and a device structure of the mask read-only memory; and a difference between threshold voltage of the N-type polysilicon gate and the P-type polysilicon gate is about 1.12eV and is stable, so that write-in of information "0" is realized, and the device uniformity is ensured.
Description
Technical field
The present invention relates to IC manufacturing field, particularly relate to structure and the manufacture method of mask read-only memory.
Background technology
Read-only memory (Read-Only Memory) is a kind of memory that can only read data.The data of this memory write when producing.In the fabrication process, by data with special light shield (mask) burning in circuit, so be sometimes also called " mask read-only memory " (mask ROM).In fact it is the spitting image of the principle of CD CD, in the photo-etching technological process of semiconductor, be written with data mode.
The data of this mask read-only memory can not be changed after write, so data can not be lost, and its manufacturing cost is very low, and therefore, do not needing in the equipment of Data Update, Mask ROM is by use widely.
Traditional mask read-only memory, in order to realize high device density as far as possible, the grid of device and source and drain are all strips, spaced one by one, mutually vertical between grid and source-drain electrode, as shown in Figure 1.Owing to pursuing high density, the distance between the source and drain representing channel length always can be done little, does little.
The device cell of mask read-only memory is a N-type MOSFET (nmos device), and as shown in Figure 2, raceway groove is the trap of P type, and source and drain and polysilicon gate are N-type doping.The method of information " 0 " code write is after device is formed, the threshold voltage (VT) of device is improved by one extra P type ion implantation, namely make the raceway groove of this device cell have extra channel doping, finally there is higher channel dopant concentration.Have to pass through polysilicon gate because this road injects, the Implantation Energy therefore needed is comparatively large, and the impurity loss in injection process is more.Therefore, the device homogeneity of high threshold voltage is poor, causes the space between information " 0 " and " 1 " to diminish.In addition, the write of code also needs an extra light shield and the independent photoetching of a step and ion implantation technology, and therefore process costs is relatively high.
Summary of the invention
One of the technical problem to be solved in the present invention is to provide a kind of manufacture method of mask read-only memory, and its process uniformity is good, and cost is low.
For solving the problems of the technologies described above, the manufacture method of mask read-only memory of the present invention, step comprises:
1) on silicon substrate active area, form shallow isolation trench by existing technique, and carry out the injection of P trap;
2) be coated with N-type and bury source and drain photoresistance, exposure, carry out arsenic ion or phosphonium ion injection, form N-type and bury source and drain;
3) form polysilicon gate and the first isolation side walls, deposit silicon nitride dielectric layer, and return formation second at quarter isolation side walls;
4) source and drain injection is carried out to NMOS, N-type doping is carried out to the region of information unit " 1 " simultaneously;
5) source and drain injection is carried out to PMOS, the doping of P type is carried out to the region of information unit " 0 " simultaneously;
6) on polysilicon gate, form metal silicide, complete the making of mask read-only memory.
Two of the technical problem to be solved in the present invention is to provide the structure of the mask read-only memory manufactured with said method, and the polysilicon gate in the region of its information unit " 0 " is contrary with the doping type of the polysilicon gate in the region of information unit " 1 ".
The polysilicon gate in the region of described information unit " 1 " is N-type doping, and the polysilicon gate in the region of information unit " 0 " is the doping of P type.
The present invention is by improving code wiring method and the device architecture of mask read-only memory, (its threshold voltage is low to make information unit " 1 " still adopt the polysilicon gate of N-type, at operating voltage lower unit break-over of device), and information unit " 0 " adopts the polysilicon gate of P type, 1.12 electron-volts are only had an appointment because N-type differs with the device threshold voltage of P-type polysilicon gate pole, and this difference is stablized, the write of information " 0 " is achieved, and ensure that the process uniformity of device, reduce the manufacturing cost of device.
Accompanying drawing explanation
Fig. 1 is traditional mask read-only memory vertical view.
Fig. 2 is that traditional mask read-only memory is along the profile along grid direction.Wherein, metal silicide is not shown.
Fig. 3 ~ Figure 12 is the manufacturing process flow schematic diagram of the mask read-only memory of the embodiment of the present invention.Wherein, Fig. 3 ~ Fig. 7 is the profile burying source and drain direction along N-type, and Fig. 8 ~ Figure 10 is the profile along grid direction; Figure 11 is the profile of the mask read-only memory that finally manufactures of the present invention along grid direction; Figure 12 is mask read-only memory that the present invention finally manufactures buries source and drain direction profile along N-type.
Figure 13 is the information unit " 1 " (N-type polycrystalline silicon grid) of the mask read-only memory that the present invention manufactures and the input characteristic curve of " 0 " (P-type polysilicon gate).The difference of both threshold voltages is about 1.12 electron-volts.
Embodiment
Understand more specifically for having technology contents of the present invention, feature and effect, now by reference to the accompanying drawings, details are as follows:
The manufacture method of mask read-only memory of the present invention, its concrete technology step is as follows:
Step 1, the active area of silicon substrate forms shallow isolation trench, to isolate mask read-only memory region and peripheral circuit, as shown in Figure 3.
Step 2, carries out the injection of P trap in the active area of mask read-only memory, form the active area in P trap, as shown in Figure 4 (B figure is the vertical view after this step completes).
Step 3, coating N-type buries source and drain photoresistance, exposure, then carries out the less high dose arsenic ion of primary energy or phosphonium ion injection, forms N-type and bury source and drain, as shown in Figure 5.
The Implantation Energy that this step arsenic ion or phosphonium ion inject is 50 ~ 90keV, and implantation dosage is 5.8e14 ~ 6.1e15/cm
2, implant angle is 0 degree of inclination.
Step 4, form polysilicon gate and the first isolation side walls, then deposition thickness is
silicon nitride medium layer, as shown in Figure 6.
Step 5, carries out back carving to silicon nitride medium layer, forms the second isolation side walls, as shown in Figure 7.
Space between polysilicon gate is filled by the second isolation side walls completely, NMOS and PMOS source can be avoided like this to leak the N-type being injected into mask read-only memory when injecting buries in source and drain, also ensure that metal silicide is only formed on polysilicon gate simultaneously, and can not bury in source and drain in N-type and formed.
Step 6, while carrying out source and drain injection to NMOS, also carries out N-type doping to the region of the information unit " 1 " of mask read-only memory, the polysilicon gate in this region injects the N-type impurity of high concentration, as shown in Figure 8.
This step injects arsenic ion, and Implantation Energy is 21 ~ 48keV, and implantation dosage is 8e14 ~ 4.2e15/cm
2.
Step 7, while carrying out source and drain injection to PMOS, also carries out the doping of P type to the region of the information unit " 0 " of mask read-only memory, the polysilicon gate in this region injects the p type impurity of high concentration, as shown in Figure 9.
This step injects boron ion, and Implantation Energy is 5 ~ 15keV, and implantation dosage is 7.3e14 ~ 5.2e15/cm
2.
After this step completes, the N-type device of mask read-only memory is provided with the polysilicon gate (information unit " 1 ") of the polysilicon gate of P type (information unit " 0 ") and N-type, as shown in Figure 10.
Step 8, forms metal silicide on N-type polycrystalline silicon grid and P-type polysilicon gate, realizes the Electrode connection of grid.The structure of the mask read-only memory of final formation as shown in Figure 11,12.
Claims (6)
1. the manufacture method of mask read-only memory, is characterized in that, step comprises:
1) on silicon substrate active area, form shallow isolation trench by existing technique, and carry out the injection of P trap;
2) be coated with N-type and bury source and drain photoresistance, exposure, carry out arsenic ion or phosphonium ion injection, form N-type and bury source and drain;
3) form polysilicon gate and the first isolation side walls, deposit silicon nitride dielectric layer, and return formation second at quarter isolation side walls;
4) source and drain injection is carried out to NMOS, N-type doping is carried out to the region of information unit " 1 " simultaneously;
5) source and drain injection is carried out to PMOS, the doping of P type is carried out to the region of information unit " 0 " simultaneously;
6) on polysilicon gate, form metal silicide, complete the making of mask read-only memory.
2. method according to claim 1, is characterized in that, step 2), Implantation Energy is 50 ~ 90keV, and implantation dosage is 5.8e14 ~ 6.1e15/cm
2, implant angle is 0 degree of inclination.
3. method according to claim 1, is characterized in that, step 4), and implanted dopant is arsenic, and Implantation Energy is 21 ~ 48keV, and implantation dosage is 8e14 ~ 4.2e15/cm
2.
4. method according to claim 1, is characterized in that, step 5), and implanted dopant is boron, and Implantation Energy is 5 ~ 15keV, and implantation dosage is 7.3e14 ~ 5.2e15/cm
2.
5. the structure of the mask read-only memory manufactured by Claims 1-4 method described in any one, it is characterized in that, the polysilicon gate in the region of information unit " 0 " is contrary with the doping type of the polysilicon gate in the region of information unit " 1 ".
6. method according to claim 5, is characterized in that, the polysilicon gate in the region of information unit " 1 " is N-type doping, and the polysilicon gate in the region of information unit " 0 " is the doping of P type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310727957.1A CN104752354B (en) | 2013-12-25 | 2013-12-25 | The structure and manufacturing method of mask read-only memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310727957.1A CN104752354B (en) | 2013-12-25 | 2013-12-25 | The structure and manufacturing method of mask read-only memory |
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| Publication Number | Publication Date |
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| CN104752354A true CN104752354A (en) | 2015-07-01 |
| CN104752354B CN104752354B (en) | 2019-01-04 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6054353A (en) * | 1996-03-22 | 2000-04-25 | United Microelectronics Corporation | Short turn around time mask ROM process |
| US6177313B1 (en) * | 1998-10-02 | 2001-01-23 | Stmicroelectronics S.R.L. | Method for forming a muti-level ROM memory in a dual gate CMOS process, and corresponding ROM memory cell |
| US6326669B1 (en) * | 1999-04-22 | 2001-12-04 | Samsung Electronics Co., Ltd | Semiconductor device and method of making the same |
-
2013
- 2013-12-25 CN CN201310727957.1A patent/CN104752354B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6054353A (en) * | 1996-03-22 | 2000-04-25 | United Microelectronics Corporation | Short turn around time mask ROM process |
| US6177313B1 (en) * | 1998-10-02 | 2001-01-23 | Stmicroelectronics S.R.L. | Method for forming a muti-level ROM memory in a dual gate CMOS process, and corresponding ROM memory cell |
| US6326669B1 (en) * | 1999-04-22 | 2001-12-04 | Samsung Electronics Co., Ltd | Semiconductor device and method of making the same |
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| CN104752354B (en) | 2019-01-04 |
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