CN104752176B - The forming method of metal gates - Google Patents

The forming method of metal gates Download PDF

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CN104752176B
CN104752176B CN201310739022.5A CN201310739022A CN104752176B CN 104752176 B CN104752176 B CN 104752176B CN 201310739022 A CN201310739022 A CN 201310739022A CN 104752176 B CN104752176 B CN 104752176B
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groove
annealing
layer
dielectric layer
gate dielectric
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CN104752176A (en
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张海洋
张城龙
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/401—Multistep manufacturing processes

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Abstract

A kind of forming method of metal gates, including：Semiconductor substrate is provided, the Semiconductor substrate has PMOS area and NMOS area, the PMOS area is from top to bottom formed with the first high-K gate dielectric layer, the first barrier layer and the first dummy grid, the NMOS area also has interlayer dielectric layer from top to bottom formed with the second high-K gate dielectric layer, the second barrier layer and the second dummy grid in the Semiconductor substrate；Remove first dummy grid and form first groove；Air storage annealing is carried out to first barrier layer and first high-K gate dielectric layer；Remove second dummy grid and form second groove；Workfunction layers are formed in the bottom and side wall of the first groove and the second groove simultaneously；The full first groove and the second groove are filled using metal material simultaneously.The forming method simplifies manufacture craft, and reduces process costs.

Description

The forming method of metal gates
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, to a kind of forming method of metal gates.
Background technology
Main devices in integrated circuit especially super large-scale integration are Metal-oxide-semicondutor field-effects Transistor（Metal oxide semiconductor field effect transistor, abbreviation MOS transistor）.Since Since metal-oxide-semiconductor is by invention, its physical dimension is constantly reducing always.In the case, various limitations and technological challenge start Existing, the further diminution of device size is just becoming more and more difficult.With combined metal oxide semiconductor's structure (CMOS, Complementary Metal-Oxide-Semiconductor) manufacturing process tapers to below 32nm ranks, introduce use New design and the technology of material.In prepared by MOS transistor device and circuit, most challenging is that conventional CMOS device exists By polysilicon and silica during diminution（Or silicon oxynitride）The grid structural thickness of formation reduces the higher grid brought and let out Reveal electric current.Therefore, the solution having pointed out is, using metal gate and high-k（K）Gate medium substitutes traditional heavily doped Miscellaneous polysilicon gate and silica（Or silicon oxynitride）Gate medium.
The forming method of existing metal gates is as shown in Figures 1 to 5.
It refer to Fig. 1, there is provided Semiconductor substrate 100, Semiconductor substrate 100 have PMOS area and a NMOS area, in Fig. 1 The left-half region of Semiconductor substrate 100 is PMOS area, and the right half part of Semiconductor substrate 100 is NMOS area.In PMOS areas The first high-K gate dielectric layer 111, the first barrier layer 112 and the first dummy grid 113 are formed on domain, forms second on an nmos area High-K gate dielectric layer 121, the second barrier layer 122 and the second dummy grid 123, and form interlayer dielectric layer 101 and cover Semiconductor substrate 100, the surface of interlayer dielectric layer 101 and the first dummy grid 113 flush with the surface of the second dummy grid 123.
Fig. 2 is refer to, mask layer 102 is formed and protects the second dummy grid 123, and is mask with mask layer 102, etching removes First dummy grid 113 shown in Fig. 1, form the first groove 114.
Fig. 3 is refer to, the first workfunction layers 115 are formed in the bottom of the first groove 114 shown in Fig. 2 and side wall, it The first groove 114 shown in full Fig. 2 is filled until forming the first metal gates 116 with metal material again afterwards.
Fig. 4 is refer to, removes the dummy grid 123 of mask layer 102 and second shown in Fig. 3, forms the second groove 124.
Fig. 5 is refer to, the second workfunction layers 125 are formed in the bottom of the second groove 124 shown in Fig. 4 and side wall, it The second groove 124 shown in full Fig. 4 is filled until forming the second metal gates 126 with metal material again afterwards.
As seen from the above description, the forming method of existing metal gates needs to form difference respectively with different metal materials Workfunction layers, therefore, its complex manufacturing technology, and process costs are high.
For this reason, it may be necessary to a kind of forming method of new metal gates, with prevent from overcoming existing method complex manufacturing technology and The problem of process costs are high.
The content of the invention
It is of the invention to solve the problems, such as to be to provide a kind of forming method of metal gates, to simplify manufacture craft, and reduce work Skill cost.
To solve the above problems, the present invention provides a kind of forming method of metal gates, including：
Semiconductor substrate is provided, the Semiconductor substrate has PMOS area and NMOS area, and the PMOS area is under On formed with the first high-K gate dielectric layer, the first barrier layer and the first dummy grid, the NMOS area is from top to bottom formed with Two high-K gate dielectric layers, the second barrier layer and the second dummy grid, also there is interlayer dielectric layer, the layer in the Semiconductor substrate Between dielectric layer surface flushed with first dummy grid and the second dummy grid surface；
Remove first dummy grid and form first groove；
Air storage annealing is carried out to first barrier layer and first high-K gate dielectric layer；
Remove second dummy grid and form second groove；
Workfunction layers are formed in the bottom and side wall of the first groove and the second groove simultaneously；
The full first groove and the second groove are filled using metal material simultaneously.
Optionally, the air storage annealing is helium annealing or oxygen annealing processing.
Optionally, the temperature range that the helium annealing uses is 500 DEG C~1500 DEG C, the helium gas flow model of use Enclose for 10sccm~1000sccm, the annealing time used is 10s~600s.
Optionally, the temperature range that the oxygen annealing processing uses is 100 DEG C~400 DEG C, the oxygen flow model of use Enclose for 10sccm~1000sccm, the annealing time used is 1s~600s.
Optionally, after the first groove is formed, and before the helium annealing is carried out, the forming method is also Including：Processing is dried.
To solve the above problems, present invention also offers the forming method of another metal gates, including：
Semiconductor substrate is provided, the Semiconductor substrate has PMOS area and NMOS area, and the PMOS area is under It is pseudo- formed with second interface layer and second from top to bottom formed with the first boundary layer and the first dummy grid, the NMOS area on Grid, also there is interlayer dielectric layer, the inter-level dielectric layer surface and first dummy grid and institute in the Semiconductor substrate The second dummy grid surface is stated to flush；
Remove first boundary layer and first dummy grid forms first groove, remove the second interface layer and institute State the second dummy grid and form second groove；
The first high-K gate dielectric layer, the first barrier layer and the first packed layer are formed in the first groove, described second The second high-K gate dielectric layer, the second barrier layer and the second packed layer are formed in groove；
First packed layer is removed until re-forming the first groove；
Air storage annealing is carried out to first high-K gate dielectric layer and first barrier layer；
Second packed layer is removed until re-forming the second groove；
Workfunction layers are formed in the bottom and side wall of the first groove and the second groove simultaneously；
The full first groove and the second groove are filled using metal material simultaneously.
Optionally, the air storage annealing is helium annealing or oxygen annealing processing.
Optionally, the temperature range that the helium annealing uses is 500 DEG C~1500 DEG C, the helium gas flow model of use Enclose for 10sccm~1000sccm, the annealing time used is 10s~600s.
Optionally, the temperature range that the oxygen annealing processing uses is 100 DEG C~400 DEG C, the oxygen flow model of use Enclose for 10sccm~1000sccm, the annealing time used is 1s~600s.
Optionally, after the first groove is formed, and before the helium annealing is carried out, the forming method is also Including：Processing is dried.
Compared with prior art, technical scheme has advantages below：
In technical scheme, formed in PMOS area and NMOS area after barrier layer and high-K gate dielectric layer, The barrier layer being pointed in PMOS area and high-K gate dielectric layer carry out air storage annealing, then simultaneously in PMOS area and Workfunction layers are formed in NMOS area, hereafter form metal gates in PMOS area and NMOS area simultaneously.Formed The work functions of workfunction layers meet the requirement of nmos pass transistor.And for the workfunction layers in PMOS area For, it is formed on the barrier layer and high-K gate dielectric layer after being made annealing treatment by air storage, and barrier layer is stored in after annealing It can be diffused into the gas atom in high-K gate dielectric layer inside it, raise its work function, reach the required of PMOS transistor Ask, therefore, the workfunction layers that need to be only formed simultaneously, you can while meet the requirement of PMOS transistor and nmos pass transistor, Technique is simplified, saves process costs.
Further, when air storage annealing is handled for oxygen annealing, the oxygen flow scope used is 10sccm ~1000sccm.In 10sccm~1000sccm range of flows, oxygen flow is bigger, and subsequent storage is on the first barrier layer 212 （And first high-K gate dielectric layer 211）Oxygen atom it is more, be more favorably improved the work function of follow-up workfunction layers, but It is, after flow is more than 1000sccm, to oxygen atom on the first barrier layer 212（And first high-K gate dielectric layer 211）In storage Storage does not influence substantially, and if flow is less than 10sccm, then possibly can not be on the first barrier layer 212（And the first high K grid Dielectric layer 211）Store enough oxygen atoms.
Further, air storage annealing for helium annealing when, the concentrations of helium that uses for 10sccm~ 1000sccm.In 10sccm~1000sccm range of flows, helium gas flow is bigger, and subsequent storage is on the first barrier layer 212（With And first high-K gate dielectric layer 211）Helium atom it is more, be more favorably improved the work function of follow-up workfunction layers, still, After flow is more than 1000sccm, to helium atom on the first barrier layer 212（And first high-K gate dielectric layer 211）In storage Amount does not influence substantially, and if flow is less than 10sccm, then possibly can not be on the first barrier layer 212（And first high K grid be situated between Matter layer 211）Store enough helium atoms.
Brief description of the drawings
Fig. 1 to Fig. 5 is structural representation corresponding to each step of forming method of existing metal gates；
Fig. 6 to Figure 10 is structural representation corresponding to each step of forming method of one embodiment of the invention metal gates；
Figure 11 to Figure 16 is structural representation corresponding to each step of forming method of further embodiment of this invention metal gates.
Embodiment
Because PMOS transistor is different with the threshold voltage of nmos pass transistor, therefore, PMOS transistor and nmos pass transistor Need using the different workfunction layers of work function.The forming method of existing metal gates is formed by different metal material Different workfunction layers, therefore, the forming method of existing metal gates are needed respectively in PMOS transistor and NMOS crystal Pipe individually carries out the formation process of workfunction layers, causes the forming method complex process and process costs of metal gates It is high.
For nmos pass transistor, PMOS transistor needs the larger workfunction layers of work function.Therefore, this hair Bright to provide a kind of forming method of metal gates, the forming method forms barrier layer and height in PMOS area and NMOS area The barrier layer being pointed to after K gate dielectric layers in PMOS area and high-K gate dielectric layer carry out air storage annealing, then simultaneously Workfunction layers are formed in PMOS area and NMOS area, hereafter form metal in PMOS area and NMOS area simultaneously Grid.The work function of the workfunction layers formed meets the requirement of nmos pass transistor.And in PMOS area For workfunction layers, it is formed on the barrier layer and high-K gate dielectric layer after being made annealing treatment by air storage, after annealing The gas atom stayed in barrier layer and high-K gate dielectric layer can be diffused into inside it, raised its work function, reached PMOS crystal The necessary requirement of pipe, therefore, the workfunction layers that need to be only formed simultaneously, you can while meet PMOS transistor and NMOS crystal The requirement of pipe, simplifies technique, saves process costs.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.
The embodiment of the present invention provides a kind of forming method of metal gates, and the forming method of metal gates is divided into many kinds, It is broadly divided into first grid（gate first）And post tensioned unbonded prestressed concrete（gate late）, wherein post tensioned unbonded prestressed concrete is divided into first high K again（high K first）With rear high K（high K last）, the present embodiment provides a kind of forming method of first high-K metal gate, incorporated by reference to reference Fig. 6 to Figure 10.
It refer to Fig. 6, there is provided Semiconductor substrate 200, Semiconductor substrate 200 have PMOS area（Do not mark）And nmos area Domain（Do not mark）.The left-half region of Semiconductor substrate 200 is PMOS area in Fig. 6, and the right half part of Semiconductor substrate 200 is NMOS area.The PMOS area of Semiconductor substrate 200 is from top to bottom formed with the first high-K gate dielectric layer 211, the first barrier layer 212 and first dummy grid 213.The NMOS area of Semiconductor substrate 200 is from top to bottom formed with the second high-K gate dielectric layer 221, Two barrier layers 222 and the second dummy grid 223, also there is interlayer dielectric layer 201, the table of interlayer dielectric layer 201 in Semiconductor substrate 200 Face flushes with the first dummy grid 213 and the surface of the second dummy grid 223.
In the present embodiment, Semiconductor substrate 200 can be silicon substrate or germanium silicon substrate etc. or semiconductor-on-insulator Conductor substrate, the present embodiment is by taking silicon substrate as an example.Semiconductor substrate 200 provides a carrier to form various semiconductor devices.
In the present embodiment, the first high-K gate dielectric layer 211 and the second high-K gate dielectric layer 221 can use same technique simultaneously It is made, and their material can be hafnium oxide, hafnium silicon oxide, lanthana, lanthana aluminium, zirconium oxide, zirconium oxide Silicon, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yittrium oxide, aluminum oxide, lead oxide scandium tantalum or niobic acid The one or more of lead zinc etc..
In the present embodiment, the first barrier layer 212 and the second barrier layer 222 can be made simultaneously using same technique, And their material is specifically as follows at least one of titanium nitride and tantalum nitride.First barrier layer 212 and second stops The metal gates that layer 222 can prevent from ultimately forming spread, so as to prevent metal gates from destroying positioned at high-K gate dielectric layer Dielectric properties.
In the present embodiment, the material of the first dummy grid 213 and the second dummy grid 223 can be polysilicon（poly silicon）, and can be made simultaneously using same technique.
In the present embodiment, the material of interlayer dielectric layer 201 can be silica, can be formed by chemical vapour deposition technique Interlayer dielectric layer 201.It after interlayer dielectric layer 201 is formed, can be planarized, be passed through using chemical mechanical planarization method After planarization, the upper surface of the first dummy grid 213 and the second dummy grid 223 is exposed, so that the surface of interlayer dielectric layer 201 Flushed with the first dummy grid 213 and the surface of the second dummy grid 223.
Fig. 7 is refer to, mask layer 202 is formed on the second dummy grid 223, is mask with mask layer 202, etching removes the One dummy grid 213 forms first groove 214.
In the present embodiment, mask layer 202 can be photoresist layer, amorphous carbon layer or metal compound layer.Work as mask When layer 202 is metal compound layer, it is specifically as follows at least one of titanium nitride and tantalum nitride, titanium nitride and tantalum nitride Property it is stable and good into film uniformity, therefore can be used for substituting conventional photoresist in the present embodiment as mask.
In the present embodiment, the plasma of hydrogen can be used, or uses the hybrid plasma of hydrogen bromide and oxygen, Remove the first dummy grid 213.
In the present embodiment, after first groove 214 is formed, processing can also be dried to first groove 214, so as to The impurity for preventing from remaining during the first dummy grid 213 is removed has undesirable effect to subsequent technique.
Fig. 8 is refer to, air storage annealing is carried out to the first barrier layer 212 and the first high-K gate dielectric layer 211.Specifically, The air storage annealing can be helium annealing or oxygen annealing processing.
Because the material on the first barrier layer 212 is specifically as follows at least one of titanium nitride and tantalum nitride, and nitrogenize Nitrogen-atoms room would generally be formed inside titanium and tantalum nitride because of the missing of some nitrogen-atoms（N-vacancy）.Likewise, the One high-K gate dielectric layer 211 is metal oxide（Such as hafnium oxide）, inside it would generally because of some oxygen atoms missing and Form oxygen atom room（O-vacancy）.These nitrogen-atoms rooms and oxygen atom room can by the oxygen atom in environment or Helium atom is filled（Because the size in room is consistent with atom size）, therefore, when the progress helium annealing or oxygen When gas makes annealing treatment, oxygen atom or helium atom can be packed into corresponding nitrogen-atoms room and oxygen atom room, make the first resistance Rich in oxygen atom or rich in helium atom in the high-K gate dielectric layer 211 of barrier 212 and first（In Fig. 8, first is represented with band twill Rich in oxygen atom or rich in helium atom in the high-K gate dielectric layer 211 of barrier layer 212 and first）, i.e., oxygen atom or helium atom storage In the presence of in the first barrier layer 212 and the first high-K gate dielectric layer 211.Particularly the first barrier layer 212, due to being moved back in the helium The first barrier layer 212 is directly exposed in helium atmosphere or oxygen atmosphere during fire processing, therefore, in the first barrier layer 212 All atom vacancies are substantially by oxygen atom or helium atom institute saturation.By oxygen atom or the first barrier layer of helium atom saturation 212（And first high-K gate dielectric layer 211）Substantial amounts of oxygen atom or helium atom temporarily are stored, subsequently on the first barrier layer 212（And first high-K gate dielectric layer 211）During upper formation workfunction layers, the first barrier layer 212 is stored in（And first High-K gate dielectric layer 211）Oxygen atom or helium atom diffuse into workfunction layers, make the work(of workfunction layers Function improves.
In the present embodiment, when air storage annealing for oxygen annealing processing when, the oxygen flow scope that uses for 10sccm~1000sccm.In 10sccm~1000sccm range of flows, oxygen flow is bigger, and subsequent storage stops first Layer 212（And first high-K gate dielectric layer 211）Oxygen atom it is more, be more favorably improved the work content of follow-up workfunction layers Number, still, after flow is more than 1000sccm, to oxygen atom on the first barrier layer 212（And first high-K gate dielectric layer 211） In storage capacity do not influence substantially, then possibly can not be on the first barrier layer 212 and if flow is less than 10sccm（And the One high-K gate dielectric layer 211）Store enough oxygen atoms.
In the present embodiment, when air storage annealing for oxygen annealing processing when, the temperature range that uses for 500 DEG C~ 1500 DEG C, temperature is too low, and oxygen atom does not have enough energy to enter the first barrier layer 212（And first high-K gate dielectric layer 211） In, temperature is too high, and oxygen atom energy is too big, and oxygen atom may be again from the first barrier layer 212（And first high-K gate dielectric layer 211）Middle effusion.
In the present embodiment, when air storage annealing for oxygen annealing processing when, the annealing time scope that uses can be with For 1s~600s.In 1s~600s time range, annealing time is longer, and subsequent storage is on the first barrier layer 212（And the One high-K gate dielectric layer 211）Oxygen atom it is more, be more favorably improved the work function of follow-up workfunction layers, still, annealing After 600s, to oxygen atom on the first barrier layer 212（And first high-K gate dielectric layer 211）In storage capacity do not have substantially Have an impact, and if annealing time is less than 1s, then possibly can not be on the first barrier layer 212（And first high-K gate dielectric layer 211） Store enough oxygen atoms.
In the present embodiment, when air storage annealing for helium annealing when, the helium gas flow scope that uses for 10sccm~1000sccm.In 10sccm~1000sccm range of flows, helium gas flow is bigger, and subsequent storage stops first Layer 212（And first high-K gate dielectric layer 211）Helium atom it is more, be more favorably improved the work content of follow-up workfunction layers Number, still, after flow is more than 1000sccm, to helium atom on the first barrier layer 212（And first high-K gate dielectric layer 211） In storage capacity do not influence substantially, then possibly can not be on the first barrier layer 212 and if flow is less than 10sccm（And the One high-K gate dielectric layer 211）Store enough helium atoms.
In the present embodiment, when air storage annealing for helium annealing when, the temperature range that uses for 100 DEG C~ 400 DEG C, temperature is too low, and helium atom does not have enough energy to enter the first barrier layer 212（And first high-K gate dielectric layer 211） In, temperature is too high, and helium atom energy is too big, and helium atom may be again from the first barrier layer 212（And first high-K gate dielectric layer 211）Middle effusion.
In the present embodiment, when air storage annealing for helium annealing when, the annealing time scope that uses can be with For 10s~600s.In 10s~600s time range, annealing time is longer, and subsequent storage is on the first barrier layer 212（And First high-K gate dielectric layer 211）Helium atom it is more, be more favorably improved the work function of follow-up workfunction layers, still, move back After fire is more than 600s, to helium atom on the first barrier layer 212（And first high-K gate dielectric layer 211）In storage capacity it is basic Do not influence, and if annealing time is less than 1s, then possibly can not be on the first barrier layer 212（And first high-K gate dielectric layer 211）Store enough helium atoms.
Refer to Fig. 9, carried out it is above-mentioned after, remove Fig. 8 shown in mask layer 202.
In this implementation, when mask layer 202 is metal compound layer, flatening process can be used to remove mask layer 202. And when mask layer 202 is photoresist, cineration technics can be used to remove.
Please continue to refer to Fig. 9, after mask layer 202 is removed, remove the second dummy grid 223 shown in Fig. 8 and form the second ditch Groove 224.
In the present embodiment, wet-etching technology can be used to remove the second dummy grid 223.
Figure 10 is refer to, the first workfunction layers 215 are formed in the bottom of first groove 214 shown in Fig. 9 and side wall, The bottom of second groove 224 shown in Fig. 9 and side wall form the second workfunction layers 225.
In the present embodiment, the first workfunction layers 215 and the second workfunction layers 225 are simultaneously formed, that is, are used Identical material and same process step is formed, specifically, the material can be ramet or tungsten carbide（That is the gold of carbon doping Belong to layer）.
The work function of the script of second workfunction layers 225 is to meet the making demand of nmos pass transistor.And for being formed For the first workfunction layers 215 on the first barrier layer 212, the first barrier layer 212 and the first high-K gate dielectric layer 211 In oxygen atom or nitrogen-atoms can be diffused into inside the first workfunction layers 215, make the work content of the first workfunction layers 215 It is high several litres.Also, according to the regulation and control of above-mentioned annealing temperature, gas flow and annealing time, the first work function can be made The work function value added of metal level 215 is controlled between 10mV~1000mV, and generally nmos pass transistor and PMOS transistor Work function is only 300mV~400mV between workfunction layers, therefore, is made annealing treatment by above-mentioned air storage, it is ensured that The work function of first workfunction layers 215 is adjusted to the making demand for meeting PMOS transistor.
Please continue to refer to Figure 10, first groove 214 and second groove 224 shown in full Fig. 9 are filled simultaneously using metal material, Form the first metal gates 216 and the second metal gates 226.
In the present embodiment, the metal material can be one or a combination set of following metal：Copper, ruthenium, palladium, platinum, cobalt, nickel, Tungsten, aluminium, titanium, tantalum, hafnium and zirconium.
In the forming method for the metal gates that the present embodiment is provided, first to the first barrier layer 212 and the first high-K gate dielectric Layer 211 carries out air storage annealing, them is rich in oxygen atom or helium atom, then forms the first workfunction layers simultaneously 215 and second workfunction layers 225, the work function of the second workfunction layers 225 meet the requirement of nmos pass transistor.It is and right For the first workfunction layers 215, it forms the first barrier layer 212 after being made annealing treatment by air storage and the first high K The gas atom stayed on gate dielectric layer 211, after annealing in the first barrier layer 212 and the first high-K gate dielectric layer 211 can expand It is scattered to inside it, raises its work function, reach the necessary requirement of PMOS transistor, therefore, need to only carries out work function once Metal level formation process, you can while meet the requirement of PMOS transistor and nmos pass transistor, technique is simplified, reduces technique Cost.
Further embodiment of this invention provides the forming method of another metal gates, and the forming method is rear high K The forming method of metal gates, incorporated by reference to reference to figures 11 to Figure 16.
It refer to Figure 11, there is provided Semiconductor substrate 300, Semiconductor substrate 300 have PMOS area（Do not mark）And NMOS Region（Do not mark）.The left-half region of Semiconductor substrate 300 is PMOS area in Figure 11, the right half part of Semiconductor substrate 300 For NMOS area.The PMOS area of Semiconductor substrate 300 is from top to bottom formed with the first boundary layer 311 and the first dummy grid 312. The NMOS area of Semiconductor substrate 300 is from top to bottom formed with the dummy grid 322 of second interface layer 321 and second, Semiconductor substrate Also there is interlayer dielectric layer 301, the surface of interlayer dielectric layer 301 and the first dummy grid 312 and the surface of the second dummy grid 322 on 300 Flush.
In the present embodiment, Semiconductor substrate 300 can be silicon substrate or germanium silicon substrate etc. or semiconductor-on-insulator Conductor substrate, the present embodiment is by taking silicon substrate as an example.Semiconductor substrate 300 provides a carrier to form various semiconductor devices.
In the present embodiment, the first boundary layer 311 and second interface layer 321 can be made simultaneously using same technique, And their material can be silica.
In the present embodiment, the material of the first dummy grid 312 and the second dummy grid 322 can be polysilicon, and can adopt It is made simultaneously with same technique.
In the present embodiment, the material of interlayer dielectric layer 301 can be silica, can be formed by chemical vapour deposition technique Interlayer dielectric layer 301.It after interlayer dielectric layer 301 is formed, can be planarized, be passed through using chemical mechanical planarization method After planarization, the upper surface of the first dummy grid 312 and the second dummy grid 322 is exposed, so that the surface of interlayer dielectric layer 301 Flushed with the first dummy grid 312 and the surface of the second dummy grid 322.
Figure 12 is refer to, the first dummy grid 312 shown in Figure 11 is removed and forms first groove 313, remove second shown in Figure 11 Dummy grid 322 forms second groove 323.
In the present embodiment, the plasma of hydrogen can be used, or using hydrogen bromide（HBr）With the mixing of oxygen etc. from Daughter, remove the first dummy grid 312 and the second dummy grid 322.
Figure 13 is refer to, the first high-K gate dielectric layer 314, the first barrier layer are formed in first groove 313 shown in Figure 12 315 and first packed layer 316, the second high-K gate dielectric layer 324, the second barrier layer are formed in second groove 323 shown in Figure 12 325 and second packed layer 326.
In the present embodiment, the first high-K gate dielectric layer 314 and the second high-K gate dielectric layer 324 can use same technique simultaneously It is made, and their material can be hafnium oxide, hafnium silicon oxide, lanthana, lanthana aluminium, zirconium oxide, zirconium oxide Silicon, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yittrium oxide, aluminum oxide, lead oxide scandium tantalum or niobic acid The one or more of lead zinc etc..
In the present embodiment, the first barrier layer 315 and the second barrier layer 325 can be made simultaneously using same technique, And their material is specifically as follows at least one of titanium nitride and tantalum nitride.First barrier layer 315 and second stops The metal gates that layer 325 can prevent from ultimately forming spread, so as to prevent metal gates from destroying positioned at high-K gate dielectric layer Dielectric properties.
In the present embodiment, the material of the first packed layer 316 and the second packed layer 326 is specifically as follows using spin coating proceeding shape Into silicon oxide layer.
Figure 14 is refer to, mask layer 302 is formed on the second dummy grid 322, is mask with mask layer 302, etching removes The first packed layer 316 is until re-form first groove 314 shown in Figure 13.
In the present embodiment, mask layer 302 can be photoresist layer, amorphous carbon layer or metal compound layer.Work as mask When layer 302 is metal compound layer, it is specifically as follows at least one of titanium nitride and tantalum nitride, titanium nitride and tantalum nitride Property it is stable and good into film uniformity, therefore can be used for substituting conventional photoresist in the present embodiment as mask.
In the present embodiment, when the first packed layer 316 is the silicon oxide layer formed using spin coating proceeding, hydrogen-oxygen can be used Change alkyl ammonium salt solution and remove the first packed layer 316.
In the present embodiment, after first groove 314 is formed, processing can also be dried to first groove 314, so as to The impurity for preventing from remaining during the first dummy grid 312 is removed has undesirable effect to subsequent technique.
Figure 15 is refer to, air storage annealing is carried out to the first high-K gate dielectric layer 314 and the first barrier layer 315.Specifically , the air storage annealing can be helium annealing or oxygen annealing processing.
Because the material on the first barrier layer 315 is specifically as follows at least one of titanium nitride and tantalum nitride, and nitrogenize Nitrogen-atoms room would generally be formed inside titanium and tantalum nitride because of the missing of some nitrogen-atoms（N-vacancy）.Likewise, the One high-K gate dielectric layer 314 is metal oxide（Such as hafnium oxide）, inside it would generally because of some oxygen atoms missing and Form oxygen atom room（O-vacancy）.These nitrogen-atoms rooms and oxygen atom room can by the oxygen atom in environment or Helium atom is filled（Because the size in room is consistent with atom size）, therefore, when the progress helium annealing or oxygen When gas makes annealing treatment, oxygen atom or helium atom can be packed into corresponding nitrogen-atoms room and oxygen atom room, make the first resistance Rich in oxygen atom or rich in helium atom in the high-K gate dielectric layer 314 of barrier 315 and first（In Figure 14, first is represented with band twill Rich in oxygen atom or rich in helium atom in the high-K gate dielectric layer 314 of barrier layer 315 and first）.Particularly the first barrier layer 315, Because when the helium makes annealing treatment, the first barrier layer 315 is directly exposed in helium atmosphere or oxygen atmosphere, therefore, the All atom vacancies in one barrier layer 315 are substantially by oxygen atom or helium atom institute saturation.Satisfied by oxygen atom or helium atom First barrier layer 315 of sum（And first high-K gate dielectric layer 314）Temporarily substantial amounts of oxygen atom or helium atom are stored.Afterwards Continue on the first barrier layer 315（And first high-K gate dielectric layer 314）During upper formation workfunction layers, the first stop is stored in Layer 315（And first high-K gate dielectric layer 314）Oxygen atom or helium atom diffuse into workfunction layers, make work( The work function of function metal improves.
In the present embodiment, when air storage annealing for oxygen annealing processing when, the oxygen flow scope that uses for 10sccm~1000sccm.In 10sccm~1000sccm range of flows, oxygen flow is bigger, and subsequent storage stops first Layer 315（And first high-K gate dielectric layer 314）Oxygen atom it is more, be more favorably improved the work content of follow-up workfunction layers Number, still, after flow is more than 1000sccm, to oxygen atom on the first barrier layer 315（And first high-K gate dielectric layer 314） In storage capacity do not influence substantially, then possibly can not be on the first barrier layer 315 and if flow is less than 10sccm（And the One high-K gate dielectric layer 314）Store enough oxygen atoms.
In the present embodiment, when air storage annealing for oxygen annealing processing when, the temperature range that uses for 500 DEG C~ 1500 DEG C, temperature is too low, and oxygen atom does not have enough energy to enter the first barrier layer 315（And first high-K gate dielectric layer 314） In, temperature is too high, and oxygen atom energy is too big, and oxygen atom may be again from the first barrier layer 315（And first high-K gate dielectric layer 314）Middle effusion.
In the present embodiment, when air storage annealing for oxygen annealing processing when, the annealing time scope that uses can be with For 1s~600s.In 1s~600s time range, annealing time is longer, and subsequent storage is on the first barrier layer 315（And the One high-K gate dielectric layer 314）Oxygen atom it is more, be more favorably improved the work function of follow-up workfunction layers, still, annealing After 600s, to oxygen atom on the first barrier layer 315（And first high-K gate dielectric layer 314）In storage capacity do not have substantially Have an impact, and if annealing time is less than 1s, then possibly can not be on the first barrier layer 315（And first high-K gate dielectric layer 314） Store enough oxygen atoms.
In the present embodiment, when air storage annealing for helium annealing when, the helium gas flow scope that uses for 10sccm~1000sccm.In 10sccm~1000sccm range of flows, helium gas flow is bigger, and subsequent storage stops first Layer 315（And first high-K gate dielectric layer 314）Helium atom it is more, be more favorably improved the work content of follow-up workfunction layers Number, still, after flow is more than 1000sccm, to helium atom on the first barrier layer 315（And first high-K gate dielectric layer 314） In storage capacity do not influence substantially, then possibly can not be on the first barrier layer 315 and if flow is less than 10sccm（And the One high-K gate dielectric layer 314）Store enough helium atoms.
In the present embodiment, when air storage annealing for helium annealing when, the temperature range that uses for 100 DEG C~ 400 DEG C, temperature is too low, and helium atom does not have enough energy to enter the first barrier layer 315（And first high-K gate dielectric layer 314） In, temperature is too high, and helium atom energy is too big, and helium atom may be again from the first barrier layer 315（And first high-K gate dielectric layer 314）Middle effusion.
In the present embodiment, when air storage annealing for helium annealing when, the annealing time scope that uses can be with For 10s~600s.In 10s~600s time range, annealing time is longer, and subsequent storage is on the first barrier layer 315（And First high-K gate dielectric layer 314）Helium atom it is more, be more favorably improved the work function of follow-up workfunction layers, still, move back After fire is more than 600s, to helium atom on the first barrier layer 315（And first high-K gate dielectric layer 314）In storage capacity it is basic Do not influence, and if annealing time is less than 1s, then possibly can not be on the first barrier layer 315（And first high-K gate dielectric layer 314）Store enough helium atoms.
Please continue to refer to Figure 15, mask layer 302 shown in Figure 14 is removed.
In this implementation, when mask layer 302 is metal compound layer, flatening process can be used to remove mask layer 302. And when mask layer 302 is photoresist, cineration technics can be used to remove.
Please continue to refer to Figure 15, the second packed layer 326 shown in Figure 14 is removed.
Figure 16 is refer to, the first workfunction layers 317 are formed in the bottom of first groove 313 shown in Figure 15 and side wall, The second workfunction layers 327 are formed in the bottom of second groove 323 and side wall.
In the present embodiment, the first workfunction layers 317 and the second workfunction layers 327 are simultaneously formed, that is, are used Identical material and same process step is formed, specifically, the material can be ramet or tungsten carbide（That is the gold of carbon doping Belong to layer）.
The work function of the script of second workfunction layers 327 is to meet the making demand of nmos pass transistor.And for being formed For the first workfunction layers 317 on the first barrier layer 315, the first barrier layer 315 and the first high-K gate dielectric layer 314 Oxygen atom or nitrogen-atoms can be diffused into inside the first workfunction layers 317, make the work function of the first workfunction layers 317 Rise.Also, according to the regulation and control of above-mentioned annealing temperature, gas flow and annealing time, the first work function can be made golden The work function value added for belonging to layer 317 is controlled between 10mV~1000mV, and generally nmos pass transistor and the work(of PMOS transistor Work function is only 300mV~400mV between function metal, therefore, is made annealing treatment by above-mentioned air storage, it is ensured that the The work function of one workfunction layers 317 is adjusted to the making demand for meeting PMOS transistor.
Please continue to refer to Figure 16, first groove 313 and second groove shown in full Figure 15 are filled simultaneously using metal material 323, form the first metal gates 318 and the second metal gates 328.
In the present embodiment, the metal material can be one or a combination set of following metal：Copper, ruthenium, palladium, platinum, cobalt, nickel, Tungsten, aluminium, titanium, tantalum, hafnium and zirconium.
In the forming method for the metal gates that the present embodiment is provided, first to the first barrier layer 315 and the first high-K gate dielectric Layer 314 carries out air storage annealing, them is rich in oxygen atom or helium atom, then forms the first workfunction layers simultaneously 317 and second workfunction layers 327, the work function of the second workfunction layers 327 meet the requirement of nmos pass transistor.It is and right For the first workfunction layers 317, it forms the first barrier layer 315 after being made annealing treatment by air storage and the first high K The gas atom meeting stayed on gate dielectric layer 314, after annealing in the first barrier layer 3153 and the first high-K gate dielectric layer 314 It is diffused into inside it, raises its work function, reach the necessary requirement of PMOS transistor, therefore, need to only carries out work content once Number metal level formation process, you can while meet the requirement of PMOS transistor and nmos pass transistor, technique is simplified, saves work Skill cost.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute The scope of restriction is defined.

Claims (10)

  1. A kind of 1. forming method of metal gates, it is characterised in that including：
    Semiconductor substrate is provided, the Semiconductor substrate has PMOS area and NMOS area, and the PMOS area is from top to bottom It is high formed with second from top to bottom formed with the first high-K gate dielectric layer, the first barrier layer and the first dummy grid, the NMOS area K gate dielectric layers, the second barrier layer and the second dummy grid, also have interlayer dielectric layer in the Semiconductor substrate, and the interlayer is situated between Matter layer surface flushes with first dummy grid and the second dummy grid surface；
    Remove first dummy grid and form first groove；
    Air storage annealing is carried out to first barrier layer and first high-K gate dielectric layer；
    Remove second dummy grid and form second groove；
    Workfunction layers are formed in the bottom and side wall of the first groove and the second groove simultaneously；
    The full first groove and the second groove are filled using metal material simultaneously.
  2. 2. the forming method of metal gates as claimed in claim 1, it is characterised in that the air storage annealing is moved back for helium Fire processing or oxygen annealing processing.
  3. 3. the forming method of metal gates as claimed in claim 2, it is characterised in that the temperature that the oxygen annealing processing uses It is 100 DEG C~400 DEG C to spend scope, and the oxygen flow scope used is 10sccm~1000sccm, and the annealing time used is 1s ~600s.
  4. 4. the forming method of metal gates as claimed in claim 2, it is characterised in that the temperature that the helium annealing uses It is 500 DEG C~1500 DEG C to spend scope, the helium gas flow scope used for 10sccm~1000sccm, the annealing time that uses for 10s~600s.
  5. 5. the forming method of metal gates as claimed in claim 2, it is characterised in that after the first groove is formed, and Before the helium annealing is carried out, the forming method also includes：Processing is dried.
  6. A kind of 6. forming method of metal gates, it is characterised in that including：
    Semiconductor substrate is provided, the Semiconductor substrate has PMOS area and NMOS area, and the PMOS area is from top to bottom Formed with the first boundary layer and the first dummy grid, the NMOS area is from top to bottom formed with second interface layer and the second pseudo- grid Pole, also has interlayer dielectric layer in the Semiconductor substrate, the inter-level dielectric layer surface and first dummy grid and described Second dummy grid surface flushes；
    Remove first boundary layer and first dummy grid and form first groove, remove the second interface layer and described the Two dummy grids form second groove；
    The first high-K gate dielectric layer, the first barrier layer and the first packed layer are formed in the first groove, in the second groove The second high-K gate dielectric layer of interior formation, the second barrier layer and the second packed layer；
    First packed layer is removed until re-forming the first groove；
    Air storage annealing is carried out to first high-K gate dielectric layer and first barrier layer；
    Second packed layer is removed until re-forming the second groove；
    Workfunction layers are formed in the bottom and side wall of the first groove and the second groove simultaneously；
    The full first groove and the second groove are filled using metal material simultaneously.
  7. 7. the forming method of metal gates as claimed in claim 6, it is characterised in that the air storage annealing is moved back for helium Fire processing or oxygen annealing processing.
  8. 8. the forming method of metal gates as claimed in claim 7, it is characterised in that the temperature that the oxygen annealing processing uses It is 100 DEG C~400 DEG C to spend scope, and the oxygen flow scope used is 10sccm~1000sccm, and the annealing time used is 1s ~600s.
  9. 9. the forming method of metal gates as claimed in claim 7, it is characterised in that the temperature that the helium annealing uses It is 500 DEG C~1500 DEG C to spend scope, the helium gas flow scope used for 10sccm~1000sccm, the annealing time that uses for 10s~600s.
  10. 10. the forming method of metal gates as claimed in claim 7, it is characterised in that after the first groove is formed, and Before the helium annealing is carried out, the forming method also includes：Processing is dried.
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CN102214609A (en) * 2010-04-07 2011-10-12 中国科学院微电子研究所 Semiconductor device and manufacturing method thereof

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US7229873B2 (en) * 2005-08-10 2007-06-12 Texas Instruments Incorporated Process for manufacturing dual work function metal gates in a microelectronics device
US9024299B2 (en) * 2008-10-14 2015-05-05 Imec Method for fabricating a dual work function semiconductor device and the device made thereof
US8643113B2 (en) * 2008-11-21 2014-02-04 Texas Instruments Incorporated Structure and method for metal gate stack oxygen concentration control using an oxygen diffusion barrier layer and a sacrificial oxygen gettering layer
US8536654B2 (en) * 2010-01-13 2013-09-17 Texas Instruments Incorporated Structure and method for dual work function metal gate CMOS with selective capping
US8580630B2 (en) * 2011-10-21 2013-11-12 Applied Materials, Inc. Methods for forming a metal gate structure on a substrate
KR101929384B1 (en) * 2012-05-24 2018-12-14 삼성전자주식회사 Method for manufacturing semiconductor device having selectively nitrided gate dielectric layer

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CN102214609A (en) * 2010-04-07 2011-10-12 中国科学院微电子研究所 Semiconductor device and manufacturing method thereof

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