CN104752176A - Method for forming metal gate - Google Patents
Method for forming metal gate Download PDFInfo
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- CN104752176A CN104752176A CN201310739022.5A CN201310739022A CN104752176A CN 104752176 A CN104752176 A CN 104752176A CN 201310739022 A CN201310739022 A CN 201310739022A CN 104752176 A CN104752176 A CN 104752176A
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- 238000000034 method Methods 0.000 title claims abstract description 163
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 52
- 239000002184 metal Substances 0.000 title claims abstract description 52
- 239000010410 layer Substances 0.000 claims abstract description 353
- 238000000137 annealing Methods 0.000 claims abstract description 113
- 230000004888 barrier function Effects 0.000 claims abstract description 106
- 230000008569 process Effects 0.000 claims abstract description 102
- 239000004065 semiconductor Substances 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 239000011229 interlayer Substances 0.000 claims abstract description 23
- 239000007769 metal material Substances 0.000 claims abstract description 13
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 77
- 229910052734 helium Inorganic materials 0.000 claims description 72
- 238000003860 storage Methods 0.000 claims description 56
- 230000015572 biosynthetic process Effects 0.000 claims description 49
- 239000001307 helium Substances 0.000 claims description 37
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 33
- 239000001301 oxygen Substances 0.000 claims description 33
- 229910052760 oxygen Inorganic materials 0.000 claims description 33
- 239000007789 gas Substances 0.000 claims description 15
- 238000001035 drying Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 125000004430 oxygen atom Chemical group O* 0.000 description 50
- 239000000463 material Substances 0.000 description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 10
- 125000004433 nitrogen atom Chemical group N* 0.000 description 10
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 10
- 125000004429 atom Chemical group 0.000 description 8
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 8
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 150000002736 metal compounds Chemical class 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910044991 metal oxide Inorganic materials 0.000 description 5
- 150000004706 metal oxides Chemical class 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000004567 concrete Substances 0.000 description 4
- 230000008034 disappearance Effects 0.000 description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 229920006395 saturated elastomer Polymers 0.000 description 4
- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Chemical compound [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- -1 yittrium oxide Chemical compound 0.000 description 4
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 2
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 2
- WUNIMIODOAGQAW-UHFFFAOYSA-N [O-2].[Ba+2].[Ti+4] Chemical compound [O-2].[Ba+2].[Ti+4] WUNIMIODOAGQAW-UHFFFAOYSA-N 0.000 description 2
- PXNDALNSUJQINT-UHFFFAOYSA-N [Sc].[Ta] Chemical compound [Sc].[Ta] PXNDALNSUJQINT-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 230000009931 harmful effect Effects 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910000464 lead oxide Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- YEXPOXQUZXUXJW-UHFFFAOYSA-N oxolead Chemical compound [Pb]=O YEXPOXQUZXUXJW-UHFFFAOYSA-N 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 239000011513 prestressed concrete Substances 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- UONOETXJSWQNOL-UHFFFAOYSA-N tungsten carbide Chemical compound [W+]#[C-] UONOETXJSWQNOL-UHFFFAOYSA-N 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 2
- 125000005210 alkyl ammonium group Chemical group 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
Abstract
A method for forming a metal gate comprises the following steps: providing a semiconductor substrate which has a PMOS region and an NMOS region, wherein a first high-K gate dielectric layer, a first barrier layer and a first dummy gate are formed in the PMOS region from bottom to top, a second high-K gate dielectric layer, a second barrier layer and a second dummy gate are formed in the NMOS region from bottom to top, and the semiconductor substrate further has an interlayer dielectric layer; removing the first dummy gate to form a first trench; performing gas annealing on the first barrier layer and the first high-K gate dielectric layer; removing the second dummy gate to form a second trench; forming work function metal layers on the bottoms and side walls of the first trench and the second trench; and filling the first trench and the second trench with metal material. By adopting the method, the manufacturing process is simplified, and the process cost is reduced.
Description
Technical field
The present invention relates to field of semiconductor manufacture, especially relate to a kind of formation method of metal gates.
Background technology
The main devices of integrated circuit especially in very lagre scale integrated circuit (VLSIC) is metal-oxide semiconductor fieldeffect transistor (metal oxide semiconductor field effect transistor is called for short MOS transistor).Since metal-oxide-semiconductor is invented, its physical dimension is constantly reducing always.In the case, various restriction and technological challenge start to occur, reducing further of device size just becomes more and more difficult.Along with combined metal oxide semiconductor's structure (CMOS, ComplementaryMetal-Oxide-Semiconductor) manufacturing process tapers to below 32nm rank, introduce the technology adopting new design and material.In MOS transistor device and circuit preparation, most is challenging is the higher grid Leakage Current that grid structural thickness that conventional CMOS device is formed by polysilicon and silica (or silicon oxynitride) in the process reduced reduces to bring.For this reason, the solution proposed is, adopts metal gate and high-k (K) gate medium to substitute traditional heavily doped polysilicon grid and silica (or silicon oxynitride) gate medium.
The formation method of existing metal gates as shown in Figures 1 to 5.
Please refer to Fig. 1, provide Semiconductor substrate 100, Semiconductor substrate 100 has PMOS area and NMOS area, and in Fig. 1, Semiconductor substrate 100 left-half region is PMOS area, and Semiconductor substrate 100 right half part is NMOS area.PMOS area is formed the first high-K gate dielectric layer 111, first barrier layer 112 and the first dummy grid 113, form the second high-K gate dielectric layer 121, second barrier layer 122 and the second dummy grid 123 on an nmos area, and form interlayer dielectric layer 101 and cover Semiconductor substrate 100, surface and first dummy grid 113 of interlayer dielectric layer 101 flush with the surface of the second dummy grid 123.
Please refer to Fig. 2, form mask layer 102 and protect the second dummy grid 123, and with mask layer 102 for mask, the first dummy grid 113 shown in Fig. 1 is removed in etching, forms the first groove 114.
Please refer to Fig. 3, shown in Fig. 2, the bottom of the first groove 114 and sidewall form the first workfunction layers 115, fill the first groove 114 shown in full Fig. 2 until form the first metal gates 116 more afterwards with metal material.
Please refer to Fig. 4, remove mask layer 102 and the second dummy grid 123 shown in Fig. 3, form the second groove 124.
Please refer to Fig. 5, shown in Fig. 4, the bottom of the second groove 124 and sidewall form the second workfunction layers 125, fill the second groove 124 shown in full Fig. 4 until form the second metal gates 126 more afterwards with metal material.
As seen from the above description, the formation method of existing metal gates needs to form different workfunction layers respectively with different metal materials, therefore, its complex manufacturing technology, and process costs is high.
For this reason, need a kind of formation method of new metal gates, to prevent from overcoming existing method complex manufacturing technology and the high problem of process costs.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of metal gates, to simplify manufacture craft, and reduces process costs.
For solving the problem, the invention provides a kind of formation method of metal gates, comprising:
Semiconductor substrate is provided, described Semiconductor substrate has PMOS area and NMOS area, described PMOS area is formed with the first high-K gate dielectric layer, the first barrier layer and the first dummy grid from top to bottom, described NMOS area is formed with the second high-K gate dielectric layer, the second barrier layer and the second dummy grid from top to bottom, described Semiconductor substrate also has interlayer dielectric layer, and described interlayer dielectric layer surface flushes with described first dummy grid and described second dummy grid surface;
Remove described first dummy grid and form the first groove;
Air storage annealing in process is carried out to described first barrier layer and described first high-K gate dielectric layer;
Remove described second dummy grid and form the second groove;
Form workfunction layers in the bottom of described first groove and described second groove and sidewall simultaneously;
Adopt metal material to fill completely described first groove and described second groove simultaneously.
Optionally, described air storage annealing in process is helium annealing in process or oxygen annealing process.
Optionally, the temperature range that described helium annealing in process adopts is 500 DEG C ~ 1500 DEG C, and the helium gas flow scope of employing is 10sccm ~ 1000sccm, and the annealing time of employing is 10s ~ 600s.
Optionally, the temperature range that described oxygen annealing process adopts is 100 DEG C ~ 400 DEG C, and the oxygen flow scope of employing is 10sccm ~ 1000sccm, and the annealing time of employing is 1s ~ 600s.
Optionally, after described first groove of formation, and before carrying out described helium annealing in process, described formation method also comprises: carry out drying process.
For solving the problem, present invention also offers the formation method of another metal gates, comprising:
Semiconductor substrate is provided, described Semiconductor substrate has PMOS area and NMOS area, described PMOS area is formed with the first boundary layer and the first dummy grid from top to bottom, described NMOS area is formed with second interface layer and the second dummy grid from top to bottom, described Semiconductor substrate also has interlayer dielectric layer, and described interlayer dielectric layer surface flushes with described first dummy grid and described second dummy grid surface;
Remove described first boundary layer and described first dummy grid forms the first groove, remove described second interface layer and described second dummy grid forms the second groove;
In described first groove, form the first high-K gate dielectric layer, the first barrier layer and the first packed layer, in described second groove, form the second high-K gate dielectric layer, the second barrier layer and the second packed layer;
Remove described first packed layer until again form described first groove;
Air storage annealing in process is carried out to described first high-K gate dielectric layer and described first barrier layer;
Remove described second packed layer until again form described second groove;
Form workfunction layers in the bottom of described first groove and described second groove and sidewall simultaneously;
Adopt metal material to fill completely described first groove and described second groove simultaneously.
Optionally, described air storage annealing in process is helium annealing in process or oxygen annealing process.
Optionally, the temperature range that described helium annealing in process adopts is 500 DEG C ~ 1500 DEG C, and the helium gas flow scope of employing is 10sccm ~ 1000sccm, and the annealing time of employing is 10s ~ 600s.
Optionally, the temperature range that described oxygen annealing process adopts is 100 DEG C ~ 400 DEG C, and the oxygen flow scope of employing is 10sccm ~ 1000sccm, and the annealing time of employing is 1s ~ 600s.
Optionally, after described first groove of formation, and before carrying out described helium annealing in process, described formation method also comprises: carry out drying process.
Compared with prior art, technical scheme of the present invention has the following advantages:
In technical scheme of the present invention, after PMOS area and NMOS area are formed barrier layer and high-K gate dielectric layer, air storage annealing in process is carried out to the barrier layer be positioned in PMOS area and high-K gate dielectric layer, then in PMOS area and NMOS area, form workfunction layers simultaneously, after this in PMOS area and NMOS area, form metal gates simultaneously.The work function of the workfunction layers formed meets the requirement of nmos pass transistor.And for the workfunction layers be positioned in PMOS area, it is formed on the barrier layer after air storage annealing in process and high-K gate dielectric layer, the gas atom be stored in after annealing in process in barrier layer and high-K gate dielectric layer can be diffused into its inside, its work function is raised, reaches the necessary requirement of PMOS transistor, therefore, the workfunction layers that only need simultaneously be formed, the requirement of PMOS transistor and nmos pass transistor can be met simultaneously, simplify technique, save process costs.
Further, when described air storage annealing in process is oxygen annealing process, the oxygen flow scope of employing is 10sccm ~ 1000sccm.In 10sccm ~ 1000sccm range of flow, oxygen flow is larger, subsequent storage is at the first barrier layer 212(and the first high-K gate dielectric layer 211) oxygen atom more, more contribute to the work function improving follow-up workfunction layers, but, after flowing exceed 1000sccm, on oxygen atom at the first barrier layer 212(and the first high-K gate dielectric layer 211) in storage capacity substantially do not affect, if and flow is less than 10sccm, then possibly cannot at the first barrier layer 212(and the first high-K gate dielectric layer 211) store enough oxygen atoms.
Further, when described air storage annealing in process is helium annealing in process, the concentrations of helium of employing is 10sccm ~ 1000sccm.In 10sccm ~ 1000sccm range of flow, helium gas flow is larger, subsequent storage is at the first barrier layer 212(and the first high-K gate dielectric layer 211) helium atom more, more contribute to the work function improving follow-up workfunction layers, but, after flowing exceed 1000sccm, on helium atom at the first barrier layer 212(and the first high-K gate dielectric layer 211) in storage capacity substantially do not affect, if and flow is less than 10sccm, then possibly cannot at the first barrier layer 212(and the first high-K gate dielectric layer 211) store enough helium atoms.
Accompanying drawing explanation
Fig. 1 to Fig. 5 is structural representation corresponding to each step of formation method of existing metal gates;
Fig. 6 to Figure 10 is structural representation corresponding to each step of formation method of one embodiment of the invention metal gates;
Figure 11 to Figure 16 is structural representation corresponding to each step of formation method of further embodiment of this invention metal gates.
Embodiment
Because PMOS transistor is different with the threshold voltage of nmos pass transistor, therefore, PMOS transistor and nmos pass transistor need the workfunction layers that employing work function is different.The formation method of existing metal gates forms different workfunction layers by different metal material, therefore, the formation method of existing metal gates needs the formation process of carrying out workfunction layers respectively in PMOS transistor and nmos pass transistor individually, causes the formation method complex process of metal gates and process costs is high.
Compared to nmos pass transistor, the workfunction layers that PMOS transistor needs work function larger.For this reason, the invention provides a kind of formation method of metal gates, after described formation method forms barrier layer and high-K gate dielectric layer in PMOS area and NMOS area, air storage annealing in process is carried out to the barrier layer be positioned in PMOS area and high-K gate dielectric layer, then in PMOS area and NMOS area, form workfunction layers simultaneously, after this in PMOS area and NMOS area, form metal gates simultaneously.The work function of the workfunction layers formed meets the requirement of nmos pass transistor.And for the workfunction layers be positioned in PMOS area, it is formed on the barrier layer after air storage annealing in process and high-K gate dielectric layer, the gas atom stayed after annealing in process in barrier layer and high-K gate dielectric layer can be diffused into its inside, its work function is raised, reaches the necessary requirement of PMOS transistor, therefore, the workfunction layers that only need simultaneously be formed, the requirement of PMOS transistor and nmos pass transistor can be met simultaneously, simplify technique, save process costs.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
The embodiment of the present invention provides a kind of formation method of metal gates, the formation method of metal gates is divided into a variety of, mainly be divided into first grid (gate first) and post tensioned unbonded prestressed concrete (gate late), wherein post tensioned unbonded prestressed concrete is divided into again first high K(high K first) and rear high K(high K last), the present embodiment provides a kind of formation method of first high-K metal gate, incorporated by reference to reference to figure 6 to Figure 10.
Please refer to Fig. 6, provide Semiconductor substrate 200, Semiconductor substrate 200 has PMOS area (mark) and NMOS area (mark).In Fig. 6, Semiconductor substrate 200 left-half region is PMOS area, and Semiconductor substrate 200 right half part is NMOS area.The PMOS area of Semiconductor substrate 200 is formed with the first high-K gate dielectric layer 211, first barrier layer 212 and the first dummy grid 213 from top to bottom.The NMOS area of Semiconductor substrate 200 is formed with the second high-K gate dielectric layer 221, second barrier layer 222 and the second dummy grid 223 from top to bottom, Semiconductor substrate 200 also has interlayer dielectric layer 201, and interlayer dielectric layer 201 surface flushes with the first dummy grid 213 and the second dummy grid 223 surface.
In the present embodiment, Semiconductor substrate 200 can be silicon substrate or germanium silicon substrate etc., and also can be semiconductor-on-insulator substrate, the present embodiment be for silicon substrate.Semiconductor substrate 200 provides a carrier for forming various semiconductor device.
In the present embodiment, first high-K gate dielectric layer 211 and the second high-K gate dielectric layer 221 can adopt same technique to be made simultaneously, and their material can be hafnium oxide, hafnium silicon oxide, lanthana, lanthana aluminium, zirconia, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yittrium oxide, aluminium oxide, lead oxide scandium tantalum or lead niobate zinc etc. one or more.
In the present embodiment, the first barrier layer 212 and the second barrier layer 222 can adopt same technique to be made simultaneously, and their material be specifically as follows titanium nitride and tantalum nitride at least one of them.First barrier layer 212 and the second barrier layer 222 can prevent the final metal gates formed from spreading, thus prevent metal gates from destroying the dielectric property being positioned at high-K gate dielectric layer.
In the present embodiment, the material of the first dummy grid 213 and the second dummy grid 223 can be polysilicon (polysilicon), and same technique can be adopted to be made simultaneously.
In the present embodiment, the material of interlayer dielectric layer 201 can be silicon dioxide, forms interlayer dielectric layer 201 by chemical vapour deposition technique.After formation interlayer dielectric layer 201, chemical mechanical planarization method can be adopted to carry out planarization, after planarization, the upper surface of the first dummy grid 213 and the second dummy grid 223 comes out, thus interlayer dielectric layer 201 surface is flushed with the first dummy grid 213 and the second dummy grid 223 surface.
Please refer to Fig. 7, the second dummy grid 223 forms mask layer 202, with mask layer 202 for mask, etching removal first dummy grid 213 forms the first groove 214.
In the present embodiment, mask layer 202 can be photoresist layer, amorphous carbon layer or metal compound layer.When mask layer 202 is metal compound layer, its be specifically as follows titanium nitride and tantalum nitride at least one of them, the stable in properties of titanium nitride and tantalum nitride, and become film uniformity good, therefore can be used for substituting conventional photoresist as mask in the present embodiment.
In the present embodiment, the plasma of hydrogen can be adopted, or adopt the hybrid plasma of hydrogen bromide and oxygen, remove the first dummy grid 213.
In the present embodiment, after formation first groove 214, drying process can also be carried out to the first groove 214, thus prevent impurity residual in the process of removal first dummy grid 213 from causing harmful effect to subsequent technique.
Please refer to Fig. 8, air storage annealing in process is carried out to the first barrier layer 212 and the first high-K gate dielectric layer 211.Concrete, described air storage annealing in process can be helium annealing in process or oxygen annealing process.
Material due to the first barrier layer 212 be specifically as follows titanium nitride and tantalum nitride at least one of them, and titanium nitride and tantalum nitride is inner usually can form nitrogen-atoms room (N-vacancy) because of the disappearance of some nitrogen-atoms.Same, the first high-K gate dielectric layer 211 is metal oxide (such as hafnium oxide), and its inner meeting usually form oxygen atom room (O-vacancy) because of the disappearance of some oxygen atom.These nitrogen-atoms rooms and oxygen atom room can by the oxygen atom in environment or helium atom fill (because the size in room conforms to atom size), therefore, when carrying out described helium annealing in process or oxygen annealing process, oxygen atom or helium atom can be packed in corresponding nitrogen-atoms room and oxygen atom room, make to be rich in oxygen atom or to be rich in helium atom (in Fig. 8 in the first barrier layer 212 and the first high-K gate dielectric layer 211, represent in the first barrier layer 212 and the first high-K gate dielectric layer 211 with band twill and be rich in oxygen atom or be rich in helium atom), namely oxygen atom or helium atom are stored in the first barrier layer 212 and the first high-K gate dielectric layer 211.Particularly the first barrier layer 212, because when described helium annealing in process, the first barrier layer 212 is directly exposed in helium atmosphere or oxygen atmosphere, therefore, all atom vacancies in the first barrier layer 212 substantially by oxygen atom or helium atom institute saturated.By oxygen atom or saturated the first barrier layer 212(of helium atom and the first high-K gate dielectric layer 211) temporarily store a large amount of oxygen atoms or helium atom, follow-up at the first barrier layer 212(and the first high-K gate dielectric layer 211) upper when forming workfunction layers, be stored in the first barrier layer 212(and the first high-K gate dielectric layer 211) oxygen atom or helium atom will be diffused in workfunction layers, the work function of workfunction layers is improved.
In the present embodiment, when described air storage annealing in process is oxygen annealing process, the oxygen flow scope of employing is 10sccm ~ 1000sccm.In 10sccm ~ 1000sccm range of flow, oxygen flow is larger, subsequent storage is at the first barrier layer 212(and the first high-K gate dielectric layer 211) oxygen atom more, more contribute to the work function improving follow-up workfunction layers, but, after flowing exceed 1000sccm, on oxygen atom at the first barrier layer 212(and the first high-K gate dielectric layer 211) in storage capacity substantially do not affect, if and flow is less than 10sccm, then possibly cannot at the first barrier layer 212(and the first high-K gate dielectric layer 211) store enough oxygen atoms.
In the present embodiment, when described air storage annealing in process is oxygen annealing process, the temperature range adopted is 500 DEG C ~ 1500 DEG C, temperature is too low, oxygen atom does not have enough energy to enter the first barrier layer 212(and the first high-K gate dielectric layer 211) in, temperature is too high, and oxygen atom energy is too large, and oxygen atom may again from the first barrier layer 212(and the first high-K gate dielectric layer 211) overflow.
In the present embodiment, when described air storage annealing in process is oxygen annealing process, the annealing time scope of employing can be 1s ~ 600s.In the time range of 1s ~ 600s, annealing time is longer, subsequent storage is at the first barrier layer 212(and the first high-K gate dielectric layer 211) oxygen atom more, more contribute to the work function improving follow-up workfunction layers, but, annealing is more than after 600s, on oxygen atom at the first barrier layer 212(and the first high-K gate dielectric layer 211) in storage capacity substantially do not affect, if and annealing time is less than 1s, then possibly cannot at the first barrier layer 212(and the first high-K gate dielectric layer 211) store enough oxygen atoms.
In the present embodiment, when described air storage annealing in process is helium annealing in process, the helium gas flow scope of employing is 10sccm ~ 1000sccm.In 10sccm ~ 1000sccm range of flow, helium gas flow is larger, subsequent storage is at the first barrier layer 212(and the first high-K gate dielectric layer 211) helium atom more, more contribute to the work function improving follow-up workfunction layers, but, after flowing exceed 1000sccm, on helium atom at the first barrier layer 212(and the first high-K gate dielectric layer 211) in storage capacity substantially do not affect, if and flow is less than 10sccm, then possibly cannot at the first barrier layer 212(and the first high-K gate dielectric layer 211) store enough helium atoms.
In the present embodiment, when described air storage annealing in process is helium annealing in process, the temperature range adopted is 100 DEG C ~ 400 DEG C, temperature is too low, helium atom does not have enough energy to enter the first barrier layer 212(and the first high-K gate dielectric layer 211) in, temperature is too high, and helium atom energy is too large, and helium atom may again from the first barrier layer 212(and the first high-K gate dielectric layer 211) overflow.
In the present embodiment, when described air storage annealing in process is helium annealing in process, the annealing time scope of employing can be 10s ~ 600s.In the time range of 10s ~ 600s, annealing time is longer, subsequent storage is at the first barrier layer 212(and the first high-K gate dielectric layer 211) helium atom more, more contribute to the work function improving follow-up workfunction layers, but, annealing is more than after 600s, on helium atom at the first barrier layer 212(and the first high-K gate dielectric layer 211) in storage capacity substantially do not affect, if and annealing time is less than 1s, then possibly cannot at the first barrier layer 212(and the first high-K gate dielectric layer 211) store enough helium atoms.
Please refer to Fig. 9, carry out above-mentioned after, remove mask layer 202 shown in Fig. 8.
In this enforcement, when mask layer 202 is metal compound layer, flatening process can be adopted to remove mask layer 202.And when mask layer 202 is photoresist, cineration technics can be adopted to remove.
Please continue to refer to Fig. 9, after removal mask layer 202, remove the second dummy grid 223 shown in Fig. 8 and form the second groove 224.
In the present embodiment, wet-etching technology can be adopted to remove the second dummy grid 223.
Please refer to Figure 10, shown in Fig. 9, the bottom of the first groove 214 and sidewall form the first workfunction layers 215, and shown in Fig. 9, the bottom of the second groove 224 and sidewall form the second workfunction layers 225.
In the present embodiment, simultaneously the first workfunction layers 215 and the second workfunction layers 225 formed, and namely adopt same material and same process step to be formed, concrete, described material can be ramet or tungsten carbide (i.e. the metal level of carbon doping).
Namely second workfunction layers 225 work function originally meets the making demand of nmos pass transistor.And for the first workfunction layers 215 be formed on the first barrier layer 212, it is inner that oxygen atom in first barrier layer 212 and the first high-K gate dielectric layer 211 or nitrogen-atoms can be diffused into the first workfunction layers 215, and the first workfunction layers 215 work function is raised.And, according to the regulation and control of above-mentioned annealing temperature, gas flow and annealing time, the work function added value of the first workfunction layers 215 can be made to control between 10mV ~ 1000mV, and usually between nmos pass transistor and the workfunction layers of PMOS transistor work function be only 300mV ~ 400mV, therefore, by above-mentioned air storage annealing in process, can ensure that the work function of the first workfunction layers 215 is adjusted to the making demand meeting PMOS transistor.
Please continue to refer to Figure 10, adopt metal material to fill the first groove 214 and the second groove 224 shown in full Fig. 9 simultaneously, form the first metal gates 216 and the second metal gates 226.
In the present embodiment, described metal material can be following metal one or a combination set of: copper, ruthenium, palladium, platinum, cobalt, nickel, tungsten, aluminium, titanium, tantalum, hafnium and zirconium.
In the formation method of the metal gates that the present embodiment provides, first air storage annealing in process is carried out to the first barrier layer 212 and the first high-K gate dielectric layer 211, them are made to be rich in oxygen atom or helium atom, then the work function simultaneously forming the first workfunction layers 215 and the second workfunction layers 225, second workfunction layers 225 meets the requirement of nmos pass transistor.And for the first workfunction layers 215, it is formed on the first barrier layer 212 after air storage annealing in process and the first high-K gate dielectric layer 211, the gas atom stayed after annealing in process in the first barrier layer 212 and the first high-K gate dielectric layer 211 can be diffused into its inside, its work function is raised, reach the necessary requirement of PMOS transistor, therefore, only need carry out workfunction layers formation process once, the requirement of PMOS transistor and nmos pass transistor can be met simultaneously, simplify technique, reduce process costs.
Further embodiment of this invention provides the formation method of another metal gates, and described formation method is the formation method of rear high-K metal gate, incorporated by reference to reference to figures 11 to Figure 16.
Please refer to Figure 11, provide Semiconductor substrate 300, Semiconductor substrate 300 has PMOS area (mark) and NMOS area (mark).In Figure 11, Semiconductor substrate 300 left-half region is PMOS area, and Semiconductor substrate 300 right half part is NMOS area.The PMOS area of Semiconductor substrate 300 is formed with the first boundary layer 311 and the first dummy grid 312 from top to bottom.The NMOS area of Semiconductor substrate 300 is formed with second interface layer 321 and the second dummy grid 322 from top to bottom, and Semiconductor substrate 300 also has interlayer dielectric layer 301, and interlayer dielectric layer 301 surface flushes with the first dummy grid 312 and the second dummy grid 322 surface.
In the present embodiment, Semiconductor substrate 300 can be silicon substrate or germanium silicon substrate etc., and also can be semiconductor-on-insulator substrate, the present embodiment be for silicon substrate.Semiconductor substrate 300 provides a carrier for forming various semiconductor device.
In the present embodiment, the first boundary layer 311 and second interface layer 321 can adopt same technique to be made simultaneously, and their material can be silicon dioxide.
In the present embodiment, the material of the first dummy grid 312 and the second dummy grid 322 can be polysilicon, and same technique can be adopted to be made simultaneously.
In the present embodiment, the material of interlayer dielectric layer 301 can be silicon dioxide, forms interlayer dielectric layer 301 by chemical vapour deposition technique.After formation interlayer dielectric layer 301, chemical mechanical planarization method can be adopted to carry out planarization, after planarization, the upper surface of the first dummy grid 312 and the second dummy grid 322 comes out, thus interlayer dielectric layer 301 surface is flushed with the first dummy grid 312 and the second dummy grid 322 surface.
Please refer to Figure 12, remove the first dummy grid 312 shown in Figure 11 and form the first groove 313, remove the second dummy grid 322 shown in Figure 11 and form the second groove 323.
In the present embodiment, the plasma of hydrogen can be adopted, or adopt the hybrid plasma of hydrogen bromide (HBr) and oxygen, remove the first dummy grid 312 and the second dummy grid 322.
Please refer to Figure 13, in the first groove 313 shown in Figure 12, form the first high-K gate dielectric layer 314, first barrier layer 315 and the first packed layer 316, in the second groove 323 shown in Figure 12, form the second high-K gate dielectric layer 324, second barrier layer 325 and the second packed layer 326.
In the present embodiment, first high-K gate dielectric layer 314 and the second high-K gate dielectric layer 324 can adopt same technique to be made simultaneously, and their material can be hafnium oxide, hafnium silicon oxide, lanthana, lanthana aluminium, zirconia, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yittrium oxide, aluminium oxide, lead oxide scandium tantalum or lead niobate zinc etc. one or more.
In the present embodiment, the first barrier layer 315 and the second barrier layer 325 can adopt same technique to be made simultaneously, and their material be specifically as follows titanium nitride and tantalum nitride at least one of them.First barrier layer 315 and the second barrier layer 325 can prevent the final metal gates formed from spreading, thus prevent metal gates from destroying the dielectric property being positioned at high-K gate dielectric layer.
In the present embodiment, the material of the first packed layer 316 and the second packed layer 326 is specifically as follows the silicon oxide layer adopting spin coating proceeding to be formed.
Please refer to Figure 14, the second dummy grid 322 forms mask layer 302, with mask layer 302 for mask, etching removes the first packed layer 316 shown in Figure 13 until again form the first groove 314.
In the present embodiment, mask layer 302 can be photoresist layer, amorphous carbon layer or metal compound layer.When mask layer 302 is metal compound layer, its be specifically as follows titanium nitride and tantalum nitride at least one of them, the stable in properties of titanium nitride and tantalum nitride, and become film uniformity good, therefore can be used for substituting conventional photoresist as mask in the present embodiment.
In the present embodiment, when the first packed layer 316 is the silicon oxide layer adopting spin coating proceeding to be formed, alkyl ammonium hydroxide solution removal first packed layer 316 can be adopted.
In the present embodiment, after formation first groove 314, drying process can also be carried out to the first groove 314, thus prevent impurity residual in the process of removal first dummy grid 312 from causing harmful effect to subsequent technique.
Please refer to Figure 15, air storage annealing in process is carried out to the first high-K gate dielectric layer 314 and the first barrier layer 315.Concrete, described air storage annealing in process can be helium annealing in process or oxygen annealing process.
Material due to the first barrier layer 315 be specifically as follows titanium nitride and tantalum nitride at least one of them, and titanium nitride and tantalum nitride is inner usually can form nitrogen-atoms room (N-vacancy) because of the disappearance of some nitrogen-atoms.Same, the first high-K gate dielectric layer 314 is metal oxide (such as hafnium oxide), and its inner meeting usually form oxygen atom room (O-vacancy) because of the disappearance of some oxygen atom.These nitrogen-atoms rooms and oxygen atom room can by the oxygen atom in environment or helium atom fill (because the size in room conforms to atom size), therefore, when carrying out described helium annealing in process or oxygen annealing process, oxygen atom or helium atom can be packed in corresponding nitrogen-atoms room and oxygen atom room, make to be rich in oxygen atom in the first barrier layer 315 and the first high-K gate dielectric layer 314 or to be rich in helium atom (in Figure 14, represent in the first barrier layer 315 and the first high-K gate dielectric layer 314 with band twill and be rich in oxygen atom or be rich in helium atom).Particularly the first barrier layer 315, because when described helium annealing in process, the first barrier layer 315 is directly exposed in helium atmosphere or oxygen atmosphere, therefore, all atom vacancies in the first barrier layer 315 substantially by oxygen atom or helium atom institute saturated.By oxygen atom or saturated the first barrier layer 315(of helium atom and the first high-K gate dielectric layer 314) temporarily store a large amount of oxygen atoms or helium atom.Follow-up at the first barrier layer 315(and the first high-K gate dielectric layer 314) upper when forming workfunction layers, be stored in the first barrier layer 315(and the first high-K gate dielectric layer 314) oxygen atom or helium atom will be diffused in workfunction layers, the work function of workfunction layers is improved.
In the present embodiment, when described air storage annealing in process is oxygen annealing process, the oxygen flow scope of employing is 10sccm ~ 1000sccm.In 10sccm ~ 1000sccm range of flow, oxygen flow is larger, subsequent storage is at the first barrier layer 315(and the first high-K gate dielectric layer 314) oxygen atom more, more contribute to the work function improving follow-up workfunction layers, but, after flowing exceed 1000sccm, on oxygen atom at the first barrier layer 315(and the first high-K gate dielectric layer 314) in storage capacity substantially do not affect, if and flow is less than 10sccm, then possibly cannot at the first barrier layer 315(and the first high-K gate dielectric layer 314) store enough oxygen atoms.
In the present embodiment, when described air storage annealing in process is oxygen annealing process, the temperature range adopted is 500 DEG C ~ 1500 DEG C, temperature is too low, oxygen atom does not have enough energy to enter the first barrier layer 315(and the first high-K gate dielectric layer 314) in, temperature is too high, and oxygen atom energy is too large, and oxygen atom may again from the first barrier layer 315(and the first high-K gate dielectric layer 314) overflow.
In the present embodiment, when described air storage annealing in process is oxygen annealing process, the annealing time scope of employing can be 1s ~ 600s.In the time range of 1s ~ 600s, annealing time is longer, subsequent storage is at the first barrier layer 315(and the first high-K gate dielectric layer 314) oxygen atom more, more contribute to the work function improving follow-up workfunction layers, but, annealing is more than after 600s, on oxygen atom at the first barrier layer 315(and the first high-K gate dielectric layer 314) in storage capacity substantially do not affect, if and annealing time is less than 1s, then possibly cannot at the first barrier layer 315(and the first high-K gate dielectric layer 314) store enough oxygen atoms.
In the present embodiment, when described air storage annealing in process is helium annealing in process, the helium gas flow scope of employing is 10sccm ~ 1000sccm.In 10sccm ~ 1000sccm range of flow, helium gas flow is larger, subsequent storage is at the first barrier layer 315(and the first high-K gate dielectric layer 314) helium atom more, more contribute to the work function improving follow-up workfunction layers, but, after flowing exceed 1000sccm, on helium atom at the first barrier layer 315(and the first high-K gate dielectric layer 314) in storage capacity substantially do not affect, if and flow is less than 10sccm, then possibly cannot at the first barrier layer 315(and the first high-K gate dielectric layer 314) store enough helium atoms.
In the present embodiment, when described air storage annealing in process is helium annealing in process, the temperature range adopted is 100 DEG C ~ 400 DEG C, temperature is too low, helium atom does not have enough energy to enter the first barrier layer 315(and the first high-K gate dielectric layer 314) in, temperature is too high, and helium atom energy is too large, and helium atom may again from the first barrier layer 315(and the first high-K gate dielectric layer 314) overflow.
In the present embodiment, when described air storage annealing in process is helium annealing in process, the annealing time scope of employing can be 10s ~ 600s.In the time range of 10s ~ 600s, annealing time is longer, subsequent storage is at the first barrier layer 315(and the first high-K gate dielectric layer 314) helium atom more, more contribute to the work function improving follow-up workfunction layers, but, annealing is more than after 600s, on helium atom at the first barrier layer 315(and the first high-K gate dielectric layer 314) in storage capacity substantially do not affect, if and annealing time is less than 1s, then possibly cannot at the first barrier layer 315(and the first high-K gate dielectric layer 314) store enough helium atoms.
Please continue to refer to Figure 15, remove mask layer 302 shown in Figure 14.
In this enforcement, when mask layer 302 is metal compound layer, flatening process can be adopted to remove mask layer 302.And when mask layer 302 is photoresist, cineration technics can be adopted to remove.
Please continue to refer to Figure 15, remove the second packed layer 326 shown in Figure 14.
Please refer to Figure 16, shown in Figure 15, the bottom of the first groove 313 and sidewall form the first workfunction layers 317, form the second workfunction layers 327 in the bottom of the second groove 323 and sidewall.
In the present embodiment, simultaneously the first workfunction layers 317 and the second workfunction layers 327 formed, and namely adopt same material and same process step to be formed, concrete, described material can be ramet or tungsten carbide (i.e. the metal level of carbon doping).
Namely second workfunction layers 327 work function originally meets the making demand of nmos pass transistor.And for the first workfunction layers 317 be formed on the first barrier layer 315, it is inner that the oxygen atom of the first barrier layer 315 and the first high-K gate dielectric layer 314 or nitrogen-atoms can be diffused into the first workfunction layers 317, and the first workfunction layers 317 work function is raised.And, according to the regulation and control of above-mentioned annealing temperature, gas flow and annealing time, the work function added value of the first workfunction layers 317 can be made to control between 10mV ~ 1000mV, and usually between nmos pass transistor and the workfunction layers of PMOS transistor work function be only 300mV ~ 400mV, therefore, by above-mentioned air storage annealing in process, can ensure that the work function of the first workfunction layers 317 is adjusted to the making demand meeting PMOS transistor.
Please continue to refer to Figure 16, adopt metal material to fill the first groove 313 and the second groove 323 shown in full Figure 15 simultaneously, form the first metal gates 318 and the second metal gates 328.
In the present embodiment, described metal material can be following metal one or a combination set of: copper, ruthenium, palladium, platinum, cobalt, nickel, tungsten, aluminium, titanium, tantalum, hafnium and zirconium.
In the formation method of the metal gates that the present embodiment provides, first air storage annealing in process is carried out to the first barrier layer 315 and the first high-K gate dielectric layer 314, them are made to be rich in oxygen atom or helium atom, then the work function simultaneously forming the first workfunction layers 317 and the second workfunction layers 327, second workfunction layers 327 meets the requirement of nmos pass transistor.And for the first workfunction layers 317, it is formed on the first barrier layer 315 after air storage annealing in process and the first high-K gate dielectric layer 314, the gas atom stayed after annealing in process in the first barrier layer 3153 and the first high-K gate dielectric layer 314 can be diffused into its inside, its work function is raised, reach the necessary requirement of PMOS transistor, therefore, only need carry out workfunction layers formation process once, the requirement of PMOS transistor and nmos pass transistor can be met simultaneously, simplify technique, save process costs.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a formation method for metal gates, is characterized in that, comprising:
Semiconductor substrate is provided, described Semiconductor substrate has PMOS area and NMOS area, described PMOS area is formed with the first high-K gate dielectric layer, the first barrier layer and the first dummy grid from top to bottom, described NMOS area is formed with the second high-K gate dielectric layer, the second barrier layer and the second dummy grid from top to bottom, described Semiconductor substrate also has interlayer dielectric layer, and described interlayer dielectric layer surface flushes with described first dummy grid and described second dummy grid surface;
Remove described first dummy grid and form the first groove;
Air storage annealing in process is carried out to described first barrier layer and described first high-K gate dielectric layer;
Remove described second dummy grid and form the second groove;
Form workfunction layers in the bottom of described first groove and described second groove and sidewall simultaneously;
Adopt metal material to fill completely described first groove and described second groove simultaneously.
2. the formation method of metal gates as claimed in claim 1, it is characterized in that, described air storage annealing in process is helium annealing in process or oxygen annealing process.
3. the formation method of metal gates as claimed in claim 1, is characterized in that, the temperature range that described oxygen annealing process adopts is 100 DEG C ~ 400 DEG C, and the oxygen flow scope of employing is 10sccm ~ 1000sccm, and the annealing time of employing is 1s ~ 600s.
4. the formation method of metal gates as claimed in claim 1, is characterized in that, the temperature range that described helium annealing in process adopts is 500 DEG C ~ 1500 DEG C, and the helium gas flow scope of employing is 10sccm ~ 1000sccm, and the annealing time of employing is 10s ~ 600s.
5. the formation method of metal gates as claimed in claim 1, is characterized in that, after described first groove of formation, and before carrying out described helium annealing in process, described formation method also comprises: carry out drying process.
6. a formation method for metal gates, is characterized in that, comprising:
Semiconductor substrate is provided, described Semiconductor substrate has PMOS area and NMOS area, described PMOS area is formed with the first boundary layer and the first dummy grid from top to bottom, described NMOS area is formed with second interface layer and the second dummy grid from top to bottom, described Semiconductor substrate also has interlayer dielectric layer, and described interlayer dielectric layer surface flushes with described first dummy grid and described second dummy grid surface;
Remove described first boundary layer and described first dummy grid forms the first groove, remove described second interface layer and described second dummy grid forms the second groove;
In described first groove, form the first high-K gate dielectric layer, the first barrier layer and the first packed layer, in described second groove, form the second high-K gate dielectric layer, the second barrier layer and the second packed layer;
Remove described first packed layer until again form described first groove;
Air storage annealing in process is carried out to described first high-K gate dielectric layer and described first barrier layer;
Remove described second packed layer until again form described second groove;
Form workfunction layers in the bottom of described first groove and described second groove and sidewall simultaneously;
Adopt metal material to fill completely described first groove and described second groove simultaneously.
7. the formation method of metal gates as claimed in claim 6, it is characterized in that, described air storage annealing in process is helium annealing in process or oxygen annealing process.
8. the formation method of metal gates as claimed in claim 6, is characterized in that, the temperature range that described oxygen annealing process adopts is 100 DEG C ~ 400 DEG C, and the oxygen flow scope of employing is 10sccm ~ 1000sccm, and the annealing time of employing is 1s ~ 600s.
9. the formation method of metal gates as claimed in claim 6, is characterized in that, the temperature range that described helium annealing in process adopts is 500 DEG C ~ 1500 DEG C, and the helium gas flow scope of employing is 10sccm ~ 1000sccm, and the annealing time of employing is 10s ~ 600s.
10. the formation method of metal gates as claimed in claim 6, is characterized in that, after described first groove of formation, and before carrying out described helium annealing in process, described formation method also comprises: carry out drying process.
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