CN103066019B - Complementary metal-oxide-semiconductor transistor (CMOS) and manufacturing method thereof, and N-channel metal oxide semiconductor field effect transistor (NMOS) and manufacturing method thereof - Google Patents

Complementary metal-oxide-semiconductor transistor (CMOS) and manufacturing method thereof, and N-channel metal oxide semiconductor field effect transistor (NMOS) and manufacturing method thereof Download PDF

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CN103066019B
CN103066019B CN201110318999.0A CN201110318999A CN103066019B CN 103066019 B CN103066019 B CN 103066019B CN 201110318999 A CN201110318999 A CN 201110318999A CN 103066019 B CN103066019 B CN 103066019B
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described
workfunction layers
manufacture method
transistor
dielectric layer
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CN201110318999.0A
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CN103066019A (en
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平延磊
鲍宇
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中芯国际集成电路制造(上海)有限公司
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Abstract

Disclosed are a complementary metal-oxide-semiconductor transistor (CMOS) and a manufacturing method thereof, and an N-channel metal oxide semiconductor field effect transistor (NMOS) and a manufacturing method thereof. The manufacturing method of the CMOS includes the following steps: supplying a semiconductor substrate which comprises an NMOS region and a PMOS region; forming a gate dielectric layer on the semiconductor substrate; forming a work function metal layer on the gate dielectric layer, wherein the work function of the work function metal layer is placed in the range of the work function of the PMOS; injecting of N type ions into the corresponding work function metal layer in the NMOS region; forming a polycrystalline silicon layer on the work function metal layer; and respectively etching the polycrystalline silicon layer, the work function metal layer and the gate dielectric layer so as to form a gate structure corresponding to the NMOS region and a gate structure corresponding to the PMOS region. In the using process of gate-first manufacturing technology, the work function of metal grid electrodes can be controlled stably and accurately, and so that the transistors can be provided with threshold voltages which are stable in performance.

Description

CMOS transistor and manufacture method, nmos pass transistor and manufacture method

Technical field

The present invention relates to IC manufacturing field, particularly relate to a kind of CMOS transistor and manufacture method, nmos pass transistor and manufacture method.

Background technology

The main devices of integrated circuit especially very lagre scale integrated circuit (VLSIC) is metal-oxide semiconductor fieldeffect transistor (MOS transistor).Since MOS transistor invention, its physical dimension is constantly reducing according to Moore's Law always, its characteristic size development has at present entered 45 nanometer range, under this yardstick, the second-order effect that the physics limit of various because device is brought is inevitable gradually, and the characteristic size of device is scaled becomes more and more difficult.Wherein, manufacture field at MOS transistor device and circuit thereof, most is challenging be traditional cmos process in the scaled process of device due to polysilicon, SiO 2or SiON gate dielectric layer thickness reduces the leakage problem from grid to substrate brought.

The current solution proposed in CMOS technology is, adopts high K (dielectric constant) gate dielectric material to replace traditional SiO 2gate medium, and use metal to match to avoid grid loss and boron to permeate the leakage problem caused as gate electrode.The research of current high-K gate dielectric material is comparatively ripe, multiselect with hafnium sill (as HfO 2deng), and be positioned at the Material selec-tion of the gate electrode on gate dielectric layer and preparation technology still immature.

The technology of preparing of current existing a kind of metal gate electrode is: use two kinds of metals that work function is adjustable, respectively as the gate electrode of nmos pass transistor in CMOS technology and PMOS transistor, the cmos device of such formation because possess more excellent device performance, and be easy to existing CMOS technology compatible and accept extensively by industry.

In prior art, the manufacture method of metal gates is mainly divided into first grid (Gate-first) and post tensioned unbonded prestressed concrete (Gate-last) two kinds.Wherein, post tensioned unbonded prestressed concrete manufacture craft more complicated, and lower than first gate fabrication process under the tube core density equal conditions of chip, specifically can with reference to the formation method of metal gate electrode in a kind of CMOS technology disclosed in US Patent No. 6586288.And the key issue of first gate fabrication process is the threshold voltage controlling PMOS transistor.

By making the metal gates of transistor be in respective workfunction range, transistor finally can be made to reach the threshold voltage Vt of its expection.In order to obtain threshold voltage Vt, in PMOS transistor, the workfunction range of metal gates can between 4.8eV ~ 5.1eV, and in nmos pass transistor, the workfunction range of metal gates can be positioned at about 4.0eV ~ 4.3eV.

Figure 1 shows that a kind of structural representation of CMOS transistor of prior art, described CMOS transistor comprises: nmos pass transistor and PMOS transistor, wherein:

Described nmos pass transistor comprises: the first source region 61 and the first drain region 71 being arranged in described Semiconductor substrate nmos transistor region 11; Be positioned at the first grid structure on described nmos transistor region 11, described first grid structure comprises: the first grid dielectric layer 21 being positioned at the high K dielectric on described nmos transistor region 11, be positioned at the first workfunction layers 31 on described first grid dielectric layer 21, the material of described first workfunction layers 31 is lanthana (LaO), is positioned at the first polysilicon layer 41 in described first workfunction layers 31; Be positioned at the first side wall 51 of described first grid structure periphery;

Described PMOS transistor comprises: the second source region 62 and the second drain region 72 being arranged in described Semiconductor substrate PMOS transistor region 12; Be positioned at the second grid structure on described PMOS transistor region 12, described second grid structure comprises: the second gate dielectric layer 22 being positioned at the high K dielectric on described PMOS transistor region 12, be positioned at the second workfunction layers 32 on described second gate dielectric layer 22, the material of described second workfunction layers 32 is aluminium oxide (Al 2o 3), be positioned at the second polysilicon layer 42 in described second workfunction layers 32; Be positioned at the second side wall 52 of described second grid structure periphery;

Described nmos transistor region 11 and described PMOS transistor region 12 are isolated by fleet plough groove isolation structure 13.

In above-mentioned transistor arrangement, PMOS transistor carries out work function adjustment by described second workfunction layers 32 (that is: aluminium oxide), nmos pass transistor carries out work function adjustment by described first workfunction layers 31 (that is: lanthana), thus makes the threshold voltage that PMOS transistor and nmos pass transistor reach respective respectively.

When adopting the CMOS transistor shown in first grid technology construction drawing 1, mainly comprise the following steps:

There is provided Semiconductor substrate, described Semiconductor substrate comprises nmos transistor region and PMOS transistor region, and described nmos transistor region and described PMOS transistor region are isolated by a fleet plough groove isolation structure;

Form the gate dielectric layer of high K dielectric on the semiconductor substrate;

On described gate dielectric layer, deposition forms alumina layer, and removes alumina layer corresponding to described nmos transistor region;

Deposition forms the lanthana layer covering described aluminium oxide and described gate dielectric layer, and removes lanthana layer corresponding on described alumina layer;

Remaining described alumina layer and remaining described lanthana layer form polysilicon layer;

Etch described polysilicon layer, lanthana layer, alumina layer and gate dielectric layer, form the grid structure of the nmos pass transistor be positioned on described nmos transistor region respectively, be positioned at the grid structure of the PMOS transistor on described PMOS transistor region;

Form the side wall around two described grid structures respectively;

Respectively with two side walls for mask, in described nmos transistor region and described PMOS transistor region, carry out heavy doping ion injection, form the first source/drain region and the second source/drain region.

So far, the CMOS transistor shown in Fig. 1 is obtained.

In prior art, described first workfunction layers 31 and described second workfunction layers 32 need by chemical vapour deposition (CVD) (chemical vapor deposition, or physical vapour deposition (PVD) (PhysicalVapor Deposition CVD), etc. PVD) deposition process is formed, thus the work function of workfunction layers is wayward, accuracy is lower, finally causes the threshold voltage of MOS transistor unstable.

Therefore, how in the process of first gate fabrication process, the more stable work function controlling metal gates exactly just becomes those skilled in the art's problem demanding prompt solution.

Summary of the invention

The problem that the present invention solves is to provide a kind of CMOS transistor and manufacture method, nmos pass transistor and manufacture method, with in the process adopting first gate fabrication process, the more stable work function controlling metal gates exactly, makes transistor have the threshold voltage of stable performance.

In order to solve the problem, the invention provides a kind of manufacture method of CMOS transistor, comprising:

There is provided Semiconductor substrate, described Semiconductor substrate comprises: nmos transistor region and PMOS transistor region;

Form gate dielectric layer on the semiconductor substrate;

Described gate dielectric layer forms workfunction layers, and the work function of described workfunction layers is positioned at PMOS transistor workfunction range;

N-type ion implantation is carried out in the workfunction layers that described nmos transistor region is corresponding;

Described workfunction layers forms polysilicon layer;

Etch described polysilicon layer, workfunction layers and the gate dielectric layer on described nmos transistor region and described PMOS transistor region respectively, form grid structure corresponding to grid structure corresponding to nmos transistor region and PMOS transistor region.

Alternatively, the material of described gate dielectric layer is high K dielectric material.

Alternatively, described gate dielectric layer adopts ALD (Atomic Layer Deposition, ald) or CVD method to be formed.Alternatively, the thickness range of described gate dielectric layer comprises:

Alternatively, the manufacture method of described CMOS transistor also comprises: after the described workfunction layers of formation, carry out rapid thermal oxidation process or/and processed by rapid thermal nitridation.

Alternatively, the work function of described workfunction layers is more than or equal to 4.8eV and is less than or equal to 5.1eV.

Alternatively, the material of described workfunction layers comprises: tantalum nitride (TaN) or titanium nitride (TiN).Alternatively, the thickness range of described workfunction layers comprises:

Alternatively, described workfunction layers adopts ALD or PVD method to be formed.

Alternatively, the temperature range forming described workfunction layers comprises: 300 DEG C ~ 500 DEG C.

Alternatively, described N-type ion implantation comprises injection arsenic (As) ion, antimony (Sb) ion or tellurium (Te) ion.

Alternatively, the energy range of described N-type ion implantation comprises: 0.6KeV ~ 25KeV.

Alternatively, the dosage range of described N-type ion implantation comprises: 1E15/ square centimeter ~ 1E16/ square centimeter.

Alternatively, the manufacture method of described CMOS transistor also comprises: after the described grid structure of formation, form the side wall be positioned in Semiconductor substrate respectively around each grid structure; With described side wall for mask, carry out heavy doping ion injection, in described nmos transistor region, form the first source/drain region, and form the second source/drain region in described PMOS transistor region.

Alternatively, the manufacture method of described CMOS transistor also comprises: after described first source/drain region of formation and the second source/drain region, carry out spike annealing (Spike anneal).

In order to solve the problem, present invention also offers a kind of CMOS transistor adopting the manufacture method of above-mentioned CMOS transistor to make.

In order to solve the problem, present invention also offers a kind of manufacture method of nmos pass transistor, comprising:

Semiconductor substrate is provided;

Form gate dielectric layer on the semiconductor substrate;

Described gate dielectric layer forms workfunction layers, and the work function of described workfunction layers is positioned at PMOS transistor workfunction range;

N-type ion implantation is carried out in described workfunction layers;

Described workfunction layers forms polysilicon layer;

Etch described polysilicon layer, workfunction layers and gate dielectric layer, form grid structure.

Alternatively, the work function of described workfunction layers is more than or equal to 4.8eV and is less than or equal to 5.1eV.

Alternatively, the material of described workfunction layers comprises: tantalum nitride or titanium nitride.

Alternatively, described N-type ion implantation comprises injection arsenic ion, antimony ion or tellurium ion.

In order to solve the problem, present invention also offers a kind of nmos pass transistor adopting the manufacture method of above-mentioned nmos pass transistor to make.

Compared with prior art, the invention has the advantages that:

1) a kind of CMOS transistor and manufacture method is provided, gate dielectric layer forms workfunction layers, the work function of described workfunction layers is positioned at PMOS transistor workfunction range, and this workfunction layers can meet the requirement of PMOS transistor threshold voltage; N-type ion implantation is carried out in the workfunction layers that nmos transistor region is corresponding, thus the requirement of nmos pass transistor threshold voltage can be met by the N-type ion injected, wherein the mode of ion implantation is simple and easy to control, by the accurate control to injection ion, can realize accurately controlling the stable of its work function size, finally ensure that the stability of nmos pass transistor and PMOS transistor performance.

2) similarly, provide a kind of nmos pass transistor and manufacture method, the requirement of nmos pass transistor threshold voltage is met by the N-type ion injected, wherein the mode of ion implantation is simple and easy to control, by the accurate control to injection ion, can realize accurately controlling the stable of its work function size, finally ensure that the stability of nmos pass transistor performance.

Accompanying drawing explanation

Fig. 1 is a kind of structural representation of CMOS transistor of prior art;

Fig. 2 is the schematic flow sheet of the manufacture method of the embodiment of the present invention one CMOS transistor;

Fig. 3 A to Fig. 3 K is the schematic diagram of the manufacture method of the embodiment of the present invention one CMOS transistor;

Fig. 4 is the schematic flow sheet of the manufacture method of embodiment of the present invention bi-NMOS transistor;

Fig. 5 is the schematic diagram of the manufacture method of embodiment of the present invention bi-NMOS transistor.

Embodiment

For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.

Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, therefore the present invention is not by the restriction of following public specific embodiment.

As described in background, in prior art, nmos pass transistor and workfunction layers corresponding to PMOS transistor are formed respectively by deposition process, thus the work function of workfunction layers is wayward, accuracy is lower, finally causes the threshold voltage of MOS transistor unstable.

For overcoming above-mentioned defect, the invention provides a kind of CMOS transistor and manufacture method, nmos pass transistor and manufacture method, with in the process adopting first gate fabrication process, the more stable work function controlling metal gates exactly, makes transistor have the threshold voltage of stable performance.

Be described in detail below in conjunction with accompanying drawing.

Embodiment one

Shown in figure 2, present embodiments provide a kind of manufacture method of CMOS transistor, comprising:

Step S11, provides Semiconductor substrate, and described Semiconductor substrate comprises: nmos transistor region and PMOS transistor region;

Step S12, forms gate dielectric layer on the semiconductor substrate;

Step S13, described gate dielectric layer forms workfunction layers, and the work function of described workfunction layers is positioned at PMOS transistor workfunction range;

Step S14, carries out N-type ion implantation in the workfunction layers that described nmos transistor region is corresponding;

Step S15, described workfunction layers forms polysilicon layer;

Step S16, etches described polysilicon layer, workfunction layers and the gate dielectric layer on described nmos transistor region and described PMOS transistor region respectively, forms grid structure corresponding to grid structure corresponding to nmos transistor region and PMOS transistor region.

First perform step S11, as shown in Figure 3A, provide Semiconductor substrate, described Semiconductor substrate can be P type, can be also N-type, be illustrated in the present embodiment for P type.Described Semiconductor substrate is divided into nmos transistor region 110 and PMOS transistor region 120, is isolated by fleet plough groove isolation structure 130 between shown nmos transistor region 110 and PMOS transistor region 120.

N trap (not shown) can also be formed with in described PMOS transistor region 110, in nmos transistor region 120, also can be formed with P trap (not shown).

Then perform step S12, as shown in Figure 3 B, form gate dielectric layer 200 on the semiconductor substrate.

The material of described gate dielectric layer 200 can be the traditional gate dielectric material such as silicon dioxide, also can be high K dielectric material.Preferably, the material of gate dielectric layer 200 described in the present embodiment is high K dielectric material, concrete as hafnium oxide, hafnium silicon oxide, lanthana, lanthana aluminium, zirconia, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yittrium oxide, aluminium oxide, lead oxide scandium tantalum or lead niobate zinc.

Described gate dielectric layer 200 can be formed by ALD or CVD method, and it is known for those skilled in the art, therefore does not repeat them here.

The thickness range of described gate dielectric layer 200 can comprise: as: or deng.

Then perform step S13, as shown in Figure 3 C, described gate dielectric layer 200 forms workfunction layers 300.

Nmos pass transistor work function refers to the work function that can meet the requirement of nmos pass transistor threshold voltage, specifically can be positioned at 4.0eV ~ 4.3eV; PMOS transistor work function refers to the work function that can meet the requirement of PMOS transistor threshold voltage, specifically can be positioned at 4.8eV ~ 5.1eV; The arithmetic mean scope of nmos pass transistor work function and PMOS transistor work function specifically can be positioned at 4.6eV ~ 4.8eV.It should be noted that, above numerical value is only citing, and it should not limit the scope of the invention.

The work function of described workfunction layers 300 should meet the work function requirement of PMOS transistor, and namely the work function of described workfunction layers 300 should be more than or equal to 4.8eV and be less than or equal to 5.1eV, as: 4.8eV, 4.9eV, 5.0eV or 5.1eV.

The material of described workfunction layers 300 specifically can select titanium nitride or tantalum nitride.The material of workfunction layers 300 described in the present embodiment is titanium nitride.Because the work function of titanium nitride and its thickness have relation, at a certain temperature, the thickness of titanium nitride is larger, and its work function is larger.Be more than or equal to 4.8eV and the requirement being less than or equal to 5.1eV to meet work function, in the present embodiment, the thickness range of workfunction layers 300 can comprise as: or deng.

Described workfunction layers 300 can adopt ALD or PVD method to be formed, the temperature range wherein forming described workfunction layers 300 can comprise 300 DEG C ~ 500 DEG C, as: 300 DEG C, 340 DEG C, 400 DEG C, 450 DEG C or 500 DEG C etc., its concrete formation process is known for those skilled in the art, does not repeat them here.

Preferably, after the described workfunction layers 300 of formation, rapid thermal oxidation (Rapid Thermal Oxidation, RTO) process can also be carried out or/and Rapid Thermal Nitrided (Rapid ThermalNitridation, RTN) process.Described rapid thermal oxidation refers to and carries out quick thermal annealing process, passes into oxygen simultaneously; Described Rapid Thermal Nitrided refers to carries out quick thermal annealing process, passes into nitrogen simultaneously.

Be more than or equal to 4.8eV and the workfunction layers 300 being less than or equal to 5.1eV by forming work function on the gate dielectric layer 200 of PMOS transistor region 120 correspondence in the present embodiment, thus meet the requirement of PMOS transistor gate work-function; By RTO process or/and RTN process, the gate work-function of PMOS transistor is obtained further stable.

Then perform step S14, in the workfunction layers 300 of described nmos transistor region 110 correspondence, carry out N-type ion implantation, specifically comprise:

Shown in figure 3D, described workfunction layers 300 forms hard mask layer 400, the material of described hard mask layer 400 can be indefinite form silicon.

Shown in figure 3E, photoetching treatment is carried out to described hard mask layer 400, remove hard mask layer 400 corresponding on described nmos transistor region 110, retain hard mask layer 400 corresponding on described PMOS transistor region 120.

Shown in figure 3F, with remaining hard mask layer 400 for mask, carry out ion implantation, the described ion of injection is arranged in the workfunction layers 300 of described nmos transistor region 110 correspondence.

Shown in figure 3G, remove in remaining described hard mask layer 400, Fig. 3 G the ion that representative is injected.

Described N-type ion implantation can comprise injects arsenic ion, antimony ion or tellurium ion, and the ion injected in the present embodiment is arsenic ion.

The energy range of described N-type ion implantation comprises: 0.6KeV ~ 25KeV, as: 0.6KeV, 3KeV, 8KeV, 15KeV or 25KeV etc.The ion of described injection finally can be arranged in the workfunction layers 300 of described nmos transistor region 110 correspondence, is especially positioned at the workfunction layers 300 of described nmos transistor region 110 correspondence and the intersection of gate dielectric layer 200.

The dosage range of described N-type ion implantation comprises: 1E15/ square centimeter ~ 1E16/ square centimeter, as: 1E15/ square centimeter, 5 × 1E15/ square centimeter or 1E16/ square centimeter.

By injecting arsenic ion, antimony ion or tellurium ion in the workfunction layers 300 of nmos transistor region 110 correspondence in the present embodiment, thus make the work function comprising the workfunction layers 300 injecting ion can meet the requirement of nmos pass transistor gate work-function, the ion injected can reduce the work function of workfunction layers 300, and the work function namely comprising the workfunction layers 300 of arsenic ion, antimony ion or tellurium ion is positioned at the scope of 4.0eV ~ 4.3eV.

Then perform step S15, shown in figure 3H, described workfunction layers 300 forms polysilicon layer 500.

Described polysilicon layer 500 can adopt PVD or CVD method to be formed, and it is known for those skilled in the art, does not repeat them here.

Then perform step S16, etch the described polysilicon layer 500 of described nmos transistor region 110 correspondence, workfunction layers 300 and gate dielectric layer 200 successively, form the first grid structure of nmos transistor region 110 correspondence; Etch the described polysilicon layer 500 of described PMOS transistor region 120 correspondence, workfunction layers 300 and gate dielectric layer 200 successively, form the second grid structure of PMOS transistor region 120 correspondence.

Described first grid structure and described second grid structure can be formed simultaneously, also can successively be formed.

Shown in figure 3I, described first grid structure comprises successively: be positioned at first grid dielectric layer 210, first workfunction layers 310 on described nmos transistor region 110 and the first polysilicon layer 510; Described second grid structure comprises successively: be positioned at second grid dielectric layer 220, second workfunction layers 320 on described PMOS transistor region 120 and the second polysilicon layer 520.

The method of concrete formation grid structure is same as the prior art, does not repeat them here.

After the described first grid structure of formation and second grid structure, can also following steps be performed:

Shown in figure 3J, around described first grid structure, form the first side wall 610 be positioned on described nmos transistor region 110, around described second grid structure, form the second side wall 620 be positioned on described PMOS transistor region 120.

Shown in figure 3K, after formation first side wall 610 and the second side wall 620, can also with described first side wall 610 for mask, carry out heavy doping ion injection, in described nmos transistor region 110, form the first source region 710 and the first drain region 810, and in described PMOS transistor region 120, form the second source region 720 and the second drain region 820.

Finally, spike annealing can also be carried out, to activate the Doped ions in the first source region, drain region 810, second, source region 710, first 720 and the second drain region 820.

It should be noted that, before described first side wall 610 of formation and the second side wall 620, light dope ion implantation can also be carried out in described nmos transistor region 110, form the first source/drain extension area; And light dope ion implantation is carried out in described PMOS transistor region 120, form the second source/drain extension area.

So far, making obtains the CMOS transistor comprising nmos pass transistor and PMOS transistor.

The present embodiment forms workfunction layers 300 on gate dielectric layer 200, and the work function of described workfunction layers 300 is more than or equal to 4.8eV and is less than or equal to 5.1eV, and this workfunction layers can meet the requirement of PMOS transistor threshold voltage; N-type ion implantation is carried out in the workfunction layers 300 of nmos transistor region 110 correspondence, thus the requirement of nmos pass transistor threshold voltage can be met by the N-type ion injected, wherein the mode of ion implantation is simple and easy to control, by the accurate control to injection ion, can realize accurately controlling the stable of its work function size, finally ensure that the stability of nmos pass transistor and PMOS transistor performance.

Embodiment two

Shown in figure 4, present embodiments provide a kind of manufacture method of nmos pass transistor, comprising:

Step S31, provides Semiconductor substrate;

Step S32, forms gate dielectric layer on the semiconductor substrate;

Step S33, described gate dielectric layer forms workfunction layers, and the work function of described workfunction layers is positioned at PMOS transistor workfunction range;

Step S34, carries out N-type ion implantation in described workfunction layers;

Step S35, described workfunction layers forms polysilicon layer;

Step S36, etches described polysilicon layer, workfunction layers and gate dielectric layer, forms grid structure.

Shown in figure 5, adopt the present embodiment method to make the nmos pass transistor obtained and comprise:

Semiconductor substrate 211;

Be positioned at the grid structure in described Semiconductor substrate 211, described grid structure comprises: be positioned at the gate dielectric layer 221 in described Semiconductor substrate 211; Be positioned at the workfunction layers 231 on described gate dielectric layer 221; Be positioned at the polysilicon layer 251 in described workfunction layers 231; The work function of described workfunction layers 231 is more than or equal to 4.8eV and is less than or equal to 5.1eV, described workfunction layers 231 comprise Doped ions (in Fig. 5 with represent).

Wherein, the thickness range of described gate dielectric layer 221 can comprise:

Wherein, the work function of described workfunction layers 231 can be more than or equal to 4.8eV and be less than or equal to 5.1eV.As: as described in the material of workfunction layers 231 can comprise: tantalum nitride or titanium nitride.

Particularly, described workfunction layers 231 can adopt ALD or PVD method to be formed, and the temperature range forming described workfunction layers 231 can comprise 300 DEG C ~ 500 DEG C.

Particularly, the thickness of described workfunction layers 231 can scope comprise:

Wherein, the manufacture method of described nmos pass transistor can also comprise: after the described workfunction layers 231 of formation, carry out rapid thermal oxidation process or/and processed by rapid thermal nitridation.

Wherein, described N-type ion implantation can comprise injection arsenic ion, antimony ion or tellurium ion.

Particularly, the energy range of described N-type ion implantation can comprise: 0.6KeV ~ 25KeV; The dosage range of described N-type ion implantation can comprise: 1E15/ square centimeter ~ 1E16/ square centimeter.

The manufacture method of nmos pass transistor described in the present embodiment can also comprise: around described grid structure, form the side wall 261 be positioned in described Semiconductor substrate; With described side wall 261 for mask, carry out heavy doping ion injection, in described Semiconductor substrate 211, form source region 271 and drain region 281; Carry out spike annealing, to activate the Doped ions in source region 271 and drain region 281.

The concrete grammar of each step can reference example one, does not repeat them here.

The present embodiment by carrying out N-type ion implantation in workfunction layers 231, thus the work function of the requirement of nmos pass transistor threshold voltage can be met by the N-type ion injected, wherein the mode of ion implantation is simple and easy to control, by the accurate control to injection ion, can realize accurately controlling the stable of its work function size, finally ensure that the stability of nmos pass transistor performance.

Correspondingly, present invention also offers a kind of CMOS transistor adopting the manufacture method of the CMOS transistor of embodiment one to make, specifically please refer to Fig. 3 K, do not repeat them here.

Correspondingly, present invention also offers a kind of nmos pass transistor adopting the manufacture method of the nmos pass transistor of embodiment two to make, specifically please refer to Fig. 5, do not repeat them here.

Although the present invention with preferred embodiment openly as above; but it is not for limiting claim; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible variation and amendment, the scope that therefore protection scope of the present invention should define with the claims in the present invention is as the criterion.

Claims (17)

1. a manufacture method for CMOS transistor, is characterized in that, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate comprises: nmos transistor region and PMOS transistor region;
Form gate dielectric layer on the semiconductor substrate;
Described gate dielectric layer forms workfunction layers, and the work function of described workfunction layers is positioned at PMOS transistor workfunction range;
The material of described workfunction layers is titanium nitride;
In the titanium nitride that described nmos transistor region is corresponding, carry out N-type ion implantation, described N-type ion is Sb, makes described N-type ion be positioned at the intersection of workfunction layers corresponding to described nmos transistor region and gate dielectric layer;
Described workfunction layers forms polysilicon layer;
Etch described polysilicon layer, workfunction layers and the gate dielectric layer on described nmos transistor region and described PMOS transistor region respectively, form grid structure corresponding to grid structure corresponding to nmos transistor region and PMOS transistor region.
2. the manufacture method of CMOS transistor as claimed in claim 1, it is characterized in that, the material of described gate dielectric layer is high K dielectric material.
3. the manufacture method of CMOS transistor as claimed in claim 2, is characterized in that, described gate dielectric layer adopts ALD or CVD method to be formed.
4. the manufacture method of CMOS transistor as claimed in claim 2 or claim 3, it is characterized in that, the thickness range of described gate dielectric layer comprises:
5. the manufacture method of CMOS transistor as claimed in claim 1, it is characterized in that, the manufacture method of described CMOS transistor also comprises: after the described workfunction layers of formation, carry out rapid thermal oxidation process or/and processed by rapid thermal nitridation.
6. the manufacture method of CMOS transistor as claimed in claim 1, it is characterized in that, the work function of described workfunction layers is more than or equal to 4.8eV and is less than or equal to 5.1eV.
7. the manufacture method of CMOS transistor as claimed in claim 1, it is characterized in that, the thickness range of described workfunction layers comprises:
8. the manufacture method of CMOS transistor as claimed in claim 1, is characterized in that, described workfunction layers adopts ALD or PVD method to be formed.
9. the manufacture method of CMOS transistor as claimed in claim 8, it is characterized in that, the temperature range forming described workfunction layers comprises: 300 DEG C ~ 500 DEG C.
10. the manufacture method of CMOS transistor as claimed in claim 1, it is characterized in that, the energy range of described N-type ion implantation comprises: 0.6KeV ~ 25KeV.
The manufacture method of 11. CMOS transistor as claimed in claim 1, it is characterized in that, the dosage range of described N-type ion implantation comprises: 1E15/ square centimeter ~ 1E16/ square centimeter.
The manufacture method of 12. CMOS transistor as claimed in claim 1, it is characterized in that, the manufacture method of described CMOS transistor also comprises: after the described grid structure of formation, form the side wall be positioned in Semiconductor substrate respectively around each grid structure; With described side wall for mask, carry out heavy doping ion injection, in described nmos transistor region, form the first source/drain region, and form the second source/drain region in described PMOS transistor region.
The manufacture method of 13. CMOS transistor as claimed in claim 12, it is characterized in that, the manufacture method of described CMOS transistor also comprises: after described first source/drain region of formation and the second source/drain region, carry out spike annealing.
14. 1 kinds of CMOS transistor adopting the manufacture method of the CMOS transistor according to any one of claim 1 to 13 to make.
The manufacture method of 15. 1 kinds of nmos pass transistors, is characterized in that, comprising:
Semiconductor substrate is provided;
Form gate dielectric layer on the semiconductor substrate;
Described gate dielectric layer forms workfunction layers, and the work function of described workfunction layers is positioned at PMOS transistor workfunction range;
The material of described workfunction layers is titanium nitride;
In described workfunction layers, carry out N-type ion implantation, described N-type ion is Sb, makes described N-type ion be positioned at the intersection of workfunction layers corresponding to described nmos transistor region and gate dielectric layer;
Described workfunction layers forms polysilicon layer;
Etch described polysilicon layer, workfunction layers and gate dielectric layer, form grid structure.
The manufacture method of 16. nmos pass transistors as claimed in claim 15, it is characterized in that, the work function of described workfunction layers is more than or equal to 4.8eV and is less than or equal to 5.1eV.
17. 1 kinds of nmos pass transistors adopting the manufacture method of the nmos pass transistor described in claim 15 or 16 to make.
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